CN111833960A - Method for testing full coverage of large-capacity memory function - Google Patents
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Abstract
The invention relates to a method for testing full coverage of a function of a mass memory, which comprises the following steps: dividing the storage space of a memory; writing an initial test pattern vector; testing the system for the first time; setting a cycle execution condition; generating a new test pattern vector; and modifying the running flow of the test program, circulating for N times, outputting a total test result, and exiting the program. The invention realizes the test by partitioning the large-capacity memory, selecting the first subblock area, automatically modifying the memory test vector of other subblock areas in a high-level language programming mode, and setting the cycle number to realize the full coverage of the function test of the large-capacity memory. The test system only needs to meet the conditions required by the test of the first subblock area, other subblock areas automatically modify the test graphic vectors through the high-level language, and the method for repeatedly executing the test flow does not occupy additional system resources, simplifies the writing of the graphic vectors and flexibly realizes the full coverage of the function test of the large-capacity memory.
Description
Technical Field
The invention relates to memory testing, in particular to a method for testing full coverage of a function of a mass memory.
Background
Improvements in memory fabrication processes and materials have resulted in a dramatic increase in memory capacity, now reaching the TB level. In order to guarantee the long-term reliable operation of the memory chip, the full coverage of the function test of the memory chip must be guaranteed, however, the hardware condition of the test system pattern generator limits the number of bits of the pattern vector generated automatically, and the depth of the test system pattern vector limits the length of the pattern vector which can be run by the test system, so the full coverage test of the function of the large-capacity memory has been a difficult problem up to now. At present, the memory test ideas mainly include two kinds: firstly, a special memory test device is used for configuring a multi-data-bit pattern generator and expanding the vector depth of a pattern; secondly, the universal integrated circuit test equipment is used, and the graphic vector is automatically generated by the equipment DSIO. The former is expensive and it is impossible to expand the hardware capability without limit; the latter is limited to the hardware capabilities of the DSIO, the number of bits of the DSIO bus determining the total number of bits of data and addresses. Therefore, with the increasing memory capacity, the testing of the mass memory is often limited by the testing hardware, and the full coverage of the functions cannot be realized.
In view of the above-mentioned deficiencies of the prior art, the present invention provides a method for realizing full coverage of the function test of the mass storage without being limited by the hardware of the test system.
Disclosure of Invention
The invention aims to provide a method for realizing full coverage of the function test of a mass storage without being limited by hardware of a test system.
In order to achieve the purpose, the invention adopts the following technical scheme: a method for testing full coverage of a function of a mass storage comprises the following steps:
s1, dividing the storage space of a memory:
equally dividing the storage space of the memory into N subblock areas;
s2, writing an initial test pattern vector:
selecting a first sub-block area, analyzing a main fault mode according to the category and the function of a memory, determining a memory test algorithm, and manually compiling an initial test pattern vector;
s3, testing by the testing system for the first time:
according to the test flow of the test system, the test system guides and loads the written initial test pattern vector, applies power and input excitation to the memory, compares the output results and outputs the test result;
s4, setting a cycle execution condition:
taking the address of the first subblock region as an initial address, taking the address length of the subblock region as a stepping value, subtracting 1 from the number of the subblock regions to obtain the number of circulation times, adding the stepping value once to the initial address to form a new address every circulation time, and when the circulation is performed to the last time, taking the new address as the address of the last subblock region to achieve full-capacity coverage through circulation execution;
s5, generating a new test pattern vector:
converting the new address into binary codes, and corresponding the binary codes to address pins of a memory one by one; high-level language control, replacing the address vector part of the tested memory in the initial test pattern vector at the designated position by using a binary code of a new address, and maintaining other input and output signals and time sequence settings unchanged to form a new test pattern vector;
s6, modifying the operation flow of the test program:
and controlling the running process of the test system program, after the test system tests for the first time, not exiting the program, regenerating a new test pattern vector once per cycle according to the set cycle number, guiding to load a new test pattern vector, applying input excitation, performing output comparison until the cycle is performed for N times, disconnecting the input excitation and the power supply, outputting a total test result, and exiting the program.
The invention realizes the test by partitioning the large-capacity memory and selecting the first subblock area of the memory, and other subblock areas automatically modify the test vector of the memory and set the cycle times in a high-level language programming mode, thereby realizing the full coverage of the function test of the large-capacity memory. Therefore, the test system only needs to meet the conditions required by the test of the first subblock region, other subblock regions automatically modify the test graphics vector through the high-level language, and the method for repeatedly executing the test flow does not occupy additional test system resources, so that the limit of test hardware of the test system can be broken through, the writing of the graphics vector is simplified, and the functional test of the large-capacity memory is flexibly realized.
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FIG. 1 is a schematic flow diagram of the present invention;
FIG. 2 is a vector diagram of an initial test pattern according to the present invention;
FIG. 3 is a schematic diagram of a new test pattern vector of the present invention;
FIG. 4 is a flow chart illustrating the operation of the high-level language modification test program according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples, which should not be construed as limiting the invention.
Example one
A memory to be tested: type (2): parallel FLASH; the model is as follows: s29GL 512N; specification: 512 Mx 16 bits; 25 address pins; and 16 data pins.
(II) equipment: j750EX-HD test System.
(III) testing process:
the method for testing full coverage of the function of the mass storage as shown in the figure comprises the following steps:
s1, dividing the storage space of a memory:
equally dividing the storage space of S29GL512N into 262144 (i.e. 2)18) Each subblock region is 128 Words;
s2, writing an initial test pattern vector:
selecting a first sub-block area, manually writing an initial test pattern vector according to a checkerboard algorithm, realizing the write-read function of the first sub-block area (each address needs 4 pattern vectors to complete write operation, and 1 pattern vector to complete read operation), and testing 640 pattern vectors;
s3, testing by the testing system for the first time:
according to the test flow of the J750EX-HD test system, the test system guides and loads the written initial test pattern vector, applies power supply and input excitation to S29GL512N, compares the output results and outputs the test results;
s4, setting a cycle execution condition:
taking 0 as an initial address, taking the address length 128 of the subblock region as a stepping value, subtracting 1 from the number of the subblock regions, namely 262143, as cycle times, adding 128 to the initial address once every cycle to form a new address, and when the cycle is to the last time, taking the new address as the address 3355304 of the last subblock region, and realizing full-capacity coverage through cycle execution;
s5, generating a new test pattern vector:
for the first time, circularly converting 128-number arrays [ 128, 129, … …, 254 and 255 ] of a new address into 26-bit binary code arrays [ 00000000000000000010000000b, 00000000000000000010000001b, … …, 00000000000000000011111110b and 00000000000000000011111111b ], wherein the binary code arrays correspond to address pins [ A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1 and A0] of the memory one by one; high-level language control, replacing the graphic vector parts (00000000000000000000000000 b, 00000000000000000000000001b, … …, 00000000000000000001111110b and 00000000000000000001111111 b) of the addresses A25 to A0 of the memories to be tested in the initial test graphic vector at the specified position by using binary code arrays (00000000000000000010000000 b, 00000000000000000010000001b, … …, 00000000000000000011111110b and 00000000000000000011111111 b) of the new address, and keeping other input and output signals and time sequence settings unchanged to form a new test graphic vector;
s6, modifying the operation flow of the test program:
controlling the program running process of the J750EX-HD test system, after the test system tests for the first time, not exiting the program, regenerating a new test pattern vector once per cycle according to the set cycle number 262143, guiding to load a new test pattern vector, applying input excitation, performing output comparison, after the cycle is 262143, disconnecting the input excitation and the power supply, outputting a total test result, and exiting the program.
Example two
The memory to be tested: type (2): serial FLASH; the model is as follows: M25P 128; specification: 128 Mx 8 bits; SPI serial mode.
(II) equipment: j750EX-HD test System.
(III) testing process:
the method for testing full coverage of the function of the mass storage as shown in the figure comprises the following steps:
s1, dividing the storage space of a memory:
equally dividing the storage space of the M25P128 into 65536 sub-block regions, wherein each sub-block region is 256 Bytes;
s2, writing an initial test pattern vector:
selecting a first subblock region, manually compiling an initial test pattern vector according to a checkerboard algorithm, realizing the writing and reading functions of the first subblock region, and setting 4196 test pattern vectors according to the time sequence requirement of an SPI (serial peripheral interface) serial protocol;
s3, testing by the testing system for the first time:
according to the test flow of the J750EX-HD test system, the test system guides and loads the written initial test pattern vector, applies power supply and input excitation to the M25P128, compares the output results and outputs the test results;
s4, setting a cycle execution condition:
taking 0 as an initial address, the address length 256 of the subblock region as a stepping value, subtracting 1 from the number of the subblock regions, namely 65535, as cycle times, adding 256 to the initial address once every cycle to form a new address, and when the cycle is to the last time, taking the new address as the address 16776960 of the last subblock region, and realizing full-capacity coverage through cycle execution;
s5, generating a new test pattern vector:
the first loop converts the new address 256 to 24-bit binary code 000000000000000100000000 b; the high-level language control is carried out, according to an SPI serial port protocol, the binary code 000000000000000100000000b of a new address is used for sequentially replacing an SI pin graphic vector part 000000000000000000000000b of a tested memory in an appointed initial test graphic vector in 24 periods, other input and output signals and time sequence setting are maintained unchanged, and a new test graphic vector is formed;
s6, modifying the operation flow of the test program:
controlling the running process of the J750EX-HD test system program, after the test system tests for the first time, not exiting the program, according to the set cycle number 65535, regenerating a new test pattern vector once per cycle, guiding to load a new test pattern vector, applying input excitation, performing output comparison, after the cycle number 65535, disconnecting the input excitation and the power supply, outputting a total test result, and exiting the program.
EXAMPLE III
The memory to be tested: type (2): a dual-port SRAM; the model is as follows: IDT70T653MS12 BGT; specification: 512 Kx 36Bit x 2; 38 address pins; and 72 data pins.
(II) equipment: j750EX-HD test System.
(III) testing process:
the method for testing full coverage of the function of the mass storage as shown in the figure comprises the following steps:
s1, dividing the storage space of a memory:
equally dividing the storage space of the IDT70T653MS12BGT into 4096 sub-block areas, wherein each sub-block area is 128 Bytes;
s2, writing an initial test pattern vector:
selecting a first sub-block area, manually writing an initial test pattern vector according to a March algorithm to realize the writing and reading functions of the first sub-block area, and separately checking the functions and testing 512 pattern vectors aiming at IDT70T653MS12BGT, wherein the address and data lines are twice of a single-port SRAM;
s3, testing by the testing system for the first time:
according to the test flow of the J750EX-HD test system, the test system guides and loads the written initial test pattern vector, applies power supply and input excitation to the IDT70T653MS12BGT, compares the output results and outputs the test results;
s4, setting a cycle execution condition:
taking 0 as an initial address, taking the address length 128 of the subblock area as a stepping value, subtracting 1 from the number of the subblock areas, namely 4095, as cycle times, adding 128 to the initial address once every cycle to form a new address, and when the cycle is carried out to the last time, taking the new address as the address 524160 of the last subblock area, and realizing full-capacity coverage through cycle execution;
s5, generating a new test pattern vector:
first-time circulation is carried out to convert the number of arrays [ 128, 129, … …, 254, 255 ] of the 128 new address into 19-bit binary code arrays [ 0000000000010000000b, 0000000000010000001b, … …, 0000000000011111110b, 0000000000011111111b ] which are in one-to-one correspondence to address pins [ A18L, A17L, A16L, A15L, A14L, A13L, A12L, A11L, A10L, A9L, A8L, A7L, A6L, A5L, A4L, A3L, A2L, A1L, A0L ] and [ A18L, A17L, A16L, A15L, A14L, A13L, A12, A11, L, A10L, A9A 72, L A6A 72, L A6A 3, L A3, L A72A 6A 72, L A3, L A3A 72A 3, L A; high-level language control, using binary code arrays [ 0000000000010000000b, 0000000000010000001b, … …, 0000000000011111110b, 0000000000011111111b ] of new addresses to respectively replace pattern vector parts [ 0000000000000000000b, 0000000000000000001b, … …, 0000000000001111110b, 0000000000001111111b ] of addresses A18L-A0L and A18R-A0R of a tested memory in the initial test pattern vector of the specified position, keeping other input and output signals and time sequence settings unchanged, and forming a new test pattern vector;
s6, modifying the operation flow of the test program:
and controlling the running process of the J750EX-HD test system program, after the test system tests for the first time, not exiting the program, regenerating a new test pattern vector once per cycle according to the set cycle number 4095, guiding to load a new test pattern vector, applying input excitation, performing output comparison, after the cycle is 4095 times, disconnecting the input excitation and the power supply, outputting a total test result, and exiting the program.
Details not described in the present specification belong to the prior art known to those skilled in the art.
Claims (1)
1. A method for testing full coverage of a function of a mass storage comprises the following steps:
s1, dividing the storage space of a memory:
equally dividing the storage space of the memory into N subblock areas;
s2, writing an initial test pattern vector:
selecting a first sub-block area, analyzing a main fault mode according to the category and the function of a memory, determining a memory test algorithm, and manually compiling an initial test pattern vector;
s3, testing by the testing system for the first time:
according to the test flow of the test system, the test system guides and loads the written initial test pattern vector, applies power and input excitation to the memory, compares the output results and outputs the test result;
s4, setting a cycle execution condition:
taking the address of the first subblock region as an initial address, taking the address length of the subblock region as a stepping value, subtracting 1 from the number of the subblock regions to obtain the number of circulation times, adding the stepping value once to the initial address to form a new address every circulation time, and when the circulation is performed to the last time, taking the new address as the address of the last subblock region to achieve full-capacity coverage through circulation execution;
s5, generating a new test pattern vector:
converting the new address into binary codes, and corresponding the binary codes to address pins of a memory one by one; high-level language control, replacing the address vector part of the tested memory in the initial test pattern vector at the designated position by using a binary code of a new address, and maintaining other input and output signals and time sequence settings unchanged to form a new test pattern vector;
s6, modifying the operation flow of the test program:
and controlling the running process of the test system program, after the test system tests for the first time, not exiting the program, regenerating a new test pattern vector once per cycle according to the set cycle number, guiding to load a new test pattern vector, applying input excitation, performing output comparison until the cycle is performed for N times, disconnecting the input excitation and the power supply, outputting a total test result, and exiting the program.
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| CN102842344A (en) * | 2012-08-24 | 2012-12-26 | 湖北航天技术研究院计量测试技术研究所 | Method for testing EEPROM (electrically erasable programmable read-only memory) read-write cycle times |
| CN103187103A (en) * | 2011-12-28 | 2013-07-03 | 中国航空工业集团公司第六三一研究所 | Memory test method |
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- 2020-07-21 CN CN202010706450.8A patent/CN111833960A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5377148A (en) * | 1990-11-29 | 1994-12-27 | Case Western Reserve University | Apparatus and method to test random access memories for a plurality of possible types of faults |
| US5954831A (en) * | 1997-10-08 | 1999-09-21 | Ects Inc. | Method for testing a memory device |
| US20030204797A1 (en) * | 2002-04-24 | 2003-10-30 | Wen-Hsi Lin | Memory testing device and method |
| CN103187103A (en) * | 2011-12-28 | 2013-07-03 | 中国航空工业集团公司第六三一研究所 | Memory test method |
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