Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Referring to fig. 2, the LED display system provided in the embodiment of the present invention includes a controller 21 and one or more groups of cascaded LED lamp bead groups 22 electrically connected to the controller 21, where each group of cascaded LED lamp bead groups 22 includes a plurality of LED lamp bead groups connected in series, and each group of LED lamp beads connected in series includes four LED lamp beads connected in series;
The LED lamp bead comprises a base, an LED driving control chip, a red LED chip, a blue LED chip and a green LED chip which are arranged on the base; the LED drive control chip is provided with a red light output end R, a green light output end G, a blue light output end B, a power supply input end VDD, a ground end GND, a first data input end DIN, a second data input end FDIN, a first data output end DO1, a second data output end DO2 and an enabling end DENL, wherein the LED lamp bead is provided with a power supply input pin VDD connected with the power supply input end VDD of the LED drive control chip, a ground pin GND connected with the ground end GND of the LED drive control chip, a first data input pin DIN connected with the first data input end DIN of the LED drive control chip, a second data input pin FDIN connected with the second data input end FDIN of the LED drive control chip, and a first data output pin DO1 connected with the first data output end DO1 of the LED drive control chip and a second data output pin DO2 connected with the LED drive control chip;
The controller 21 has one or more sets of data outputs, each set of data outputs comprising a first data output DI and a second data output FI; the first data output end DI of the controller 21 is respectively connected with the first data input pin DIN of the first LED lamp bead L1 of the first LED lamp bead group 221 and the second data input pin FDIN of the second LED lamp bead L2 of the first LED lamp bead group 221, and the second data output end FI of the controller 21 is respectively connected with the first data input pin DIN of the third LED lamp bead L3 of the first LED lamp bead group 221 and the second data input pin FDIN of the fourth LED lamp bead L4 of the first LED lamp bead group 221; the second data input pin FDIN of the first LED lamp bead L1 of the first LED lamp bead group 221 is grounded, the first data output pin DO1 of the first LED lamp bead L1 of the first LED lamp bead group 221 is connected with the first data input pin DIN of the second LED lamp bead L2 of the first LED lamp bead group 221 and the second data input pin FDIN of the third LED lamp bead L3 of the first LED lamp bead group 221, the second data output pin DO2 of the first LED lamp bead L1 of the first LED lamp bead group 221 is connected with the first data input pin DIN of the fourth LED lamp bead L4 of the first LED lamp bead group 221 and the second data input pin FDIN of the first LED lamp bead L1 of the second LED lamp bead group 222, the first data output pin DO1 of the second LED lamp bead L2 of the first LED lamp bead group 221 is connected with the first data input pin DIN of the third LED lamp bead L3 of the first LED lamp bead group 221 and the second data input pin FDIN of the fourth LED lamp bead L4 of the first LED lamp bead group 221, the second data output pins DO2 of the second LED lamp beads L2 of the first LED lamp bead group 221 are respectively connected with the first data input pins DIN of the first LED lamp beads L1 of the second LED lamp bead group 222 and the second data input pins FDIN of the second LED lamp beads L2 of the second LED lamp bead group 222, the first data output pins DO1 of the third LED lamp beads L3 of the first LED lamp bead group 221 are respectively connected with the first data input pins DIN of the fourth LED lamp beads L4 of the first LED lamp bead group 221 and the second data input pins FDIN of the first LED lamp beads L1 of the second LED lamp bead group 222, the second data output pins DO2 of the third LED lamp beads L3 of the first LED lamp bead group 221 are respectively connected with the first data input pins DIN of the second LED lamp beads L2 of the second LED lamp bead group 222 and the second data input pins FDIN of the third LED lamp beads L3 of the second LED lamp bead group 222, and the first data output pins DO of the fourth LED lamp beads L4 of the first LED lamp bead group 221 are respectively connected with the second data input pins DO of the second LED lamp beads L1 of the second LED lamp beads L2 of the second LED lamp bead group 222 and the second LED lamp beads L2 of the second lamp bead group FDIN.
The data format of the LED display system provided by the embodiment of the invention is as follows:
S1 DIN1 c1c2c3D1D2D3D4......Dn
DO1 c1c2c3D2D3D4D5..........Dn
DO2 c1c2c3D4D5D6D7...........Dn
S2 DIN1 c1c2c3D2D3D4D5......Dn
FDIN1 c1c2c3D1D2D3D4.........Dn
DO1 c1c2c3D3D4D5D6..........Dn
DO2 c1c2c3D5D6D7D8...........Dn
S3 DIN1 c1c2c3D3D4D5D6......Dn
DIN2 c1c2c3D3D4D5D6.......Dn
FDIN1 c1c2c3D2D3D4D5.........Dn
DO1 c1c2c3D4D5D6D7..........Dn
DO2 c1c2c3D6D7D8D9...........Dn
S4 DIN1 c1c2c3D4D5D6D7......Dn
DIN2 c1c2c3D4D5D6D7......Dn
FDIN1 c1c2c3D3D4D5D6.........Dn
FDIN2 c1c2c3D3D4D5D6..........Dn
DO1 c1c2c3D5D6D7D8..........Dn
DO2 c1c2c3D7D8D9D10........Dn
S5 DIN1 c1c2c3D5D6D7D8......Dn
DIN2 c1c2c3D5D6D7D8......Dn
FDIN1 c1c2c3D4D5D6D7.........Dn
FDIN2 c1c2c3D4D5D6D7..........Dn
DO1 c1c2c3D6D7D8D9..........Dn
DO2 c1c2c3D8D9D10D11......Dn
S6 DIN1 c1c2c3D6D7D8D9......Dn
DIN2 c1c2c3D6D7D8D9......Dn
FDIN1 c1c2c3D5D6D7D8.........Dn
FDIN2 c1c2c3D5D6D7D8..........Dn
DO1 c1c2c3D7D8D9D10..........Dn
DO2 c1c2c3D9D10D11D12......Dn
S7 DIN1 c1c2c3D7D8D9D10......Dn
DIN2 c1c2c3D7D8D9D10......Dn
FDIN1 c1c2c3D6D7D8D9.........Dn
FDIN2 c1c2c3D6D7D8D9..........Dn
DO1 c1c2c3D8D9D10D11..........Dn
DO2 c1c2c3D10D11D12D13......Dn
S8 DIN1 c1c2c3D8D9D10D11......Dn
DIN2 c1c2c3D8D9D10D11......Dn
FDIN1 c1c2c3D7D8D9D10.........Dn
FDIN2 c1c2c3D7D8D9D10..........Dn
DO1 c1c2c3D9D10D11D12..........Dn
DO2 c1c2c3D11D12D13D14......Dn
Sn DIN1 c1c2c3DnDn+1Dn+2Dn+3
DIN2 c1c2c3DnDn+1Dn+2Dn+3
FDIN1 c1c2c3Dn-1DnDn+1Dn+2
FDIN2 c1c2c3Dn-1DnDn+1Dn+2
DO1 c1c2c3Dn+1Dn+2Dn+3Dn+4
DO2 c1c2c3Dn+3Dn+4Dn+5Dn+6
In the embodiment of the present invention, the first data input pin DIN may also include a first data first sub-input pin DIN1 and a first data second sub-input pin DIN2 connected to the first data input terminal DIN of the LED driving control chip, respectively. The second data input pins FDIN may also include a second data first sub-input pin FDIN and a second data second sub-input pin FDIN, which are connected to the second data input FDIN of the LED driving control chip, respectively.
The first data input pin DIN of each LED lamp bead from the fourth LED lamp bead L4 of the first LED lamp bead group 221 includes a first data first sub-input pin DIN1 and a first data second sub-input pin DIN2, the second data input pin FDIN includes a second data first sub-input pin FDIN1 and a second data second sub-input pin FDIN2, and the first data first sub-input pin DIN1, the first data second sub-input pin DIN2, the second data first sub-input pin FDIN and the second data second sub-input pin FDIN correspond to one decoding channel circuit inside the LED driving control chip, the first data first sub-input pin DIN1 and the first data second sub-input pin DIN2 are identical in signal, the connection is not sequentially and randomly exchanged, and the first data first sub-input pin DIN1 and the second data second sub-input pin DIN2 can be directly decoded after being buffered with 2 ports DIN1 and DIN2 or with 1 port DIN input logic processing circuit, the first data sub-input pin is identical in priority, and no delay is needed; when the first data first sub-input pin DIN1 and the first data second sub-input pin DIN2 are invalid, the signals are switched to the second data first sub-input pin FDIN or the second data second sub-input pin FDIN2, the signals of the second data first sub-input pin FDIN and the second data second sub-input pin FDIN are identical, the connection is not in sequence and can be randomly exchanged, and the first bit data can be deleted and decoded after being input into a cache logic processing circuit by using 2 ports FDIN1 and FDIN or using 1 port FDIN so as to keep data synchronization, the priority is identical, and no delay is needed.
Each LED lamp bead at least comprises a first data output pin DO1 and a second data output pin DO2, the output data of 2 paths and more are different, the first data output pin DO1 is used for deleting the first 2 bits of data by the signal processing circuit to generate the data output of the second data output pin DO2, and if the data output pin has 1 path of output damage, all the data output pins cannot fail. However, when the circuit is simply connected due to reasons such as single-sided circuit wiring, for example, to avoid circuit crossing and to avoid using other devices (such as resistors, inductors, etc.), only the first data output pin DO1 is used, the second data output pin DO2 is suspended, and the first data output pin DO1 is connected to any 1 or DIN signal input ports in DIN1 and DIN2 of the adjacent first LED lamp beads. The first data output pin DO1 is again connected to any 1 or FDIN of FDIN or FDIN of the adjacent second LED lamp beads.
The mode setting of the LED drive control chip is as follows:
the chip is single-wire double-channel communication, and a return-to-zero code mode is adopted to send signals.
Before the chip receives the display data, the correct working mode needs to be configured, and the mode of receiving the display data is selected. The mode setting command is 48 bits in total, wherein the first 24 bits are command codes, the second 24 bits are check counter codes, the chip is reset to start receiving data, and the mode setting command is 4 kinds as follows:
(1) The 0 xfffff_000000 command the chip is configured in normal operation mode. In this mode, the default DIN receives the display data for the first time, the chip keeps the port to receive all the time when detecting that the port has a signal input, and switches to FDIN to receive the data if 160ms is exceeded, and keeps the port to receive all the time when detecting that the port has a signal input, and switches to DIN to receive the display data again if 160ms is exceeded. DIN and FDIN are sequentially switched cyclically to receive the display data.
(2) The 0xffffa_000005 command is that the chip is configured in a DIN operation mode in which the chip receives only display data inputted from the DIN terminal and the FDIN terminal data is not valid.
(3) The 0xffffff5_00000a command is that the chip is configured in FDIN operation mode, in which the chip only receives the display data inputted from FDIN terminal and the DIN terminal is not valid.
(4) The 0xffffff0_00000f command the chip is configured in test mode.
The display data of the LED drive control chip is as follows:
After the chip is powered on and reset and receives the mode setting command, the chip starts to receive the constant current value setting command, then receives display data, and after 24 bits are received, DO1 and DO2 ports start to forward data continuously sent from DIN or FDIN ends, so that display data are provided for the next cascade chip. The DO1 and DO2 ports are low until the data is forwarded. If a Reset signal is input from the DIN or FDIN terminal, the chip OUT terminal outputs PWM waveform with corresponding duty ratio according to the received 24bit display data, and the chip waits for receiving new data again, after receiving the first 24bit data, the data is forwarded through the DO terminal, and the R, G, B original output is kept unchanged before the Reset signal is not received by the chip.
The chip adopts an automatic shaping and forwarding technology, and signals cannot be distorted and attenuated. The period of data transfer is uniform for all chips cascaded together.
A complete data structure for a frame is as follows:
C1 |
C2 |
C3 |
D1 |
D2 |
D3 |
D4 |
... |
Dn |
Reset |
C1 |
C2 |
C3 |
D1 |
D2 |
D3 |
D4 |
... |
Dn |
Reset |
c1, C2 are mode setting commands, each contain 24bit data bits, each chip will receive and forward C1, C2, wherein 0xFFFFFF_000000 is normal working mode command, 0xFFFFFA_000005 is DIN working mode command, 0xFFF5_00000A is FDIN working mode command, 0xFFFF0_00000F is chip test mode command, C3 is constant current value setting command, each chip will receive and forward C1, C2, C3.
D1, D2, D3, D4, &.. Dn is PWM setting command of each chip.
Reset represents a Reset signal, active low.
The data format of C3 is as follows:
R7 |
R6 |
R5 |
R4 |
R3 |
R2 |
R1 |
R0 |
G7 |
G6 |
G5 |
G4 |
G3 |
G2 |
G1 |
G0 |
B7 |
B6 |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
the C3 command contains 8 x 3bit data bits, the high order is issued first, R7, G7, B7 are fixed to 0.
R < 6:0 > is used for setting the R output constant value. All 0 codes are 2mA, all 1 codes are 25mA, and 128 stages are adjustable.
G [6:0] is used for setting the G output constant value. All 0 codes are 2mA, all 1 codes are 25mA, and 128 stages are adjustable.
And B [6:0] is used for setting the output constant current value of B. All 0 codes are 2mA, all 1 codes are 25mA, and 128 stages are adjustable.
The data format of Dn is as follows:
R7 |
R6 |
R5 |
R4 |
R3 |
R2 |
R1 |
R0 |
G7 |
G6 |
G5 |
G4 |
G3 |
G2 |
G1 |
G0 |
B7 |
B6 |
B5 |
B4 |
B3 |
B2 |
B1 |
B0 |
each PWM setup command contains 8 x 3bit data bits, the high order bits being issued first.
R7:0 is used to set the PWM duty cycle of the R output. All 0 codes are turned off, all 1 codes are maximum in duty ratio, and 256 levels are adjustable.
G [7:0] is used to set the PWM duty cycle of the G output. All 0 codes are turned off, all 1 codes are maximum in duty ratio, and 256 levels are adjustable.
And B7:0 is used for setting the PWM duty cycle of the B output. All 0 codes are turned off, all 1 codes are maximum in duty ratio, and 256 levels are adjustable.
In the embodiment of the invention, the cascade and data transmission and forwarding processes of the LED display system are as follows, wherein the controller sends data S1, the first LED lamp bead L1 receives C1, C2 and C3 for verification, if a command is correct, the C1, C2 and C3 are forwarded, D1 is absorbed simultaneously, if a Reset signal is not generated at the moment, the first LED lamp bead L1 always forwards the data continuously sent by the controller, the second LED lamp bead L2 also receives C1, C2 and C3 for verification, if the command is correct, the C1, C2 and C3 are forwarded, D2 is absorbed simultaneously, and if the Reset signal is not generated at the moment, the second LED lamp bead L2 always forwards the data continuously sent by the first LED lamp bead L1. And so on, until the controller sends a Reset signal, a data refreshing period is completed, and the LED lamp beads return to a receiving preparation state. Reset is effective, the time of the low level is kept to be more than 80 mu s, and the LED lamp beads are Reset.
The embodiment of the invention also provides an LED display screen, which comprises a sending control module connected with the output end of a computer and one or more LED display systems provided by the embodiment of the invention and connected with the output end of the sending control module, wherein each LED display system comprises a controller and a plurality of groups of cascaded LED lamp bead groups respectively connected with the controller electrically.
In the invention, since each group of cascaded LED lamp bead groups of the LED display system comprises a plurality of LED lamp bead groups connected in series, each LED lamp bead group connected in series comprises four LED lamp beads connected in series in the manner, even if any adjacent 2 or 3 LED lamp beads are damaged, the normal operation of the LED lamp beads can not be influenced as long as no adjacent 4 LED lamp beads are damaged.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.