CN111817594A - Method and half-bridge controller for determining polarity of half-bridge current - Google Patents

Abstract

The present disclosure relates to a method and a half-bridge controller for determining the polarity of a half-bridge current. A method and a half-bridge controller for detecting the polarity of the current through the half-bridge are provided. Switching delays of switches of the half bridge are determined, and a polarity of a current through the half bridge is determined based on the switching delays.

Description

Method and half-bridge controller for determining polarity of half-bridge current

technical field

The present application relates to a method for determining the polarity of a current through a half-bridge, a corresponding half-bridge controller, and a method for dead-time compensation for a half-bridge based on the determined polarity and half-bridge controllers.

Background technique

Half bridges are used in many applications to selectively power loads. Applications include the use of so-called three-phase inverters to drive electric motors, where three such half-bridges are used to provide three-phase output currents. A half bridge typically includes a first switch coupled between a first potential of the half bridge and the output node and a second switch coupled between a second potential and the output node. For example, the first potential may be a positive power supply voltage and the second potential may be a negative power supply voltage or ground. The first switch is often referred to as the high-side switch, and the second switch is referred to as the low-side switch.

In operation of such a half bridge, the first switch and the second switch are alternately closed and open to selectively couple the output node to the first potential or the second potential.

In such a half bridge, if the first switch and the second switch are closed at the same time, a short circuit between the first potential and the second potential will result. In order to avoid such a short circuit, a so-called dead time is inserted in the case where both switches are open before one of the switches is closed.

However, through these dead times, the output voltage of the half-bridge deviates from the ideal output voltage, such as in many applications typically controlled by a pulse-width modulation (PWM) scheme, which can introduce current ripple and increase systems using the half-bridge nonlinearity. The distortion of the output voltage in the case of eg an ideal sinusoidal voltage includes both low frequency harmonics and switching frequency harmonics. Low frequency harmonics can negatively affect the performance of some half-bridge applications.

Various methods have been used to compensate for the effects of introducing dead time, referred to herein as dead time compensation. Some of these techniques apply a compensation voltage based on the polarity of the current through the half-bridge, which indicates whether the current is flowing from the half-bridge to the load or from the load to the half-bridge. However, in detection circuits conventionally used to determine polarity, errors may occur when the current is close to zero because noise may cause detection of wrong polarity. Increased reliability of these conventional detection circuits requires additional hardware or increased software complexity, eg for filtering algorithms. Also, in other cases, it may be necessary to determine the polarity of the current through the half-bridge.

SUMMARY OF THE INVENTION

The method of claim 1 and the half-bridge controller of claim 11 are provided. The dependent claims define further embodiments and systems comprising such a half-bridge controller.

According to one embodiment, there is provided a method for determining the polarity of current through a half-bridge, the method comprising: determining a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge; and switching based on The delay determines the polarity of the current through the half bridge.

According to another embodiment, a half-bridge controller is provided, the half-bridge controller comprising: a measurement circuit configured to determine a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge; and A control circuit configured to determine a polarity of current through the half-bridge based on the switching delay.

The above summary is intended only to give a brief overview of some features of some embodiments and should not be construed as limiting in any way.

Description of drawings

1 is a flowchart illustrating a method according to an embodiment;

2 is a block diagram illustrating a system according to an embodiment;

FIG. 3 is an example half bridge for illustrating an embodiment;

4A and 4B are signal diagrams illustrating example operation of the half-bridge of FIG. 3;

FIG. 5 is a graph for illustrating the voltage and current of the half bridge;

6 illustrates a delay measurement circuit according to an embodiment;

Figures 7 to 14 (including Figures A and B, respectively) illustrate the determination of the polarity of the current through the half-bridge under various conditions;

15 is a block diagram of a delay measurement circuit usable in some embodiments;

Figure 16 shows the output current of the three-phase inverter;

Figure 17 is a block diagram of a circuit for phase estimation usable in some embodiments; and

18A-18D show measurement results with dead time compensation according to the techniques disclosed herein and according to a comparative example.

Detailed ways

Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. Although various details are shown in the drawings and described in the corresponding description, this should not be construed as indicating that the order of the embodiments requires all of these details. In other embodiments, some of these details may be omitted, or may be replaced with alternative features or details.

Furthermore, other features than those explicitly described may be provided, such as features conventionally provided in half-bridge circuits, controllers for half-bridge circuits, and applications of such half-bridge circuits.

Features from different embodiments may be combined to form other embodiments. Changes and modifications described with respect to one of the embodiments also apply to the other embodiments unless expressly stated otherwise. Variations and modifications described with respect to one of the embodiments are also applicable to the other embodiments unless otherwise indicated, and thus the description will not be repeated.

Unless otherwise stated, connections or couplings shown in the figures or described herein relate to electrical connections or couplings and/or connections or couplings for transmitting signals within a circuit or logical entity.

The embodiments discussed below relate to determining the polarity of the current through the half-bridge. The polarity of the current indicates whether the current flows from the half-bridge to the load coupled to the half-bridge or from the load to the half-bridge.

A half bridge as described herein includes switches. The switch may include a control terminal and two load terminals. The state of the switch can be controlled by applying a signal to the control terminal. If the switch provides a low ohmic electrical path between its load terminals, the state of the switch is called closed or conducting. A switch is said to be open or cut-off if it is substantially electrically isolated between its load terminals. "Basic electrical isolation" refers to the fact that, in a practical switch implementation, some parasitic leakage current occurs between the load terminals even in the open state. However, such leakage current, if it occurs, is typically orders of magnitude lower than the current flowing when the switch is in the closed state.

Switches can be implemented using transistors. Useful transistors include field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors), bipolar transistors, or insulated gate bipolar transistors (IGBTs). In the case of a field effect transistor, the control terminal corresponds to the gate terminal, and the load terminal corresponds to the source and drain terminals. In the case of a bipolar transistor, the control terminal corresponds to the base terminal and the load terminal corresponds to the emitter and collector terminals. In the case of an IGBT, the control terminal corresponds to the gate terminal, and the load terminal corresponds to the collector terminal and the emitter terminal. In many implementations of half bridges, such transistor-based switches also include a freewheeling diode between the load terminals. Freewheeling diodes can be inherent to the respective transistor design, or can be provided separately.

Figure 1 shows a method according to an embodiment. The method can be implemented, for example, in a half-bridge controller.

At 10, the method of FIG. 1 includes determining switching delays of switches of the half bridge. As explained in the background section, the half-bridge includes a first switch and a second switch, also referred to as a high-side switch and a low-side switch. Switching delay as used herein refers to the delay between the control signal used to change the state of the switch from open to closed or vice versa and the actual change in the state of the switch.

At 11, the method includes determining the polarity of the current through the half bridge based on the switching delay. For example, determining the polarity may include comparing the switching delay to a threshold. Examples of suitable thresholds are discussed further below.

In some applications, dead time compensation may be applied based on the polarity determined at 12 in FIG. 1 .

Possible implementation details of various acts or events of the method of FIG. 1 are further described below.

Figure 2 shows a system according to an embodiment. The system of FIG. 2 includes a controller 20 that controls the half-bridge 21 . The current flowing through the half bridge 21 provides the output current Iout to the load, or corresponds to the output current Iout received from the load. As mentioned above, the half bridge 21 can be implemented using two switches in any conventional manner.

The controller 20 includes a delay measurement circuit 23 configured to determine the switching delay of one or both switches of the half bridge 21 . The turn-on delay when the switch is turned on, the turn-off delay when the switch is turned off, or both can be determined.

Controller 20 also includes control circuitry 22 . The control circuit 22 may control the switching of the switches of the half-bridge 21 by generating corresponding control signals provided to the control terminals of the switches. Furthermore, the control circuit 22 is configured to determine the polarity of the current Iout (ie, the current through the half-bridge) based on the determined switching delay or delays. In some implementations, the control circuit 22 may apply dead-time compensation based on the determined polarity, eg, by modifying the control signals that control the switches of the half-bridge 21 or by modifying the reference voltages used to control the switches. The implementation of delay measurement circuit 23 and an example for determining polarity and dead time compensation will be further described below.

FIG. 3 is a circuit diagram of a half bridge to be used in the following description. The half-bridge of FIG. 3 is also an example of an implementation of the half-bridge 21 of FIG. 2 or the half-bridge used in the method of FIG. 1 . The half-bridge of FIG. 3 includes a first switch QH as a high-side switch and a second switch QL as a low-side switch coupled between a first potential 30 and a second potential 31 . The first potential 30 is more positive than the second potential 31 . For example, the first potential 30 may correspond to the positive or positive supply voltage (eg, VDD) of the battery, and the second potential 31 may correspond to the negative, negative supply voltage or ground of the battery. Therefore, a DC (direct current) voltage VDC is applied between the first potential 30 and the second potential 31 .

The high-side switch QH is controlled by the control signal GH, and the low-side switch QL is controlled by the control signal GL.

The high-side switch QH has a first freewheeling diode DH connected thereto in parallel, and the low-side switch QL has a second freewheeling diode DL connected thereto in parallel. As mentioned above, the switches QH, QL may be transistor switches, and the freewheeling diodes DH, DL may be diodes inherent to the design of the transistors, or may be provided separately.

The current Iout through the half-bridge generated when the switches QH, QL are closed and opened according to some switching scheme flows from the node between the switches QH, QL to the load 32, or from the load 32 to the node between the switches QH, QL, and The current Iout is also called the output current. The polarity of the current Iout indicates whether the current Iout is flowing from the half-bridge to the load 32 or from the load 32 to the half-bridge. For example, the current Iout flowing to the load 32 may be referred to herein as a positive current having a positive polarity, while the current Iout flowing to the half bridge will be referred to herein as a negative current having a negative polarity. It should be understood, however, that this is merely a naming convention and that reverse naming may also be used.

The voltage across the high-side switch QH or the low-side switch QL will be referred to herein as the body voltage Vbody of the respective switch. In the case of field effect transistor switches, this body voltage Vbody may correspond to the drain-source voltage Vds of the respective transistor.

Figures 4A and 4B show the switches QH, QH of the half-bridge of Figure 3 in the case of a positive current Iout (Iout>0) in Figure 4A and a negative current Iout (Iout<0) in Figure 4B QL switch.

It should be noted that Figures 4A and 4B are somewhat simplified schemes, since the turn-on and turn-off transients of high-side switch QH and low-side switch QL are not considered.

In FIG. 4A, for the case of Iout>0, signals GH, GL respectively show the high-side switches QH and low for FIG. 3 according to some switching scheme that generates the desired output voltage Vout at the node between the switches Ideal control signal for side switch QL. In Figure 4A and subsequent switches, a "high" control signal indicates that the corresponding switch is closed, while a "low" control signal indicates that the corresponding switch is open. In this ideal case, the high-side switch QH and the low-side switch QL are switched at the same time, eg, when the high-side switch QH is turned on, the low-side switch QL is turned off at the same time, and vice versa.

In fact, such a switching scheme has the risk of a short circuit between the first potential 30 and the second potential 31, thus inserting a dead time td. This produces modified control signals GH1, GL1, also shown in Figure 4A.

Vout in FIG. 4A shows the ideal output voltage of an ideal switching scheme using control signals GH, GL, and Vout1 shows the output voltage with dead time insertion. In this case, after the low-side switch QL is controlled to be turned off by the control signal GL1, the current Iout flows through the diode DL until QH is turned on, so Vout1 remains low until QH is turned on during this dead time td (corresponding to the control signal GH1 ). When QH is turned off, the current Iout flows through the diode DL, and Vout1 immediately goes low (corresponding to the second potential 31).

Due to the dead time td, Vout1 is different from the ideal output voltage Vout, and this difference is represented as an error voltage in FIG. 4A.

FIG. 4B shows the same signals GH, GL and GH1 , GL1 , and Vout, Vout1 and Verr as in FIG. 4A with current Iout<0. In this case, when the low-side switch QL pass signal GL1 is turned off, the output voltage Vout1 changes immediately. On the other hand, the output voltage Vout1 drops to the second potential 31 only after the low-side switch QL pass signal GL1 is turned off, resulting in a difference between Vout1 and Vout and a corresponding error voltage, as shown in FIG. 4B . It can be seen from FIGS. 4A and 4B that the error voltage Verr is different for different polarities of the current Iout. Therefore, in order to compensate for this error voltage, it is helpful in some applications to determine the polarity of the current Iout.

For further explanation, in the case of operating switches QH, QL to generate a sinusoidal output voltage as an example, the ideal output voltage Vout, the actual output voltage Vout1 , the corresponding output current Iout and the error voltage Verr are shown in FIG. 5 as an illustration Example. As a load, take an inductive load as an example. FIG. 5 shows the ideal output voltage Vout as a sinusoidal voltage, and shows the distortion of the actual output voltage Vout1 generated due to the insertion of dead time. Distortion includes both low frequency harmonics and switching frequency harmonics. As already stated initially, this can lead to various negative effects on the performance of the system containing the half-bridge.

According to an embodiment, the dead time compensation technique is applied depending on the polarity of the current. As in conventional methods, the determination of the polarity may have some disadvantages, in the embodiments discussed herein, the polarity of Iout is determined based on a measurement of the switching delay. Based on this determined polarity, conventional dead time compensation techniques can then be applied. For example, a compensation voltage with the opposite sign of the error voltage (the sign depending on the polarity as described above) may be applied, eg by modifying the switching scheme of the switches to provide the error voltage or by modifying the additional voltage provided accordingly.

Next, the switching delay measurement and the determination of the polarity of the current Iout based on the delay measurement will be described.

FIG. 6 shows a delay measurement circuit according to an embodiment. The delay measurement circuit of FIG. 6 includes a comparator 60 and a counter 61 . Using the delay measurement circuit of FIG. 6, the switching delay of each switch QH, QL of FIG. 3 can be measured.

Comparator 60 receives the body voltage Vbody at its first input and the threshold voltage Vthr at its second input. The threshold voltage may be a threshold voltage corresponding to a voltage indicating that the corresponding switch is turned on or off when the threshold voltage is crossed. In a transistor, the threshold voltage may indicate that the transistor's on-charge Qon has been reached. Therefore, in FIG. 6, the output signal of the comparator 60 is labeled Qon. It should be noted that in other embodiments, instead of the body voltage Vbody, another voltage at the respective switch may be used, eg, in the case of a transistor switch, the voltage between the control terminal and one of the load terminals, such as the gate-drain voltage.

When the signal Qon changes its state, this indicates that the transistor has actually been switched. This signal Qon is provided to the first input of the counter 61 .

The corresponding control signal (ie GH or GL) of the switch whose switching delay is to be measured is supplied to the second input of the counter 61 . The counter 61 is clocked by the clock signal clock.

The counter 61 counts the time between the signal change of Qon and the edge of the control signal GH or GL, that is, starts counting based on one signal and stops counting based on the other signal. The count is based on the clock signal. In this way, the switching delay tdel is provided as the time difference between the actual switching of the switch (indicated by the signal Qon) and the nominal (predetermined) switching of the switch (indicated by the corresponding control signal GH or GL).

The switching delay can be measured for one or more of the following: turn-on of high-side switch QH, turn-off of high-side switch QH, turn-on of low-side switch QL, or turn-off of low-side switch QL, and can be based on these Either or a combination of the measurements is taken to determine the polarity of the current Iout. This will be explained next with reference to Figures 7 to 14, where all these possible scenarios will be discussed. In each of Figures 7-14, the corresponding Figure A (7A, 8A, . . . , 14A) shows the half-bridge of Figure 3 with an indication of the polarity of the output current and the An indication of the current paths, and corresponding graphs B (7A, 8B, . . . , 14B) show the corresponding signals, respectively.

7A and 7B show the case where the output current Iout is positive as indicated by arrow 71 and the switching delay of the high-side switch QH is measured. The low-side switch QL is turned off and the high-side switch QH is turned on, separated by a dead time td.

In the case of FIGS. 7A and 7B , after the low-side switch QL has been turned off and before the high-side switch QH is turned on (ie, during the dead time td shown in FIG. 7B ), the output current Iout is substantially passed through The current path of the freewheeling diode DL flows from the second potential 31 to the load 32 as indicated by the dashed line 70 . During this period, the Vbody of the high-side switch QH remains high (high voltage drop across the transistor, corresponding to a non-conducting state). After the rising edge of GH, the high-side switch QH begins to conduct and Vbody decreases until the threshold voltage Vthr is reached and Qon is triggered. The time delay between the rising edge of signal GH and the falling edge of signal Qon is the switching delay, in this case the on-time delay ton. In other words, ton is defined as the time of the falling edge of Qon minus the time of the rising edge of GH. This on-time delay ton is positive with respect to the rising edge of GH, or in other words, occurs after the dead time td.

Figures 8A and 8B again show the case where the high-side switch QH is turned on and the low-side switch QL is turned off (separated by dead time, as shown in Figures 7A and 7B ), but in this case the current Iout <0, as indicated by arrow 81. In this case, after the low-side switch QL is turned off, the output current (shown generally by arrow 81 and more particularly by current path 80 ) flows through diode DH. Therefore, the Vbody of the high-side switch QH decreases and goes low before the rising edge of GH. In other words, as shown in FIG. 8B, Vbody crosses the threshold Vthr before the rising edge of GH arrives, so the falling edge of Qon occurs before the rising edge of GH arrives. Where the definition of the turn-on delay ton is the same as before (ie, the time of the falling edge of Qon minus the time of the rising edge of GH), in this case, ton is negative.

Thus, for example, by measuring the turn-on delay of the high-side switch QH as the switching delay by using the circuit of FIG. 6 (in this case, tdel corresponds to ton) and by comparing the determined switching delay ton with a threshold (eg, zero) By comparison, the polarity of the current can be determined when measuring the turn-on delay of the high-side switch. For example, if ton is greater than zero, the polarity of the current is positive, while if ton is less than zero, the polarity of the current is negative.

Next, the case in which the high-side switch QH is turned off and the low-side switch QL is turned on (separated by a dead time) will be discussed, in which case the switching delay of the high-side switch QH is again measured (in this case deadline delay).

9A and 9B show the case where the current Iout is positive, as indicated by arrow 91 .

In this case, when the falling edge of GH arrives, indicating that the high-side switch QH should be turned off, the high-side switch QH actually begins to turn off, and the bulk voltage Vbody across the high-side switch QH begins to rise and reaches the threshold Vthr. In this case, during the dead time, current flows through the diode DL, as shown by the dashed line 90 . In this case, the turn-off delay time toff is the time essentially required for the turn-off of the high-side switch QH.

10A and 10B show the case of the turn-off delay of the high-side switch QH when the output current is of negative polarity, as indicated by arrow 101 . In this case, when the falling edge of the control signal GH arrives, current flows through the diode DH while the high-side switch QH starts to turn off as shown by the dashed line 100, which causes the body voltage Vbody to remain low and only in the dead zone The time td has elapsed before it rises and the low-side switch QL starts to conduct. In this case, the measured turn-off delay toff between the rising edge of Qon and the falling edge of GH is essentially the dead time td plus the inherent device turn-on delay of the low-side switch QL, and in particular, is greater than the dead time District time td. Therefore, when evaluating the turn-off delay of the high-side switch, the dead-time td can be used as a threshold, and if the measured turn-off delay toff is less than the dead-time td, the polarity of the current is positive, while when the measured turn-off delay toff is less than the dead time td When toff is greater than td, the polarity is negative.

Next, the determination of the polarity of the current Iout based on the switching delay (in this case, the turn-on delay) when the low-side switch QL is turned on will be discussed with reference to FIGS. 11 and 12 .

When the current Iout is positive as shown by the arrow 111 in FIG. 11A , after the high-side switch QH is turned off, the freewheeling current flows through the diode DL as shown by the dashed line 110 . Thus, the body voltage Vbody begins to drop and cross the threshold even before the rising edge of GL indicates the turn-on of the low-side switch QL. In this case, if the turn-on delay ton is again defined as the time of the falling edge of Qon minus the time of the rising edge of GL (similar to the case of Figures 7 and 8), then ton is negative. In other words, in this case, the turn-on delay corresponds to td minus the time required for the high-side switch QH to turn off after the falling edge of GH.

12A and 12B show the case where Iout is negative, as indicated by arrow 121 . In this case, during the dead time, current flows through the diode DH, as shown by the dashed line 120 . Therefore, the body voltage Vbody of the low-side switch QL remains high until the rising edge of GL turns on the low-side switch QL, after which the body voltage Vbody starts to decrease until the threshold voltage is reached. In this case, ton is positive when again defined as the time of the falling edge of QN minus the time of the rising edge of GL. Therefore, by comparing ton when the low-side switch QL is turned on with a threshold value of zero, the polarity of the current Iout can be determined.

Finally, measuring the turn-off delay of the low-side switch QL and deriving the polarity of the output current from this measurement will be explained with respect to FIGS. 13 and 14 .

13A and 13B show the case where the polarity of the current Iout is positive, as indicated by arrow 131 . In this case, current flows through the diode DL during the dead time as shown by the dashed line 130 . Therefore, the body voltage Vbody remains low even after the falling edge of GL indicating that the low-side switch QL is to be turned off, and rises only after the rising edge of GH turns on the high-side switch QH. Therefore, the turn-off delay toff measured as the difference between the rising edge of Qon and the falling edge of GL in this case corresponds to the dead time td plus the turn-on time of the high-side switch QH, and is greater than the delay time td.

14A and 14B show the case where the polarity of the current Iout is negative, as indicated by arrow 141 in FIG. 14A. Here, current flows through the diode DH during the dead time as shown by the dashed line 140 . Immediately after the falling edge of GL, the bulk voltage Vbody across the low-side switch QL begins to rise, and in this case the device off-time toff corresponds to the inherent off-time required by the low-side switch QL. In particular, tof is less than td in this case. Therefore, in this case, the polarity of the current Iout can be determined by comparing toff with td as a threshold value.

In summary, by measuring the turn-on delay or turn-off delay of the high-side switch QH or the low-side switch QL as the switching delay, and by comparing the corresponding delay with a threshold (eg, zero or dead time td), the polarity of the current Iout can be determined sex. In the case of Iout>0 and Iout<0, other thresholds between the respective switching delays than zero or dead time td can also be used. For example, in other embodiments, the threshold may have a value between a negative value and a value less than the actual turn-on delay time. A suitable value for the threshold can be determined experimentally. For example, for various known test currents with known polarities, a threshold value can be chosen that gives a correctly determined polarity of all test currents. In this way, a threshold value that takes system noise into account can be determined.

It should be noted that, in terms of practical implementation, in some cases, especially in some high-voltage systems, it may be advantageous to measure the turn-on delay of the low-side switch QL, since the second potential 31 is often in such devices is a common ground, and in such cases it may be easier to couple eg the delay measurement circuit of Figure 6 with the low-side switch QL, eg in terms of isolation between voltage domains.

As described above, the switching delays of both the high-side and low-side switches of a half-bridge can be used to determine the polarity of the current through the respective half-bridge. Furthermore, in some applications, multiple half-bridges may be provided, such as three half-bridges for a three-phase inverter to drive a three-phase motor. In this case, common circuitry including one or more multiplexers can be used as a delay measurement circuit for multiple switches. An example of a measurement circuit 150 usable in an embodiment is shown in FIG. 15 .

The measurement circuit 150 is designed for a system comprising a three-phase inverter based on three half-bridges, each half-bridge comprising a corresponding high-side switch (HS1-HS3 in the signal of FIG. 15) and a corresponding low-side switch ( LS1-LS3 in the signal of Figure 15).

Signals from respective comparators assigned to switches HS1-HS3, LS1-LS3 (each comparator comparing body voltage Vbody (eg drain source voltage Vds) to a threshold) are provided to the first multiplexer device 151A. Control signals (similar to the signals GH, GH of FIG. 3 ) that control the switches are supplied to the second multiplexer 151B. Using the first multiplexer 151A and the second multiplexer 151B, one of the switches is selected for delay measurement. The selected respective signals are provided to circuitry 152A, 152B, respectively. Each circuitry 152A, 152B includes an edge detection circuit for detecting a rising edge, an edge detection circuit for detecting a falling edge, and an edge signal that selects the detected rising edge or the detected falling edge as an output based on the signal edgeel Selection circuits, such as multiplexers.

The selected detected edge is provided to the stop and start inputs of counter 154, which has essentially the same function as counter 61 of FIG. 6, respectively. Counter 154 is clocked by clock signal clk. The counter 154 outputs the switching delay tdel.

In addition, the output of circuitry 152 provided to the stop input of counter 154 is additionally provided to the set input of latch 153 clocked by clock signal clk. The latch 153 outputs a signal delcom indicating the completion of the delay measurement.

Based on the detected edge, the counter 154 and latch 153 are also reset after each delay measurement for the next delay measurement. An external reset signal, labeled reset in Figure 15, can also be applied.

For example, if you want to measure the turn-on delay of a low-side switch, you can select the rising edge with the signal edgeel. Then, the rising edge of the corresponding signal LSx_ON (x=1-3) selected by the multiplexer 151B triggers the counter 154 to start, and the falling edge of the Vds_comp_o_LSx (x=1-3) selected by the multiplexer 151A The counter is stopped and the completion signal delcom is asserted. A falling edge of LSx_ON or a rising edge of Vds_comp_o_LSx then resets the counter 154 and latch 153 in preparation for the next delay measurement.

In some embodiments, the measurement circuit 150 may be a measurement circuit that is also used for other purposes, eg, to detect whether the corresponding switches HS1-HS3, LS1-LS3 are in "Good condition". In some conventional devices, such monitoring of the health of switches based on switching delays has been used. In this case, in an embodiment, the measurement circuit already provided for this monitoring can additionally be used to detect the polarity of the current through the half-bridge by comparing tdel with a threshold, as described above, and thus almost No additional circuitry is required.

In Figure 15, multiplexers 151A, 151B are used so that only one counter 154 is provided for multiple switches, thus switching delay and polarity can be measured for only one switch at a time. The switching of the low-side switch and the high-side switch typically occurs at or near the zero-crossing of the respective current Iout of the respective half-bridge. Therefore, in an embodiment, the zero-crossings of the currents of the different half-bridges are predicted and the switches used to measure the switching delay are selected based on this prediction. An example will be explained with reference to FIGS. 16 and 17 .

Figure 16 shows three output currents Ia, Ib and Ic as typical outputs of a three-phase inverter. This operation can be divided into six stages labeled I to VI in FIG. 16 . At each stage, one of the currents crosses zero. Specifically, the relationship between the currents from the first stage to the sixth stage is:

I: Ib>Ia>Ic

II: Ib>Ic>Ia

III: Ic>Ib>Ia

IV: Ic>Ia>Ib

V: Ia>Ic>Ib

VI: Ia>Ib>Ic

In each of phases I to VI, a corresponding "intermediate current" Ia, Ib or Ic (which is of magnitude between the respective magnitudes of the other two currents) forms a zero-crossing.

For the half bridge generating this "intermediate current", at each stage, the polarity can be determined based on the techniques discussed above. For the three currents Ia, Ib, and Ic, at least ideally, the relation Ia+Ib+Ic=0 holds. When the phase angle θ=ωt, where ω is the angular frequency of the current I, and t is the time, the currents Ia, Ib, and Ic can be written as:

Ia=I·sin(θ)

Ib=I·sin(θ-2/3π)

Ic=I·sin(θ-4/3π)

For the six stages I to VI, the following applies to the phase angle θ:

I: 5/6π<θ<7/6π

II: 7/6π<θ<3/2

III: 3/2π<θ<11/6π

IV: 11/6π<θ<13/6π

V: 2/6π<θ<2/2π

VI: 2/2π<θ<5/6π

Based on this, the phase angle θ can be determined using the circuit shown in FIG. 17 . The currents Ia, Ib, Ic are Clarke transformed 170 and then Park transformed 171. The output signal of Park transform 171 is provided to a proportional integral (PI) controller 172 to obtain an angular velocity ω, which is then integrated by an integrator 173 . The resulting phase angle θ is fed back to Park Transform 171 . In this way, the phase angle θ can be determined and, in an embodiment, based on the phase angle θ, for example by using the multiplexers 151A, 151B of FIG. The high-side switch is selected for the case (zero-crossing in the positive direction, eg, in stages II, IV, and VI of Figure 16), and the corresponding low-side switch is selected for the remaining stages, which corresponds to the analysis of the turn-on delay. As mentioned above, a reverse selection can also be done to analyze the cutoff delay.

Next, some measurements showing the effects of the techniques discussed herein will be described with reference to Figure 18, which includes Figures 18A-18D.

Measurements have been performed on a half-bridge of a three-phase inverter driving a three-phase brushless DC motor with vector control at 20Hz, a dead time of 1μs, and a switching frequency of 20kHz. Figures 18A and 18B show the measurement results without applying the dead time compensation technique. In FIG. 18A, curve 180 shows the output voltage, and curve 181 shows the frequency spectrum of the output voltage obtained by Fast Fourier Transform (FFT). It can be seen that in addition to the fundamental frequency component, there are also strong fifth and seventh harmonics. Curve 183 shows the output current with visible distortion.

Figures 18C and 18D show measurement results for the case where the polarity detection based dead time compensation as described herein has been applied. Figure 18C corresponds to Figure 18A, with curve 184 showing the output voltage and curve 185 showing the spectrum obtained by the Fast Fourier Transform. It can be seen that compared to curve 181, the fifth and seventh harmonics are suppressed. This produces the output current shown by curve 186 of Figure 18D with reduced distortion.

Some embodiments are defined by the following examples:

Example 1. A method for determining the polarity of current through a half-bridge, comprising:

determining a switching delay of at least one of a high-side switch or a low-side switch of the half-bridge, and

The polarity of the current through the half bridge is determined based on the switching delay.

Example 2. The method of example 1, wherein the polarity of the current through the half-bridge is determined based on a comparison of the switching delay to a threshold.

Example 3. The method of example 2, wherein the threshold is zero.

Example 4. The method of example 2, wherein the threshold is substantially equal to the dead time of the half bridge.

Example 5. The method of any one of examples 1-4, wherein the switching delay of the at least one of the high-side switch or the low-side switch of the half-bridge is determined as: The nominal switching time of the control signal according to the at least one of the high-side switch or the low-side switch and the voltage across the at least one of the high-side switch or the low-side switch The time difference between the times when the threshold voltage is predefined.

Example 6. The method of example 5, wherein the nominal switching time includes the time of a rising or falling edge of the control signal.

Example 7. The method of example 5 or 6, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and the threshold voltage is a threshold voltage of the transistor switch.

Example 8. The method of any one of examples 5-7, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and wherein the high-side switch or all The voltage of the at least one of the low-side switches includes at least one of a voltage between a load terminal of the transistor switch or a voltage between a control terminal and a load terminal of the transistor switch.

Example 9. The method of any one of examples 1-7, wherein the switching delay comprises at least one of an off delay or an on delay.

Example 10. The method of any one of examples 1 to 9, wherein the current is a current through a node between the high-side switch and the low-side switch.

Example 11. The method of any one of examples 1 to 10, further comprising selecting the half-bridge from a plurality of half-bridges for determining the switching delay based on phase angle prediction.

Example 12. A method for dead time compensation in a half bridge, comprising:

determining the polarity of current through the half-bridge according to the method of any one of Examples 1 to 11, and

The method of any of claims 1 to 8 to determine the polarity of the current through the half-bridge, and.

Example 13. The method of Example 12, wherein applying the dead-time compensation comprises at least one of: modifying a reference voltage on which control of the half-bridge is based; or modifying a pulse width modulation mode, The half bridge is controlled according to the pulse width modulation pattern.

Example 14. A half-bridge controller comprising:

a measurement circuit configured to determine the switching delay of at least one of the high-side switch or the low-side switch of the half-bridge, and

A control circuit configured to determine a polarity of current through the half-bridge based on the switching delay.

Example 15. The half-bridge controller of example 14, wherein to determine the polarity of the current through the half-bridge, the control circuit is configured to compare the switching delay to a threshold.

Example 16. The half-bridge controller of example 15, wherein the threshold is zero.

Example 17. The half-bridge controller of Example 15, wherein the threshold is substantially equal to a dead time of the half-bridge.

Example 18. The half-bridge controller of any one of examples 14-17, wherein the measurement circuit is configured to connect the at least one of the high-side switch or the low-side switch of the half-bridge The switching delay of one is determined as the difference between the nominal switching time of the control signal of the at least one of the high-side switch or the low-side switch and the difference across the high-side switch or the low-side switch The time difference between the times when the voltage of the at least one of the crosses a predefined threshold voltage.

Example 19. The half-bridge controller of Example 18, wherein the measurement circuit includes a comparator, wherein a first input of the comparator is configured to receive a signal across the high-side switch or the low-side switch. the voltage of the at least one, and a second input of the comparator is configured to receive the threshold voltage.

Example 20. The half-bridge controller of example 19, wherein the measurement circuit comprises a counter, wherein a first input of the counter is coupled to an output of the comparator, wherein a second input of the counter is configured as receiving the control signal, and wherein the counter is configured to start counting based on a first signal at one of the first input or the second input, and based on the first input or the second input A second signal at the other of the two inputs to stop counting.

Example 21. The half-bridge controller of any one of examples 18-20, wherein the nominal switching time includes the time of a rising or falling edge of the control signal.

Example 22. The half-bridge controller of any one of examples 18-21, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and the threshold voltage is all Threshold voltage of the transistor switch.

Example 23. The half-bridge controller of any one of examples 18-22, wherein the at least one of the high-side switch or the low-side switch is a transistor switch, and wherein the high-side switch is The voltage of the at least one of the switch or the low-side switch includes at least one of a voltage between a load terminal of the transistor switch or a voltage between a control terminal and a load terminal of the transistor switch .

Example 24. The half-bridge controller of any of examples 14-23, wherein the switching delay includes at least one of a turn-off delay or a turn-on delay.

Example 25. The half-bridge controller of any one of examples 14-24, wherein the current through the half-bridge is a current through a node between the high-side switch and the low-side switch.

Example 26. The half-bridge controller of any one of Examples 14 to 25, further comprising:

a prediction circuit configured to predict the phase angles of the plurality of half bridges, and

a multiplexer configured to select the half-bridge from the plurality of half-bridges for determining the switching delay based on the phase angle.

Example 27. The half-bridge controller of any one of examples 14-26, wherein the control circuit is further configured to apply dead-time compensation based on the polarity of the current through the half-bridge .

Example 28. The half-bridge controller of Example 27, wherein the control circuit is configured to apply the dead-time compensation by at least one of: modifying a reference voltage, the control of the half-bridge based on the the reference voltage; or modify the pulse width modulation mode according to which the half-bridge is controlled.

Example 29. A system comprising a half bridge and the half bridge controller of any of examples 14-28.

While specific embodiments have been shown and described herein, those of ordinary skill in the art will appreciate that various alternative and/or equivalent implementations may be substituted for the specific implementations shown and described without departing from the scope of the invention example. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims (20)

1. A method for determining the polarity of a current (Iout) through a half-bridge (21), comprising: determining the switching delay (tdel, ton, toff) of at least one of the high-side switch (QH) or the low-side switch (QL) of the half-bridge (21), and The polarity of the current (Iout) through the half-bridge (21) is determined based on the switching delays (tdel, ton, toff). 2. The method of claim 1, wherein the polarity of the current (Iout) through the half-bridge (21) is based on a comparison of the switching delay (tdel, ton, toff) with a threshold value definite. 3. The method of claim 1 or 2, wherein the switching delay of the at least one of the high-side switch (QH) or the low-side switch (QL) of the half-bridge (21) (tdel, ton, toff) is determined as: the nominal switching time according to the control signal (GH, GL) of the at least one of the high-side switch (QH) or the low-side switch (QL) and The time difference between times when the voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) crosses a predefined threshold voltage. 4. The method of claim 3, wherein the nominal switching time comprises the time of a rising or falling edge of the control signal (GH, GL). 5. The method of claim 3 or 4, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and the threshold voltage is the Threshold voltage for transistor switching. 6. The method of any one of claims 3 to 5, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and wherein all The voltage (Vbody) of the at least one of the high-side switch (QH) or the low-side switch (QL) includes a voltage between load terminals of the transistor switch or a control terminal of the transistor switch and at least one of the voltages between the load terminals. 7. The method of any one of claims 1 to 6, wherein the switching delay (tdel, ton, toff) comprises at least one of a turn-off delay (toff) or a turn-on delay (ton). 8. The method according to any of claims 1 to 7, further comprising selecting all half-bridges (21) for determining the switching delay (tdel, ton, toff) based on phase angle prediction The half bridge (21) is described. 9. A method for dead time (td) compensation in a half bridge (21), comprising: determining the polarity of the current (Iout) through the half-bridge (21) according to the method of any one of claims 1 to 8, and Dead time (td) compensation is applied based on the polarity of the current (Iout) through the half bridge (21). 10. The method of claim 9, wherein applying the dead time (td) compensation comprises at least one of: modify the reference voltage on which the control of the half-bridge (21) is based, or The pulse width modulation mode is modified according to which the half bridge (21) is controlled. 11. A half-bridge controller (20), comprising: a measurement circuit (23) configured to determine the switching delay (tdel, ton, toff) of at least one of the high-side switch (QH) or the low-side switch (QL) of the half-bridge (21), and A control circuit (22) configured to determine the polarity of the current (Iout) through the half-bridge (21) based on the switching delays (tdel, ton, toff). 12. The half-bridge controller (20) of claim 11, wherein in order to determine the polarity of the current through the half-bridge, the control circuit (22) is configured to delay the switching (tdel, ton, toff) is compared to the threshold. 13. The half-bridge controller (20) according to claim 11 or 12, wherein the measurement circuit (23) is configured to switch the high-side switch (QH) of the half-bridge (21) or the The switching delay (tdel, ton, toff) of the at least one of the low-side switches (QL) is determined as a function of the high-side switch (QH) or the low-side switch (QL) The nominal switching time of at least one of the control signals (GH, GL) and the voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) exceed a predefined The time difference between the threshold voltage times. 14. The half-bridge controller (20) of claim 13, wherein the measurement circuit (23) comprises a comparator (60), wherein a first input of the comparator (60) is configured to receive a the voltage (Vbody) of the at least one of the high-side switch (QH) or the low-side switch (QL), and a second input of the comparator (60) is configured to receive the threshold value Voltage. 15. The half-bridge controller (20) of claim 14, wherein the measurement circuit (23) comprises a counter (61; 154), wherein a first input of the counter (61; 154) is coupled to the the output of the comparator (60), wherein the second input of the counter (61; 154) is configured to receive the control signal (GH, GL), and wherein the counter (61; 154) is configured to be based on the Counting is started based on a first signal at one of the first input or the second input, and counting is stopped based on a second signal at the other of the first input or the second input. 16. The half-bridge controller (20) of any one of claims 13 to 15, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and the threshold voltage is the threshold voltage of the transistor switch. 17. The half-bridge controller (20) of any one of claims 13 to 16, wherein the at least one of the high-side switch (QH) or the low-side switch (QL) is a transistor switch, and wherein the voltage (Vbody) across the at least one of the high-side switch (QH) or the low-side switch (QL) includes the voltage between load terminals of the transistor switch or all at least one of the voltages between the control terminal and the load terminal of the transistor switch. 18. The half-bridge controller of any one of claims 11 to 17, further comprising: prediction circuits (170-173) configured to predict phase angles for the plurality of half bridges (21), and a multiplexer (151A, 151B) configured to select the half-bridge from the plurality of half-bridges (21) for determining the switching delay (tdel, ton, toff) based on the phase angle (twenty one). 19. The half-bridge controller (20) according to any one of claims 11 to 18, wherein the control circuit (22) is further configured to be based on the current (Iout) through the half-bridge (21) ) to apply dead time (td) compensation. 20. A system comprising a half bridge (21) and a half bridge controller (20) according to any of claims 11 to 19.

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