CN111814207B - Field programmable gate array data processing method and device, and readable storage medium - Google Patents

Abstract

The application discloses a field programmable gate array data processing method and device and a readable storage medium, wherein the method comprises the following steps: acquiring first configuration data to enable the field programmable gate array to enter a working state; wherein the first configuration data is stored in the first memory; acquiring second configuration data sent by the first logic processing unit, so that the field programmable gate array reorganizes the first configuration data and the second configuration data to obtain third configuration data; the field programmable gate array is configured based on the third configuration data. By the method, the problem that the configuration data of the field programmable gate array is easy to copy and clone in the prior art is solved, and the data security of the field programmable gate array is enhanced.

Description

Field programmable gate array data processing method and device, and readable storage medium

Technical Field

The present application relates to the field of data processing, and in particular to a field programmable gate array data processing method and device, and a readable storage medium.

Background Art

FPGA (Field Programmable Gate Array) has high integration and flexible programming, and is more suitable for completing sequential logic, so it is widely used in fields such as communications, medical, aviation, automotive electronics, ASIC (Application Specific Integrated Circuit) prototype verification, etc. By utilizing the flexible programming characteristics of FPGA, the purpose of improving product functions and upgrading services can be achieved by upgrading the FPGA firmware. However, the current FPGA is programmed based on SRAM (Static Random Access Memory). Since SRAM cannot save configuration data after power failure, the FPGA becomes a "blank chip", so the configuration must be reloaded every time the FPGA is powered on. In the related art, there is already a method that uses the electronic erasable programmable and fast data reading characteristics of Flash memory (flash memory) to cooperate with FPGA to achieve the purpose of saving the last used configuration after power failure. This method requires the loading file to be stored in the Flash memory in advance, and the loading file is read from the Flash memory after power-on to configure the FPGA, but the configuration data in the Flash is easily copied and cloned, thereby causing the leakage of system security and privacy information.

Summary of the invention

In order to solve the above problems, the present application provides a field programmable gate array data processing method and device, and a readable storage medium, which solves the problem in the prior art that field programmable gate array configuration data is easily copied and cloned, and enhances the data security of the field programmable gate array.

A technical solution adopted in the present application is to provide a field programmable gate array data processing method, the method comprising: obtaining first configuration data to enable the field programmable gate array to enter a working state; wherein the first configuration data is stored in a first memory; obtaining second configuration data sent by a first logic processing unit, so that the field programmable gate array recombines the first configuration data and the second configuration data to obtain third configuration data; and configuring the field programmable gate array based on the third configuration data.

Before obtaining the second configuration data sent by the first logic processing unit, the method includes: in response to the field programmable gate array entering a working state, controlling the second logic processing unit to send the second configuration data to the first logic processing unit.

The method further includes: controlling the second logic processing unit to send fourth configuration data to the first logic processing unit, so that the first logic processing unit stores the fourth configuration data in the second memory.

The method further includes: controlling the second logic processing unit to send a load command to the first logic processing unit so that the first logic processing unit obtains target configuration data corresponding to the load command from the second memory; and controlling the first logic processing unit to load the target configuration data into the field programmable gate array.

Among them, after controlling the first logic processing unit to load the target configuration data into the field programmable gate array, it includes: controlling the field programmable gate array to reorganize the first configuration data and the target configuration data to obtain fourth configuration data; and configuring the field programmable gate array based on the fourth configuration data.

Among them, after controlling the field programmable gate array to reorganize the first configuration data and the target configuration data to obtain the fourth configuration data, it includes: obtaining the second configuration data of the field programmable gate array, storing the second configuration data in the second memory, and deleting the second configuration data and the third configuration data in the field programmable gate array.

Another technical solution adopted in the present application is to provide a field programmable gate array data processing device, which includes: a first logic processing unit; a first memory, used to store first configuration data; a field programmable gate array, connected to the first logic processing unit and the first memory, used to obtain the first configuration data from the first memory, and when obtaining the second configuration data sent by the first logic processing unit, recombining the first configuration data and the second configuration data to obtain third configuration data, and configuring based on the third configuration data.

The data processing device further includes a second logic processing unit connected to the first logic processing unit and configured to send second configuration data to the first logic processing unit.

The data processing device further includes a second memory connected to the first logic processing unit; the first logic processing unit is further configured to store the fourth configuration data in the second memory when the fourth configuration data sent by the second logic processing unit is obtained; or the first logic processing unit is further configured to obtain target configuration data corresponding to the load command from the second memory when the load command sent by the second logic processing unit is obtained, and load the target configuration data into the field programmable gate array.

Another technical solution adopted by the present application is to provide a readable storage medium, characterized in that the readable storage medium is used to store program data, and the program data is used to implement the method provided by the above technical solution when executed by the processor.

The beneficial effect of the present application is that, different from the prior art, the field programmable gate array data processing method and device provided by the present application divides the configuration data of the field programmable gate array into two parts, the first configuration data belonging to the basic data is stored in the first memory, and the second configuration data belonging to the core data is sent to the field programmable gate array by the first logic processing unit for configuration after the field programmable gate array enters the working state using the basic data. On the one hand, the problem that the configuration data in the prior art is easy to be copied and cloned is solved, and on the other hand, the data security of the field programmable gate array when working is enhanced under the premise of ensuring the loading speed of the configuration data.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

FIG1 is a schematic structural diagram of a first embodiment of a field programmable gate array data processing device provided by the present application;

FIG2 is a schematic diagram of the structure of a second embodiment of a field programmable gate array data processing device provided by the present application;

3 is a schematic structural diagram of a third embodiment of a field programmable gate array data processing device provided by the present application;

FIG4 is a flow chart of a first embodiment of a field programmable gate array data processing method provided by the present application;

5 is a flow chart of a second embodiment of a field programmable gate array data processing method provided by the present application;

FIG. 6 is a schematic diagram of the structure of an embodiment of a readable storage medium provided in the present application.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

1 is a schematic diagram of the structure of a first embodiment of a field programmable gate array data processing device provided by the present application. The field programmable gate array data processing device 10 includes a first logic processing unit 11, a first memory 12 and a field programmable gate array 13.

The first logic processing unit 11 may be a CPLD (Complex Programmable Logic Device). It is composed of programmable interconnection matrix units around the center, wherein the LMC logic structure is relatively complex and has a complex I/O unit interconnection structure. Users can generate specific circuit structures as needed to complete certain functions. Since the CPLD uses metal wires of fixed length to interconnect the logic blocks, the designed logic circuit has time predictability, avoiding the disadvantage of incomplete timing prediction of the segmented interconnection structure. In addition, the CPLD has good confidentiality.

The first memory 12 may be a FLASH memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory), and is used to store first configuration data, wherein the first configuration data can be used for the field editable gate array 13 to enter a working state.

The field editable gate array 13 is connected to the first memory 12 and the first logic processing unit 11, and is used to obtain the first configuration data from the first memory 12, and when the second configuration data sent by the first logic processing unit 11 is obtained, the first configuration data and the second configuration data are recombined to obtain the third configuration data, and configuration is performed based on the third configuration data.

In some embodiments, when the field programmable gate array data processing device 10 is powered on, the field editable gate array 13 obtains the first configuration data from the first memory 12, wherein the first configuration data is basic data. Based on the first configuration data, the field editable gate array 13 is initialized, enters the working state, and realizes the basic functions. Then the field editable gate array 13 obtains the second configuration data sent by the first logic processing unit 11, recombines the first configuration data and the second configuration data to obtain the third configuration data, and configures based on the third configuration data. Among them, the second configuration data is the core data. It can be understood that the second configuration data can come from the external memory, or can be sent to the first logic processing unit 11 by an external device, and then the first logic processing unit 11 sends the second configuration data to the field editable gate array 13 when detecting that the field editable gate array 13 enters the working state.

In some embodiments, the field programmable gate array data processing device 10 further includes a second logic processing unit. The second logic processing unit is connected to the first logic processing unit 11 and is used to send second configuration data to the first logic processing unit 11. For example, when the field programmable gate array 13 enters the working state, the second logic processing unit is triggered to send the second configuration data to the first logic processing unit 11. Then the first logic processing unit 11 sends the second configuration data to the field programmable gate array 13.

Different from the prior art, the field programmable gate array data processing device of the present application divides the configuration data of the field programmable gate array into two parts, wherein the first configuration data belonging to the basic data is stored in the first memory, and the second configuration data belonging to the core data is sent to the field programmable gate array by the first logic processing unit for configuration after the field programmable gate array enters the working state using the basic data. On the one hand, the problem that the configuration data in the prior art is easily copied and cloned is solved, and on the other hand, the data security of the field programmable gate array during operation is enhanced under the premise of ensuring the loading speed of the configuration data.

2 is a schematic diagram of the structure of the second embodiment of the field programmable gate array data processing device provided by the present application. The field programmable gate array data processing device 20 includes a first logic processing unit 21, a first memory 22, a field programmable gate array 23, a second logic processing unit 24 and a second memory 25.

The first memory 22 is connected to the field editable gate array 23. The first logic processing unit 21 is connected to the field editable gate array 23, the second logic processing unit 24 and the second memory 25.

When the field programmable gate array data processing device 20 is powered on, the field editable gate array 23 obtains the first configuration data from the first memory 22, wherein the first configuration data is basic data. Based on the first configuration data, the field editable gate array 23 is initialized, enters the working state, and realizes the basic functions. Then the second logic processing unit 24 sends the second configuration data to the first logic processing unit 21, so that the first logic processing unit 21 sends the second configuration information to the field editable gate array 23. The field editable gate array 23 reorganizes the first configuration data and the second configuration data to obtain the third configuration data, and configures based on the third configuration data. Among them, the second configuration data is the core data. It can be understood that the second configuration data can come from the external memory, or can be sent to the second logic processing unit 24 by an external device, and then the second logic processing unit 24 sends the second configuration data to the first logic processing unit 21 when detecting that the field editable gate array 23 enters the working state.

In some embodiments, the first logic processing unit 21 is also used to store the fourth configuration data in the second memory 25 when the fourth configuration data sent by the second logic processing unit 24 is obtained. The fourth configuration data also belongs to the core data. In an application scenario, when the field programmable gate array data processing device 20 is powered on, the field editable gate array 23 obtains the first configuration data from the first memory 22, wherein the first configuration data is basic data. Based on the first configuration data, the field editable gate array 23 is initialized, enters the working state, and realizes the basic functions. Then the second logic processing unit 24 sends a load command to the first logic processing unit 21 to enable the first logic processing unit 21 to obtain the fourth configuration data from the second memory 25, and load the fourth configuration information to the field editable gate array 23, so that the field editable gate array 23 completes the configuration.

In some embodiments, a plurality of configuration data are stored in the second memory 25, and these configuration data are all core data. In an application scenario, when the field editable gate array 23 needs to change the configuration, the second logic processing unit 24 sends a load command to the first logic processing unit 21, so that the first logic processing unit 21 parses the load instruction to obtain the target configuration data from the second memory, and loads the target configuration information to the field editable gate array 23, so that the field editable gate array 23 completes the configuration based on the target configuration information. Specifically, before completing the configuration, the first logic processing unit 21 can save the original configuration information in the field editable gate array 23 to the second memory, and delete the original configuration information in the field editable gate array 23. It can be understood that the original configuration information here is the core data. For example, the second memory 25 stores configuration data A, B, and C, and these configuration data are all core data. The second logic processing unit 24 sends a load command for loading configuration data A to the first logic processing unit 21, so that the first logic processing unit 21 parses the load instruction to obtain configuration data A from the second memory, and loads the configuration data A to the field editable gate array 23, so that the field editable gate array 23 completes the configuration based on the configuration data A. If the second logic processing unit 24 sends a load command for loading configuration data B to the first logic processing unit 21, so that the first logic processing unit 21 parses the load instruction to obtain configuration data B from the second memory, and loads the configuration data B to the field editable gate array 23, so that the field editable gate array 23 completes the configuration based on the configuration data B.

Refer to FIG3, which is a schematic diagram of the structure of the third embodiment of the field programmable gate array data processing device provided by the present application. The field programmable gate array data processing device includes a CPU (Central Processing Unit/Processor), a CPLD, a DDR (Double Data Rate SDRAM), an FPGA and a FLASH. Among them, the CPU is connected to the CPLD; the CPLD is connected to the DDR and the FPGA; and the FPGA is connected to the FLASH.

The FLASH is used to store first configuration data, which is basic data for configuring the FPGA. When the system is powered on, the FPGA can enter a working state based on the first configuration data.

The CPLD is used to obtain the second configuration data sent by the CPU when the system is powered on, and send the second configuration data to the FPGA so that the FPGA completes the configuration. The configuration data is the core data for configuring the FPGA, and the FPGA can complete the core configuration based on the second configuration data.

After the FPGA completes the configuration, the CPU can send multiple configuration data to the CPLD. After receiving the multiple configuration data, the CPLD stores it in the DDR. In the subsequent work, the CPLD obtains the corresponding target configuration data from the DDR according to the load command issued by the CPU. And sends it to the FPGA so that the FPGA can complete the core configuration based on the target configuration data. The above prerequisite is that the entire system is always powered on.

When the system is powered off, the configuration data in the FPGA will be cleared and the data in the DDR will also be cleared. This method can improve the data security of the entire system.

In this embodiment, the encryption characteristics of CPLD and the method of storing only basic data in FLASH are used to improve the data security of the entire system. At the same time, the characteristic that the data in DDR disappears when the power is off is used to improve the system security. In addition, multiple core configuration files are stored in DDR to realize dynamic loading of FPGA configuration data.

Refer to FIG. 4 , which is a flow chart of a first embodiment of a field programmable gate array data processing method provided by the present application. The method includes:

Step 41: Acquire first configuration data to enable the field programmable gate array to enter a working state.

The first configuration data is stored in the first memory, and the first configuration data is basic data. The first memory can be a FLASH memory or an EEPROM.

In some embodiments, step 41 is applied to obtain first configuration data from the first memory when the system is powered on, so as to put the field programmable gate array into working state.

Step 42: Acquire the second configuration data sent by the first logic processing unit, so that the field programmable gate array recombines the first configuration data and the second configuration data to obtain third configuration data.

The first logic processing unit is a microcontroller, such as an MCU, which is provided with an internal storage unit storing second configuration data, which is core data.

In some embodiments, before step 42, in response to the field programmable gate array entering the working state, the second logic processing unit is controlled to send the second configuration data to the first logic processing unit, wherein the second logic processing unit is a CPU.

Step 43: Configure the field programmable gate array based on the third configuration data.

In some embodiments, the method further includes controlling the second logic processing unit to send the fourth configuration data to the first logic processing unit, so that the first logic processing unit stores the fourth configuration data in the second memory. The second memory may be an external memory connected to the first logic processing unit when the system needs to use it. When the second logic processing unit sends the fourth configuration data to the first logic processing unit, the first logic processing unit stores the fourth configuration data in the second memory.

Different from the prior art, the field programmable gate array data processing method of the present application divides the configuration data of the field programmable gate array into two parts, the first configuration data belonging to the basic data is stored in the first memory, and the second configuration data belonging to the core data is sent to the field programmable gate array by the first logic processing unit for configuration after the field programmable gate array uses the basic data to enter the working state. On the one hand, it solves the problem that the configuration data in the prior art is easy to be copied and cloned, and on the other hand, it enhances the data security of the field programmable gate array when it is working under the premise of ensuring the loading speed of the configuration data.

Refer to FIG. 5 , which is a flow chart of a second embodiment of a field programmable gate array data processing method provided by the present application. The method includes:

Step 51: Control the second logic processing unit to send a load command to the first logic processing unit, so that the first logic processing unit obtains target configuration data corresponding to the load command from the second memory.

It can be understood that a plurality of configuration data are stored in the second memory, and these configuration data are all core data. When the field editable gate array needs to change the configuration, the second logic processing unit sends a load command to the first logic processing unit, so that the first logic processing unit parses the load instruction and obtains the target configuration data corresponding to the load command from the second memory.

Step 52: Control the first logic processing unit to load the target configuration data into the field programmable gate array.

Step 53: Control the field programmable gate array to reorganize the first configuration data and the target configuration data to obtain fourth configuration data.

For example, if the second memory stores configuration data A, B, and C, which are all core data, the second logic processing unit sends a load command for loading configuration data A to the first logic processing unit, so that the first logic processing unit parses the load instruction to obtain configuration data A from the second memory, and loads configuration data A to the field editable gate array, so that the field editable gate array is reorganized based on configuration data A and the first configuration data and target configuration data obtained from the first memory to obtain fourth configuration data.

In some embodiments, after step 53, the second configuration data of the field programmable gate array is obtained, the second configuration data is stored in the second memory, and the second configuration data and the third configuration data in the field programmable gate array are deleted. In this way, the storage space of the field programmable gate array is updated, and the previous core configuration data is saved in the second memory, so that the configuration data can be reused and has high security.

Step 54: Configure the field programmable gate array based on the fourth configuration data.

After step 54, if the field programmable gate array needs to change its configuration, the second logic processing unit sends a load command for loading configuration data B to the first logic processing unit, so that the first logic processing unit parses the load instruction to obtain configuration data B from the second memory, and loads configuration data B into the field programmable gate array, so that the field programmable gate array completes the configuration based on configuration data B.

In this embodiment, multiple core configuration data are stored in the second memory to achieve dynamic loading of field editable gate array configuration data.

Refer to FIG6 , which is a schematic diagram of the structure of an embodiment of a readable storage medium provided by the present application. The readable storage medium 60 is used to store program data 61 , and the program data 61 is used to implement the following method steps when executed by a processor:

Acquire first configuration data to enable a field programmable gate array to enter a working state; wherein the first configuration data is stored in a first memory; acquire second configuration data sent by a first logic processing unit, so that the field programmable gate array recombines the first configuration data and the second configuration data to obtain third configuration data; and configure the field programmable gate array based on the third configuration data.

It can be understood that the program data 61 is also used to implement any of the above-mentioned embodiment methods when executed by the processor.

In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present implementation scheme.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.

The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims (10)

1. A field programmable gate array data processing method, characterized in that the method comprises: When the field programmable gate array data processing device is powered on, the field programmable gate array obtains first configuration data from the first memory, the first configuration data is basic data, and the field programmable gate array is initialized based on the first configuration data to enter a working state; The field programmable gate array obtains the second configuration data sent by the first logic processing unit, recombines the first configuration data and the second configuration data to obtain third configuration data; and configures the field programmable gate array based on the third configuration data; The second configuration data comes from an external memory, or is sent to the first logic processing unit by an external device. Then, when the first logic processing unit detects that the field editable gate array enters a working state, the second configuration data is sent to the field editable gate array. 2. The method according to claim 1, characterized in that Before obtaining the second configuration data sent by the first logic processing unit, the method includes: In response to the field programmable gate array entering the working state, the second logic processing unit is controlled to send second configuration data to the first logic processing unit. 3. The method according to claim 1, characterized in that The method further comprises: The second logic processing unit is controlled to send fourth configuration data to the first logic processing unit, so that the first logic processing unit stores the fourth configuration data in the second memory. 4. The method according to claim 1, characterized in that The method further comprises: Controlling the second logic processing unit to send a load command to the first logic processing unit, so that the first logic processing unit obtains target configuration data corresponding to the load command from the second memory; The first logic processing unit is controlled to load the target configuration data into the field programmable gate array. 5. The method according to claim 4, characterized in that After the controlling the first logic processing unit to load the target configuration data into the field programmable gate array, the method includes: controlling the field programmable gate array to reorganize the first configuration data and the target configuration data to obtain fourth configuration data; The field programmable gate array is configured based on the fourth configuration data. 6. The method according to claim 5, characterized in that After the controlling the field programmable gate array to reorganize the first configuration data and the target configuration data to obtain fourth configuration data, the method further comprises: The second configuration data of the field programmable gate array is acquired, the second configuration data is stored in the second memory, and the second configuration data and the third configuration data in the field programmable gate array are deleted. 7. A field programmable gate array data processing device, characterized in that the data processing device comprises: a first logic processing unit; A first memory, used to store first configuration data; A field programmable gate array, when the field programmable gate array data processing device is powered on, the field programmable gate array obtains first configuration data from a first memory, the first configuration data is basic data, and the field programmable gate array is initialized based on the first configuration data to enter a working state; The field programmable gate array obtains the second configuration data sent by the first logic processing unit, recombines the first configuration data and the second configuration data to obtain third configuration data; and configures the field programmable gate array based on the third configuration data; The second configuration data comes from an external memory, or is sent to the first logic processing unit by an external device. Then, when the first logic processing unit detects that the field editable gate array enters a working state, the second configuration data is sent to the field editable gate array. 8. The field programmable gate array data processing device according to claim 7, characterized in that: The data processing device further includes a second logic processing unit connected to the first logic processing unit and configured to send second configuration data to the first logic processing unit. 9. The field programmable gate array data processing device according to claim 8, characterized in that: The data processing device further comprises a second memory connected to the first logic processing unit; The first logic processing unit is further configured to store the fourth configuration data in the second memory when acquiring the fourth configuration data sent by the second logic processing unit; or, The first logic processing unit is further configured to, when receiving a load command sent by the second logic processing unit, obtain target configuration data corresponding to the load command from the second memory, and load the target configuration data into the field programmable gate array. 10. A readable storage medium, characterized in that the readable storage medium is used to store program data, and when the program data is executed by a processor, it is used to implement the method according to any one of claims 1 to 6.