CN111813176A - Self-starting bias voltage generation circuit and electronics - Google Patents

Abstract

The present application relates to a self-starting bias voltage generating circuit and electronic equipment, the self-starting bias voltage generating circuit includes a reference current source, a field effect transistor M1, a first current mirror, a second current mirror, a field effect transistor M2 and FET M3. The gate of the field effect transistor M1 is connected to the reference current source, and the reference current source is used for providing current to the field effect transistor M1 and making the field effect transistor M1 conduct. The first current mirror is used to generate a first bias voltage and a second bias voltage. The second current mirror is used to generate a third bias voltage and a fourth bias voltage. The self-starting bias voltage generating circuit provided by the embodiment of the present application can reduce the power consumption of the self-starting biasing voltage generating circuit.

Description

Self-starting bias voltage generation circuit and electronics

technical field

The present application relates to the technical field of electronic equipment, and in particular, to a self-starting bias voltage generating circuit and electronic equipment.

Background technique

With the continuous development of the integrated circuit industry, the demand for low-power applications of chips is gradually increasing. In order to meet the requirements of low power consumption, the power supply voltage is further reduced. At the same time, the advancement of technology makes the conductive channel of the FET shorter and shorter, however, the short channel will cause the output impedance of the FET to decrease, making it more difficult to obtain a reasonable op amp gain using the FET. In order to ensure the working performance of the chip, a cascode structure is used to provide a larger output impedance. The bias voltage generating circuit is a necessary pre-circuit when the circuits of various cascode structures in the chip work.

In the conventional technology, the power consumption of the front-end power supply is reduced by increasing the branches of the bias voltage generating circuit. However, this increases the power consumption of the bias voltage generating circuit.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a self-starting bias voltage generating circuit and an electronic device for the above technical problems.

In one aspect, an embodiment of the present application provides a self-starting bias voltage generating circuit, including:

reference current source;

a field effect transistor M1, the gate of the field effect transistor M1 is connected to the reference current source, and the reference current source is used to provide current to the field effect transistor M1 and make the field effect transistor M1 conduct;

a first current mirror, the first end of the first current mirror is connected to the reference current source, the second end of the first current mirror is connected to the source of the field effect transistor M1, the first current mirror The third end of the mirror is grounded;

a second current mirror, the first end of the second current mirror is connected to a power supply, and the second end of the second current mirror is connected to the fourth end of the first current mirror;

A field effect transistor M2, the gate of the field effect transistor M2 is connected to the fifth end of the first current mirror, the source of the field effect transistor M2 is grounded, and the drain of the field effect transistor M2 is connected to the The third end of the second current mirror is connected, and the gate and drain of the field effect transistor M2 are connected;

Field effect transistor M3, the gate of the field effect transistor M3 is connected to the fourth end of the second current mirror, the source of the field effect transistor M3 is connected to the power supply, and the drain of the field effect transistor M3 is connected to the fourth end of the second current mirror. The sixth end of the first current mirror is connected, and the gate and drain of the field effect transistor M3 are connected;

The current flowing through the field effect transistor M1 to the field effect transistor M2 makes the field effect transistor M2 turn on, and the field effect transistor M2 determines the voltage of the first current mirror, so that the first current mirror The first bias voltage and the second bias voltage are generated, the field effect transistor M3 is turned on, and the voltage of the second current mirror is determined, so that the second current mirror generates the third bias voltage and the fourth bias voltage. set voltage.

In one embodiment, the first current mirror includes:

a first branch circuit, the first end of the first branch circuit is connected to the reference current source, the second end of the first branch circuit is connected to the source of the field effect transistor M1, the first branch The third end of the circuit is connected to the gate of the field effect transistor M2, the fourth end of the first branch circuit is connected to the second end of the second current mirror, and the fifth end of the first branch circuit connected with the drain of the field effect transistor M3;

a second branch circuit, the first end of the second branch circuit is connected to the sixth end of the first branch, the second end of the second branch circuit is connected to the seventh end of the first branch circuit, The third end of the second branch circuit is connected to the eighth end of the first branch circuit, and the fourth end of the second branch circuit is grounded.

In one embodiment, the first branch circuit includes:

A field effect transistor M4, the drain of the field effect transistor M4 is connected to the reference current source, the gate of the field effect transistor M4 is connected to the source of the field effect transistor M1, and the the gate voltage is the second bias voltage;

Field effect transistor M5, the gate of the field effect transistor M5 is connected to the gate of the field effect transistor M4, and is connected to the gate of the field effect transistor M2, and the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M5. connecting the second end of the second current mirror;

A field effect transistor M8, the gate of the field effect transistor M8 is connected to the gate of the field effect transistor M5, and the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M3.

In one of the embodiments, the second branch circuit includes:

A field effect transistor M6, the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M6 is connected to the source of the field effect transistor M4, and the field effect transistor M6 is connected to the source of the field effect transistor M4. The source of the effect transistor M6 is grounded, and the gate voltage of the field effect transistor M6 is the first bias voltage;

A field effect transistor M7, the gate of the field effect transistor M7 is connected to the gate of the field effect transistor M6, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M5, the field effect transistor M5 The source of effect transistor M7 is grounded;

Field effect transistor M9, the gate of the field effect transistor M9 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M9 is connected to the source of the field effect transistor M8, the field effect transistor M8 The source of the effect transistor M9 is grounded.

In one embodiment, the second current mirror includes:

A field effect transistor M10, the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M3, the drain of the field effect transistor M10 is connected to the drain of the field effect transistor M5, and the field effect transistor M10 is connected to the drain of the field effect transistor M5. The gate voltage of the effect transistor M10 is the third bias voltage;

A field effect transistor M11, the gate of the field effect transistor M11 is connected to the drain of the field effect transistor M10, the drain of the field effect transistor M11 is connected to the source of the field effect transistor M10, the field effect transistor M11 The source of the effect transistor M11 is connected to the power supply, and the gate voltage of the field effect transistor M11 is the fourth bias voltage;

a field effect transistor M12, the gate of the field effect transistor M12 is connected to the gate of the field effect transistor M10, and the drain of the field effect transistor M12 is connected to the drain of the field effect transistor M2;

A field effect transistor M13, the gate of the field effect transistor M13 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M13 is connected to the source of the field effect transistor M12, and the field effect transistor M13 is connected to the source of the field effect transistor M12. The source of the effect transistor M13 is connected to the power supply.

In one embodiment, the fourth bias voltage is larger than the third bias voltage, the third bias voltage is larger than the second bias voltage, and the second bias voltage is larger than the first bias voltage a bias voltage.

In one embodiment, the reference current source includes a bias power circuit, and the bias power circuit is configured to turn on the field effect transistor M1 and provide power to the field effect transistor M1.

In one embodiment, the drain-source voltage of the field effect transistor M2 is greater than or equal to the overdrive voltage, and the drain-source voltage of the field effect transistor M3 is greater than or equal to the overdrive voltage.

In one embodiment, the ratio of the width to the length of the FET M11 and the ratio of the width to the length of the FET M13 is 1:1, and the width to the length of the FET M10 is 1:1. The ratio of the ratio to the ratio of the width to the length of the field effect transistor M12 is 1:1.

On the other hand, an embodiment of the present application provides an electronic device including the above-mentioned self-starting bias voltage generating circuit.

Embodiments of the present application provide a self-starting bias voltage generating circuit and an electronic device. The self-starting bias voltage generating circuit includes a reference current source, a field effect transistor M1, a first current mirror, a second current mirror, and a field effect transistor. M2 and FET M3. The gate of the field effect transistor M1 is connected to the reference current source, and the reference current source is used for providing current to the field effect transistor M1 and making the field effect transistor M1 conduct. The first current mirror is used to generate a first bias voltage and a second bias voltage. The second current mirror is used to generate a third bias voltage and a fourth bias voltage. The self-starting bias voltage generating circuit provided in the embodiment of the present application can realize the self-starting of the self-starting bias voltage generating circuit by setting the field effect transistor M1 in the case of a reference current source input, which can reduce the The number of branches of the self-starting bias voltage generating circuit simplifies the circuit structure, so that the power consumption of the self-starting biasing voltage generating circuit can be reduced.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the traditional technology, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or the traditional technology. Obviously, the drawings in the following description are only the For some embodiments of the application, for those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

1 is a schematic structural diagram of a bias voltage generating circuit in the conventional technology;

2 is a schematic structural diagram of a bias voltage generating circuit in the conventional technology;

FIG. 3 is a schematic structural diagram of a self-starting bias voltage generating circuit provided by an embodiment of the present application;

4 is a schematic diagram of a change in the operating point of a self-starting bias voltage generating circuit provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a self-starting bias voltage generating circuit according to an embodiment of the present application.

Description of reference numbers:

10. Self-starting bias voltage generating circuit;

100. Reference current source;

200, the first current mirror;

210. A first branch circuit;

220. The second branch circuit;

300. A second current mirror.

Detailed ways

In order to make the above objects, features and advantages of the present application more clearly understood, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections). In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship indicated by "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description , rather than indicating or implying that the referred device or element must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as a limitation on the present application.

In this application, unless otherwise expressly stated and defined, a first feature "on" or "under" a second feature may be in direct contact with the first and second features, or the first and second features indirectly through an intermediary touch. Also, the first feature being "above", "over" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is level higher than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

The technical solution of the present application and how the technical solution of the present application solves the technical problem will be described in detail below with specific embodiments. The following specific embodiments may be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

The first bias voltage generation circuit in the traditional technology is shown in Figure 1. A current source is input, and five branches are required to generate four bias voltages. The five branch circuits are the branch where M1 is located, the branch where M2, M4 and M5 are located, the branch where M3 and M6 are located, the branch where M7, M9 and M11 are located, and the branch where M8, M10, M12 and M3 are located . In Figure 1, the NMOS transistors M1, M2 and M3 form a current mirror, and the input current is proportionally copied to the branch where the NMOS transistors M2 and M3 are located, and the current passing through the NMOS transistor M2 and the current passing through the PMOS transistors M4 and M5 The currents are equal, and the current through the NMOS transistor M2 and the current through the PMOS transistors M4 and M5 are equal. The function of the PMOS transistor M6 is to bias the gate voltage of the PMOS transistor M5, so that both M4 and M5 work in the saturation region to ensure that the replication ratio of the current mirror is correct. The working principle of NMOS transistors M11, M12, and M13 is the same as that of PMOS transistors M6, M5, and M4. After ensuring that all MOS transistors work in the saturation region, four bias voltages VP, VPC, VNC, and VN can be obtained. The bias voltage generation circuit uses five branches, because under normal operation, the circuit on each branch is a multiple of the input circuit. Too many branches will cause the power consumption of the entire bias voltage generation circuit to be biased. big.

The second type of bias voltage generating circuit in the conventional technology is shown in Fig. 2. There are two input current sources, and a total of four branches are required to obtain four bias voltages. In Figure 2, the NMOS transistors M2 and M3 form a cascode current mirror, which copies the input current IB2 to the branch where the NMOS transistors M4 and M5 are located, and the input IB1 current is used to determine the gate of the NMOS transistor M1. pressure, so that both M2 and M3 work in the saturation region to ensure that the replication ratio of the current mirror is correct. The working principles of the PMOS transistors M8, M9, and M10 are the same as those of the NMOS transistors M2, M1, and M3. After ensuring that all MOS transistors work in the saturation region, four bias voltages VP, VPC, VNC, and VN can be obtained. Compared with the first bias voltage generation circuit in the conventional technology, the bias voltage generation circuit reduces one branch, thereby reducing the power consumption of the bias voltage generation circuit. However, the bias voltage generating circuit requires two input current sources, and the power consumption of the bias voltage generating circuit is transferred to the front-end current source circuit.

Referring to FIG. 3, an embodiment of the present application provides a self-starting bias voltage generating circuit 10, which can be applied to various circuits that require bias voltages. One current source is required, and a total of four branches are required to obtain four bias voltages. Voltage. The self-starting bias voltage generating circuit 10 includes a reference current source 100 , a field effect transistor M1 , a first current mirror 200 , a second current mirror 300 , a field effect transistor M2 and a field effect transistor M3 .

The gate of the field effect transistor M1 is connected to the reference current source 100 , and the reference current source 100 is used for providing current to the field effect transistor M1 and making the field effect transistor M1 turn on. The reference current source 100 refers to a current source with high precision and low temperature coefficient used in an integrated circuit as a current reference for other circuits. In this embodiment, the reference current source 100 is used as the current source of the self-starting bias voltage generating circuit 10 . The reference current source 100 may be a MOS tube-type reference current source, or a diode-type reference current source, etc. This embodiment does not limit the type and specific structure of the reference current source 100 as long as its function can be realized. That's it. The gate of the field effect transistor M1 is connected to the reference current source 100, and the reference current source 100 provides a voltage to the gate of the field effect transistor M1, so that the field effect transistor M1 is turned on, so that the The current provided by the reference current source 100 may flow to the field effect transistor M2 through the field effect transistor M1. Field effect transistors are common electronic components and belong to voltage-controlled semiconductor devices. Field effect transistors can be divided into N-channel and P-channel according to the channel material, and can be divided into depletion type and enhancement type according to the conduction mode. In a specific embodiment, the field effect transistor M1 is an N-communication field effect transistor. The FET has the advantages of high input resistance, low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon and wide safety area.

The first end of the first current mirror 200 is connected to the reference current source 100, the second end of the first current mirror 200 is connected to the source of the field effect transistor M1, and the first current mirror 200 The third terminal is grounded. The first current mirror 200 is used for generating the first bias voltage and the second bias voltage. The first current mirror 200 is a special case of a constant current circuit, and the controlled current of the first current mirror 200 is equal to the input reference current, that is, the input-output current transfer ratio is equal to 1. The feature of the first current mirror 200 is that it can replicate the input current in a certain proportion. The first current mirror 200 can be divided into a static current mirror and a dynamic current mirror, wherein the static current mirror includes a bipolar basic current mirror, a MOS transistor basic current mirror, a Widlar current mirror, a cascaded current mirror, and the like. This embodiment does not impose any limitation on the type and structure of the first current mirror 200, as long as its function can be realized.

The first end of the second current mirror 300 is connected to a power source, and the second end of the second current mirror 300 is connected to the fourth end of the first current mirror 200 . The second current mirror 300 is used to generate a third bias voltage and a fourth bias voltage. For the specific description of the second current mirror 300, reference may be made to the above description of the first current mirror 200, which is not repeated here. In this embodiment, the fourth end of the first current mirror 200 is connected to the second end of the second current mirror 300 , so that the current of the first current mirror 200 is connected to the second current mirror 300 The current in the self-starting bias voltage generating circuit 10 presents a certain ratio, so that the current of the entire self-starting bias voltage generating circuit 10 is stabilized, and the reliability and practicability of the self-starting biasing voltage generating circuit 10 are improved.

The gate of the field effect transistor M2 is connected to the fifth end of the first current mirror 200, the source of the field effect transistor M2 is grounded, and the drain of the field effect transistor M2 is connected to the second current mirror The third terminal of 300 is connected, and the gate and drain of the field effect transistor M2 are connected. The gate and drain of the field effect transistor M2 are connected, which is a working state of the field effect transistor M2. The gate and drain of the field effect transistor M2 are used as one end, and the source is used as the other end. As a diode, the voltage of the first current mirror 200 can be determined, thereby ensuring the correctness of the mirror relationship of the first current mirror 200 . For the specific description of the field effect transistor M2, reference may be made to the description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M2 is an N-channel field effect transistor.

The gate of the field effect transistor M3 is connected to the fourth end of the second current mirror 300, the source of the field effect transistor M3 is connected to a power supply, and the drain of the field effect transistor M3 is connected to the first current The sixth end of the mirror 200 is connected, and the gate and the drain of the field effect transistor M3 are connected. The gate and drain of the field effect transistor M3 serve as one end, and the source serves as the other end, which can be equivalent to a diode, and can determine the voltage of the second current mirror 300 . For the specific description of the field effect transistor M3, reference may be made to the description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M3 is a P-channel field effect transistor.

The working principle of the self-starting bias voltage generating circuit 10 is as follows:

The self-starting bias voltage generating circuit 10 has two operating points. As shown in FIG. 4 , the self-starting bias voltage generating circuit 10 operates at the B operating point in the initial steady state. When the reference current source 100 starts to supply current, the field effect transistor M1 is in a conducting state, and the self-starting bias voltage generating circuit begins to gradually shift to the A operating point. In FIG. 4, _IB is the current provided by the reference current source 100, the abscissa is the gate-source voltage of the FET M2, and the ordinate is the drain current of the FET M2. The charge of the current transmitted by the FET M1 will be accumulated on the gate of the FET M2, so that the FET M2 can determine the voltage of the first current mirror 200, so that the first current mirror 200 can be determined. The current mirror 200 generates the first bias voltage and the second bias voltage. When the first current mirror 200 is working normally, the field effect transistor M3 is turned on, so that the field effect transistor M3 can determine the voltage of the second current mirror 300 , thereby enabling the second current The mirror 300 generates the third bias voltage and the fourth bias voltage. When the self-starting bias voltage generating circuit 10 starts to work normally, the field effect transistor M1 will be turned off, and additional power consumption will not be increased.

The self-starting bias voltage generating circuit 10 provided in this embodiment includes a reference current source 100 , a field effect transistor M1 , a first current mirror 200 , a second current mirror 300 , a field effect transistor M2 and a field effect transistor M3 . The gate of the field effect transistor M1 is connected to the reference current source 100 , and the reference current source 100 is used for providing current to the field effect transistor M1 and making the field effect transistor M1 turn on. The first current mirror 200 is used to generate a first bias voltage and a second bias voltage. The second current mirror 300 is used to generate a third bias voltage and a fourth bias voltage. The self-starting bias voltage generating circuit 10 provided in this embodiment can realize the self-starting of the self-starting bias voltage generating circuit by setting the field effect transistor M1 in the case of a reference current source inputting the power supply, which can reduce the The number of branches of the self-starting bias voltage generating circuit 10 simplifies the circuit structure, so that the power consumption of the self-starting biasing voltage generating circuit 10 can be reduced, and at the same time, the use of the self-starting biasing voltage generating circuit 10 can be reduced. power consumption of the chip. In addition, after the self-starting bias voltage generating circuit 10 operates stably, the field effect transistor M1 will be turned off, and additional power consumption will not be increased.

Referring to FIG. 5 , in one embodiment, the first current mirror 200 includes a first branch circuit 210 and a second branch circuit 220 .

The first end of the first branch circuit 210 is connected to the reference current source 100, the second end of the first branch circuit 210 is connected to the source of the field effect transistor M1, and the first branch circuit 210 The third end of the FET is connected to the gate of the field effect transistor M2, the fourth end of the first branch circuit 210 is connected to the second end of the second current mirror 300, and the first branch circuit 210 is connected to the second end of the second current mirror 300. The fifth terminal is connected to the drain of the field effect transistor M3. The first end of the first branch circuit 210 is connected to the reference current source 100 as the first end of the first current mirror 200 . The second end of the first branch circuit 210 is connected to the source of the field effect transistor M1 as the second end of the first current mirror 200 . The third end of the first branch circuit 210 is connected to the gate of the field effect transistor M2 as the fifth end of the first current mirror 200 . The fourth end of the first branch circuit 210 is connected to the second end of the second current mirror 300 as the fourth end of the first current mirror 200 . The fifth terminal of the first branch circuit 210 is connected to the drain of the field effect transistor M3 as the sixth terminal of the first current mirror 200 . The FET M2 can determine the voltage of the first branch circuit 210 so that the first branch circuit 210 generates the second bias voltage.

The first end of the second branch circuit 220 is connected to the sixth end of the first branch circuit 210 , the second end of the second branch circuit 220 is connected to the seventh end of the first branch circuit 210 , The third end of the second branch circuit 220 is connected to the eighth end of the first branch circuit 210 , and the fourth end of the second branch circuit 220 is grounded. The fourth terminal of the second branch circuit 220 is grounded as the third terminal of the first current mirror 200 . The second branch circuit 220 can generate the first bias voltage.

Please continue to refer to FIG. 4 , in one embodiment, the first branch circuit 210 includes a field effect transistor M4 , a field effect transistor M5 and a field effect transistor M8 .

The drain of the field effect transistor M4 is connected to the reference current source 100, the gate of the field effect transistor M4 is connected to the source of the field effect transistor M1, and the gate voltage of the field effect transistor M4 is the first bias voltage. The drain of the field effect transistor M4 is connected to the reference current source 100 as the first end of the first branch circuit 210 . The voltage of the gate of the field effect transistor M4 is the second bias voltage generated by the first branch circuit 210 . For the specific description of the field effect transistor M4, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M4 is an N-channel field effect transistor.

The gate of the field effect transistor M5 is connected to the gate of the field effect transistor M4, and is connected to the gate of the field effect transistor M2, and the drain of the field effect transistor M5 is connected to the second current mirror The second end of 300 is connected. The gate of the field effect transistor M8 is connected to the gate of the field effect transistor M5, and the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M3. The gate of the field effect transistor M4, the gate of the field effect transistor M5 and the gate of the field effect transistor M8 are all connected to the gate of the field effect transistor M2, and the field effect transistor M2 can be determined The gate voltage of the field effect transistor M4, the field effect transistor M5 and the field effect transistor M8. The drain of the field effect transistor M5 is connected to the second end of the second current mirror 300 as the fourth end of the first branch circuit 210 . The drain of the field effect transistor M8 is connected to the drain of the field effect transistor M3 as the fifth end of the first branch circuit 210 . For the description of the field effect transistor M5 and the field effect transistor M8, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M5 and the field effect transistor M8 are both N-channel field effect transistors.

Please continue to refer to FIG. 4 , in one embodiment, the second branch circuit 220 includes a field effect transistor M6 , a field effect transistor M7 and a field effect transistor M9 .

The gate of the field effect transistor M6 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M6 is connected to the source of the field effect transistor M4, and the source of the field effect transistor M6 The electrode is grounded, and the gate voltage of the field effect transistor M6 is the second bias voltage. The gate of the field effect transistor M6 is connected to the drain of the field effect transistor M4, and the drain of the field effect transistor M4 is connected to the reference current source 100, that is, the gate of the field effect transistor M6 Connected to the reference current source 100, the field effect transistor M6 is turned on, and will generate the first bias voltage after normal operation. For the specific description of the field effect transistor M6, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M6 is an N-channel field effect transistor.

The gate of the field effect transistor M7 is connected to the gate of the field effect transistor M6, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M5, and the source of the field effect transistor M7 pole ground. The gate of the field effect transistor M9 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M9 is connected to the source of the field effect transistor M8, and the source of the field effect transistor M9 pole ground. The gate of the field effect transistor M6, the gate of the field effect transistor M7 and the gate of the field effect transistor M9 are all connected together. The source of the field effect transistor M6 , the source of the field effect transistor M7 and the source of the field effect transistor M9 are grounded together as the fourth end of the second branch circuit 220 . For the description of the field effect transistor M7 and the field effect transistor M9, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M7 and the field effect transistor M9 are both N-channel field effect transistors.

For the first current mirror 200, the field effect transistor M4 and the field effect transistor M6 constitute a cascode current mirror, which can reduce the drain-source voltage of the field effect transistor M4, thereby making the field effect The drain-source voltage of the transistor M4 and the field-effect transistor M6 is matched with the drain-source voltage of the field-effect transistor M5 and the field-effect transistor M7, as well as the drain-source voltage of the field-effect transistor M8 and the field-effect transistor M9. The drain-to-source voltages are matched, this connection can make the current replication more accurate, which can improve the power supply rejection ratio.

Please continue to refer to FIG. 3 , in one embodiment, the second current mirror 300 includes a field effect transistor M10 , a field effect transistor M11 , a field effect transistor M12 and a field effect transistor M13 .

The gate of the field effect transistor M10 is connected to the gate of the field effect transistor M3, the drain of the field effect transistor M10 is connected to the drain of the field effect transistor M5, and the gate of the field effect transistor M10 is connected The pole voltage is the third bias voltage. The gate of the field effect transistor M12 is connected to the gate of the field effect transistor M10, and the drain of the field effect transistor M12 is connected to the drain of the field effect transistor M2. The gate of the field effect transistor M10 is connected to the fourth end of the first branch circuit 210 as the second end of the second current mirror 300 . When the first current mirror 200 is working normally, the drain voltage of the field effect transistor M8 decreases, which reduces the gate voltage of the field effect transistor M3, so that the field effect transistor M3 is turned on . The gate of the field effect transistor M3 is connected to the gate of the field effect transistor M10, and the field effect transistor M3 can determine the gate voltage of the field effect transistor M10, so that the field effect transistor M10 is turned on, start working. The gate of the field effect transistor M12 is connected to the gate of the field effect transistor M10. When the field effect transistor M10 is turned on, the field effect transistor M12 is also turned on and starts to work. After the field effect transistor M10 is stable, the third bias voltage will be generated. For the specific description of the field effect transistor M10 and the field effect transistor M12, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M10 and the field effect transistor M12 are both P-channel field effect transistors.

The gate of the field effect transistor M11 is connected to the drain of the field effect transistor M10, the drain of the field effect transistor M11 is connected to the source of the field effect transistor M10, and the source of the field effect transistor M11 The pole is connected to the power supply, and the gate voltage of the field effect transistor M11 is the fourth bias voltage. The gate of the field effect transistor M13 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M13 is connected to the source of the field effect transistor M12, and the source of the field effect transistor M13 connected to the power supply. The source electrode of the field effect transistor M11 and the source electrode of the field effect transistor M13 are connected to a power supply together as the first end of the second current mirror 300 . The gate of the field effect transistor M11 is connected to the drain of the field effect transistor M10, and the drain of the field effect transistor M10 is connected to the drain of the field effect transistor M5, that is, the field effect transistor The gate of M11 is connected to the drain of the field effect transistor M5. After the first current mirror 200 works stably, the drain voltage of the field effect transistor M5 becomes smaller, which makes the gate voltage of the field effect transistor M11 smaller, so that the field effect transistor M1 is turned on ,start working. The gate of the field effect transistor M13 is connected to the gate of the field effect transistor M11, and the field effect transistor M13 is also turned on and starts to work. After the field effect transistor M1 is stable, the fourth bias voltage will be generated. For the specific description of the field effect transistor M11 and the field effect transistor M13, reference may be made to the above description of the field effect transistor M1, which will not be repeated here. In a specific embodiment, the field effect transistor M11 and the field effect transistor M13 are both P-channel field effect transistors.

For the second current mirror 300, the field effect transistor M11 and the field effect transistor M10 constitute a cascode current mirror. For the cascode current mirror formed by the field effect transistor M11 and the field effect transistor M10, reference may be made to the above description of the cascode current mirror formed by the field effect transistor M4 and the field effect transistor M6, It is not repeated here.

In one embodiment, the fourth bias voltage is greater than the third bias voltage, the third bias voltage is greater than the second bias voltage, and the second bias voltage is greater than the first bias voltage bias voltage.

When the self-starting bias voltage generating circuit is working normally, except the field effect transistor M1, other field effect transistors in the circuit all work in the saturation region, that is, the drain-source voltage of the field effect transistor is greater than or equal to the overdrive voltage . For the field effect transistor M4, the second bias voltage is equal to the sum of the first bias voltage and the threshold voltage value of the field effect transistor M4, so the second bias voltage is greater than the first bias Voltage. For the field effect transistor M10, the third bias voltage and the threshold voltage of the field effect transistor M10 are equal to the fourth bias voltage, then the fourth bias voltage is greater than the third bias voltage . Since the current flowing through the field effect transistors on each branch in the circuit is the same, the gate-source voltages of the field effect transistors are almost the same, and the third bias voltage must be greater than the second bias voltage.

In one embodiment, the reference current source 100 includes a bias power supply circuit, and the bias power supply circuit is configured to turn on the field effect transistor M1 and provide power to the field effect transistor M1. The bias power supply circuit may be a circuit including a plurality of diodes, or a circuit including a plurality of MOS transistors. In a specific embodiment, the drain of the P-channel MOS transistor in the bias power circuit is connected to the field effect transistor M1, and the field effect transistor M1 is an N-channel field effect transistor. When the bias power supply circuit is working, the MOS transistor of the P channel is turned on, and the drain of the MOS transistor provides a voltage to the field effect transistor M1, so that the field effect transistor M1 is turned on, so that the current can be It flows into the self-starting bias voltage generating circuit 10 through the field effect transistor M1. In this embodiment, the bias power supply circuit can provide the required current to the self-starting bias voltage generating circuit 10, and the structure of the bias power supply circuit is simple.

In one embodiment, the drain-source voltage of the field effect transistor M2 is greater than or equal to the overdrive voltage, and the drain-source voltage of the field effect transistor M3 is greater than or equal to the overdrive voltage. The overdrive voltage of the FET refers to the difference between the gate-source voltage and the threshold voltage of the FET. The drain-source voltage of the FET is the voltage between the drain and the source of the FET, the gate-source voltage of the FET is the voltage between the gate and the source of the FET, and the Threshold voltage refers to the voltage at which a FET forms a channel. When the drain-source voltage of the FET is greater than or equal to the overdrive voltage, the FET can work in the saturation region. In this embodiment, in addition to the field effect transistor M1, other field effect transistors, that is, the field effect transistor M2, the field effect transistor M3, the field effect transistor M4, the field effect transistor M5, The field effect transistor M6, the field effect transistor M7, the field effect transistor M8, the field effect transistor M9, the field effect transistor M10, the field effect transistor M11, the field effect transistor M12 and all The drain-source voltage of the field effect transistor M13 is greater than or equal to the overdrive voltage, which can ensure that all field effect transistors except the field effect transistor M1 work in the saturation region, thereby improving the self-starting bias voltage generation circuit. 10 for reliability and practicality, and the accuracy of the bias voltage generated.

In one embodiment, the ratio of the width to the length of the field effect transistor M11 and the ratio of the width to the length of the field effect transistor M13 is 1:1, and the ratio of the width to the length of the field effect transistor M10 The ratio of the width to the length of the field effect transistor M12 is 1:1.

其中，IB为通过所述场效应管M6的电流大小，μ_n是场效应管的表面迁移率，C_ox为单位面积场效应管的电容，W为场效应管的导电沟道宽度，L为场效应管的导电沟道长度。Assuming that the current replication ratio of the first current mirror 200 and the second current mirror 300 is 1:1, the current values in each branch in the self-starting bias voltage generating circuit 10 are equal. Assuming that the ratio of width to length of the conductive channel of the field effect transistor M6 is defined as W/L, the overdrive voltage of the field effect transistor M6 and the field effect transistor M9 are equal, which can be expressed as:

Among them, IB is the current through the FET M6, μ _n is the surface mobility of the FET, C _ox is the capacitance of the FET per unit area, W is the conductive channel width of the FET, and L is the The conduction channel length of the FET.

According to the fact that all field effect transistors in the circuit except the field effect transistor M1 work in the saturation region, and the drain voltage of the field effect transistor M4 should be the smallest, the conduction channel of the field effect transistor M4 can be obtained. The ratio of width to length is W/(L*n ² ), and the ratio of width to length of the conductive channel of the field effect transistor M2 is W/(L*(n+1) ² ). It can be obtained that the overdrive voltage of the field effect transistor M4 and the field effect transistor M8 is n*V _M6 , the overdrive voltage of the field effect transistor M2 is (n+1)*V _M6 , the field effect transistor The gate voltage of M6 is (n+1)V _M6 +V _tn . The drain-source voltages of the FET M6 and the FET M9 can be obtained as V _DSM6 =V _DSM9 =(n+1)V _M6 +V _tn -(nV _M6 +V _tn )=V _M6 . From this, it can be seen that the overdrive voltage and the drain-source voltage of the FET M6 are equal, and are just at the edge of the saturation region. In order to ensure that the field effect transistor M4 and the field effect transistor M8 are in the saturation region, it needs to satisfy V _{DSM4 ≥V M4} =n*V _M6 . The gate of the field effect transistor M6 is connected to the drain of the field effect transistor M4, then V _DSN4 =V _GM6 -V _DSM6 =(V _M6 +V _tn )-V _M6 =V _tn . Therefore, to ensure that the field effect transistor M4 is in the saturation region, it is necessary to ensure that V _th ≥ nV _M6 of the field effect transistor M4 . In a specific embodiment, the overdrive voltage of the field effect transistor M2 is between 0.2V-0.25V, and the value of n is determined by the range of the required bias voltage, generally in the range of 1-2. It can be concluded that the ratio of the width to the length of the FET M11 and the ratio of the width to the length of the FET M10 is n ² : 1, and the ratio of the width to the length of the FET M13 is n 2 : 1. The ratio of the width to the length of the field effect transistor M12 is n ² :1. The ratio of the width to the length of the field effect transistor M4 and the ratio of the width to the length of the field effect transistor M6 is n ² : 1, the ratio of the width to the length of the field effect transistor M5 and the field effect The ratio of the width to the length of the tube M7 is n ² :1, the ratio of the width to the length of the field effect transistor M8 and the ratio of the width to the length of the field effect transistor M9 is n ² :1. The ratio of the width to the length of the field effect transistor M10 and the ratio of the width to the length of the field effect transistor M12 is 1:1, the ratio of the width to the length of the field effect transistor M11 and the field effect transistor The ratio of width to length of M13 is 1:1. The ratio of the width to length of the field effect transistor M4, the width to length ratio of the field effect transistor M4, and the ratio of the width to length of the field effect transistor M8 are 1:1:1. The ratio of the width to the length of the effect transistor M6, the ratio of the width to the length of the field effect transistor M7, and the ratio of the width to the length of the field effect transistor M9 is 1:1:1. The ratio of the width to length of the field effect transistor M3 to the width to length of the field effect transistor M8 is n ² :(n+1) ² , and the ratio of the width to the length of the field effect transistor M2 The ratio of the width to the length of the field effect transistor M4 is n ² :(n+1) ² .

An embodiment of the present application provides an electronic device, including the self-starting bias voltage generating circuit described in the above embodiment. The self-starting bias voltage generating circuit can be applied to various bias voltage generating chips, for example, chips such as MAX1748 and AIC1880, which can provide bias voltages for thin film transistor liquid crystal displays. The electronic device may be a device that uses various bias voltages to generate chips, such as a mobile phone with a thin film transistor liquid crystal display, MP3, MP4 handheld computer and other devices. Since the electronic device includes the self-starting bias voltage generating circuit, the electronic device includes all the specific structures and beneficial effects of the self-starting bias voltage generating circuit, which will not be repeated here.

The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent of the present application. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. A self-starting bias voltage generating circuit is characterized in that, comprising: reference current source; a field effect transistor M1, the gate of the field effect transistor M1 is connected to the reference current source, and the reference current source is used to provide current to the field effect transistor M1 and make the field effect transistor M1 conduct; a first current mirror, the first end of the first current mirror is connected to the reference current source, the second end of the first current mirror is connected to the source of the field effect transistor M1, the first current mirror The third end of the mirror is grounded; a second current mirror, the first end of the second current mirror is connected to a power supply, and the second end of the second current mirror is connected to the fourth end of the first current mirror; A field effect transistor M2, the gate of the field effect transistor M2 is connected to the fifth end of the first current mirror, the source of the field effect transistor M2 is grounded, and the drain of the field effect transistor M2 is connected to the The third end of the second current mirror is connected, and the gate and drain of the field effect transistor M2 are connected; Field effect transistor M3, the gate of the field effect transistor M3 is connected to the fourth end of the second current mirror, the source of the field effect transistor M3 is connected to the power supply, and the drain of the field effect transistor M3 is connected to the fourth end of the second current mirror. The sixth end of the first current mirror is connected, and the gate and drain of the field effect transistor M3 are connected; The current flowing through the field effect transistor M1 to the field effect transistor M2 makes the field effect transistor M2 turn on, and the field effect transistor M2 determines the voltage of the first current mirror, so that the first current mirror The first bias voltage and the second bias voltage are generated, the field effect transistor M3 is turned on, and the voltage of the second current mirror is determined, so that the second current mirror generates the third bias voltage and the fourth bias voltage. set voltage. 2. The self-starting bias voltage generating circuit according to claim 1, wherein the first current mirror comprises: a first branch circuit, the first end of the first branch circuit is connected to the reference current source, the second end of the first branch circuit is connected to the source of the field effect transistor M1, the first branch The third end of the circuit is connected to the gate of the field effect transistor M2, the fourth end of the first branch circuit is connected to the second end of the second current mirror, and the fifth end of the first branch circuit connected with the drain of the field effect transistor M3; a second branch circuit, the first end of the second branch circuit is connected to the sixth end of the first branch, the second end of the second branch circuit is connected to the seventh end of the first branch circuit, The third end of the second branch circuit is connected to the eighth end of the first branch circuit, and the fourth end of the second branch circuit is grounded. 3. The self-starting bias voltage generating circuit according to claim 2, wherein the first branch circuit comprises: A field effect transistor M4, the drain of the field effect transistor M4 is connected to the reference current source, the gate of the field effect transistor M4 is connected to the source of the field effect transistor M1, and the the gate voltage is the second bias voltage; Field effect transistor M5, the gate of the field effect transistor M5 is connected to the gate of the field effect transistor M4, and is connected to the gate of the field effect transistor M2, and the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M5. connecting the second end of the second current mirror; A field effect transistor M8, the gate of the field effect transistor M8 is connected to the gate of the field effect transistor M5, and the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M3. 4. The self-starting bias voltage generating circuit according to claim 3, wherein the second branch circuit comprises: A field effect transistor M6, the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M4, the drain of the field effect transistor M6 is connected to the source of the field effect transistor M4, and the field effect transistor M6 is connected to the source of the field effect transistor M4. The source of the effect transistor M6 is grounded, and the gate voltage of the field effect transistor M6 is the first bias voltage; A field effect transistor M7, the gate of the field effect transistor M7 is connected to the gate of the field effect transistor M6, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M5, the field effect transistor M5 The source of effect transistor M7 is grounded; Field effect transistor M9, the gate of the field effect transistor M9 is connected to the gate of the field effect transistor M7, the drain of the field effect transistor M9 is connected to the source of the field effect transistor M8, the field effect transistor M8 The source of the effect transistor M9 is grounded. 5. The self-starting bias voltage generating circuit according to claim 3, wherein the second current mirror comprises: A field effect transistor M10, the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M3, the drain of the field effect transistor M10 is connected to the drain of the field effect transistor M5, and the field effect transistor M10 is connected to the drain of the field effect transistor M5. The gate voltage of the effect transistor M10 is the third bias voltage; A field effect transistor M11, the gate of the field effect transistor M11 is connected to the drain of the field effect transistor M10, the drain of the field effect transistor M11 is connected to the source of the field effect transistor M10, the field effect transistor M11 The source of the effect transistor M11 is connected to the power supply, and the gate voltage of the field effect transistor M11 is the fourth bias voltage; a field effect transistor M12, the gate of the field effect transistor M12 is connected to the gate of the field effect transistor M10, and the drain of the field effect transistor M12 is connected to the drain of the field effect transistor M2; A field effect transistor M13, the gate of the field effect transistor M13 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M13 is connected to the source of the field effect transistor M12, and the field effect transistor M13 is connected to the source of the field effect transistor M12. The source of the effect transistor M13 is connected to the power supply. 6 . The self-starting bias voltage generating circuit according to claim 1 , wherein the fourth bias voltage is greater than the third bias voltage, and the third bias voltage is greater than the second bias voltage 6 . setting voltage, the second bias voltage is greater than the first bias voltage. 7 . The self-starting bias voltage generating circuit according to claim 1 , wherein the reference current source comprises a bias power supply circuit, and the bias power supply circuit is used to turn on the field effect transistor M1 , and Supply power to the field effect transistor M1. 8 . The self-starting bias voltage generating circuit according to claim 1 , wherein the drain-source voltage of the field effect transistor M2 is greater than or equal to the overdrive voltage, and the drain-source voltage of the field effect transistor M3 is greater than or equal to the overdrive voltage 8 . drive voltage. 9 . The self-starting bias voltage generating circuit according to claim 5 , wherein the ratio between the width and length of the field effect transistor M11 and the ratio between the width and length of the field effect transistor M13 is 1. 10 . : 1, and the ratio between the width and length of the field effect transistor M10 and the width and length of the field effect transistor M12 is 1:1. 10. An electronic device, comprising the self-starting bias voltage generating circuit according to any one of claims 1 to 9.

Images