CN111813175B - High voltage, high drive, high power supply rejection ratio LDO - Google Patents
High voltage, high drive, high power supply rejection ratio LDO Download PDFInfo
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- CN111813175B CN111813175B CN202010801443.6A CN202010801443A CN111813175B CN 111813175 B CN111813175 B CN 111813175B CN 202010801443 A CN202010801443 A CN 202010801443A CN 111813175 B CN111813175 B CN 111813175B
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- 239000003990 capacitor Substances 0.000 claims abstract description 25
- 230000015556 catabolic process Effects 0.000 claims abstract description 7
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- 230000007850 degeneration Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims 1
- 230000008569 process Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- HEZMWWAKWCSUCB-PHDIDXHHSA-N (3R,4R)-3,4-dihydroxycyclohexa-1,5-diene-1-carboxylic acid Chemical compound O[C@@H]1C=CC(C(O)=O)=C[C@H]1O HEZMWWAKWCSUCB-PHDIDXHHSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
一种高压大驱动高电源抑制比LDO，属于LDO技术领域。本发明针对现有技术中为提高电源抑制比对带片外电容LDO电路进行的改造，存在噪声大及电路稳定性差的问题。包括共源共栅阻性源退化电路和动态补偿电路，所述共源共栅阻性源退化电路采用NMOS差分对管输入，获得低压差固定一级输出电压；动态补偿电路对所述一级输出电压采用动态零点补偿以及动态偏置的方式，获得最终输出电压。本发明可使输出电压噪声大幅度降低，并保证工作点稳定。
A high-voltage, high-drive, high-power supply rejection ratio LDO belongs to the field of LDO technology. The present invention is aimed at the problems of high noise and poor circuit stability in the prior art for improving the power supply rejection ratio of the LDO circuit with off-chip capacitors. It includes a common-source and common-gate resistive source degradation circuit and a dynamic compensation circuit. The common-source and common-gate resistive source degradation circuit uses an NMOS differential pair tube input to obtain a low-voltage difference fixed primary output voltage; the dynamic compensation circuit uses dynamic zero point compensation and dynamic biasing to the primary output voltage to obtain the final output voltage. The present invention can significantly reduce the output voltage noise and ensure the stability of the operating point.
Description
Technical Field
The invention relates to a high-voltage large-drive high-power supply rejection ratio LDO, and belongs to the technical field of LDOs.
Background
LDO (low dropout linear regulator) is a very critical part of integrated circuits, and is a core component of advanced systems such as data converters, precision amplifiers, and VCOs (voltage controlled oscillators), which all require high power supply rejection ratios, low noise, and high current power supplies. The noise power supply of the DCDC output cannot meet the use requirements of the advanced system due to the large ripple. The high-performance LDO can avoid the drawbacks, so that the probability of the high-level system affecting the performance due to noise is greatly reduced. Therefore, high power supply rejection ratio and low noise design of LDOs are of paramount importance.
The off-chip capacitor LDO is mainly dominated by 1/f noise of a low frequency band, and the 1/f noise is far higher than the thermal noise of a device in the low frequency band. The resistor is a passive element and mainly contributes to thermal noise, and the common MOS tube current source is changed into a current source with resistance source degradation (RESISTIVE SOURCE DEGENERATION), so that low-frequency noise of current output can be remarkably reduced. Therefore, in low noise LDOs, resistive source degeneration structures are widely employed to reduce noise.
The PMOSFET power supply tube can realize low voltage difference and good reliability at the unit gain bandwidth of the worst point loop of the off-chip capacitor LDO power supply rejection ratio, but PSR (primary feedback) of the PMOSFET power supply tube is poorer than that of the NMOSFET, and the high power supply rejection ratio is required to be realized through the improvement of an internal circuit structure.
In the prior art, the modification of the LDO circuit often causes the working point of the LDO to be changed to a great extent on the premise of process, voltage and temperature (PVT) change, thereby affecting the performance and the normal working state of the LDO circuit.
Disclosure of Invention
Aiming at the problems of large noise and poor circuit stability in the prior art of improving the transformation of the power supply rejection ratio with the off-chip capacitor LDO circuit, the invention provides a high-voltage large-drive high-power supply rejection ratio LDO.
The invention relates to a high-voltage large-drive high-power supply rejection ratio LDO, which comprises a cascode resistive source degeneration circuit and a dynamic compensation circuit,
The common-source common-gate resistive source degeneration circuit adopts NMOS differential pair pipe input to obtain a low-voltage difference fixed primary output voltage;
and the dynamic compensation circuit adopts a dynamic zero compensation and dynamic bias mode to the primary output voltage to obtain the final output voltage.
The high-voltage large-drive high-power supply rejection ratio LDO of the invention, the cascode resistive source degeneration circuit comprises a MOS tube Mn0, a MOS tube Mn1, a MOS tube Mn2, a MOS tube Mn3, a MOS tube Mp0, a MOS tube Mp1, a resistor R0, a resistor R2, a resistor R3 and a current source,
The sources of the MOS tube Mn0 and the MOS tube Mn1 are commonly connected with one end of a current source, and the other end of the current source is grounded;
The grid electrode of the MOS tube Mn0 is connected with a primary output voltage connecting end VREF, and a resistor R0 is connected between the drain electrode of the MOS tube Mn1 and the low voltage source;
The drain electrode of the MOS tube Mn0 is connected with the source electrode of the MOS tube Mp0, the drain electrode of the MOS tube Mp0 is connected with the drain electrode of the MOS tube Mn2, and a resistor R2 is connected between the source electrode of the MOS tube Mn2 and a grounding point;
The grid electrode of the MOS tube Mp0 is connected with the grid electrode of the MOS tube Mp1, the source electrode of the MOS tube Mp1 is connected with the drain electrode of the MOS tube Mn1, the drain electrode of the MOS tube Mp1 is connected with the drain electrode of the MOS tube Mn3, the grid electrode of the MOS tube Mn3 is connected with the grid electrode of the MOS tube Mn2, and a resistor R3 is connected between the source electrode of the MOS tube Mn3 and a grounding point;
The drain electrode of the MOS transistor Mn3 is used as a primary output voltage connecting end VREF.
The high-voltage large-drive high-power supply rejection ratio LDO according to the invention, the cascode resistive source degeneration circuit (100) also comprises a MOS tube Mn5 and a capacitor C0,
The drain electrode of the MOS tube Mn3 is connected with the grid electrode of the MOS tube Mn5, the source electrode of the MOS tube Mn5 is grounded, and a capacitor C0 is connected between the drain electrode and the grid electrode.
The high-voltage large-drive high-power supply rejection ratio LDO according to the invention, the dynamic compensation circuit (200) comprises a MOS tube Mn4, a MOS tube Mn6, a MOS tube MP2, a MOS tube MP3, a MOS tube PMOSFET, a resistor R4, a resistor R5 and a capacitor C1,
The grid electrode of the MOS tube Mn5 is connected with the grid electrode of the MOS tube Mn4, the source electrode of the MOS tube Mn4 is grounded, the drain electrode of the MOS tube Mn5 is connected with the source electrode of the MOS tube Mn6, the grid electrode of the MOS tube Mn6 is connected with a fixed bias voltage, the drain electrode of the MOS tube Mn6 is connected with one end of a resistor R4, the other end of the resistor R5 is connected with a drain electrode of a MOS tube MP2, the other end of the resistor R5 is connected with a high-voltage power supply, a capacitor C1 is connected between the other end of the resistor R5 and the drain electrode of the MOS tube Mn4, the grid electrode of the MOS tube MP2 is connected with the grid electrode of a MOS tube MP3, the grid electrode of the MOS tube MP3 is connected with a high-voltage power supply, the grid electrode of the MOS tube MP3 is connected with the grid electrode of a MOS tube PMOSFET, the source electrode of the MOS tube PMOSFET is connected with the high-voltage power supply, and the drain electrode serves as an intermediate voltage output end.
The dynamic compensation circuit (200) further comprises an off-chip resistor R EXT 0, an off-chip resistor R EXT 1 and an off-chip capacitor C L,
An off-chip resistor R EXT and an off-chip resistor R EXT 0 are sequentially connected in series between the drain electrode of the MOS transistor PMOSFET and a grounding point, and an off-chip capacitor C L is connected in parallel with the off-chip resistor R EXT and the off-chip resistor R EXT;
The outgoing line between the off-chip resistor R EXT and the off-chip resistor R EXT 0 is used as a connecting end VFB, and the connecting end VFB is connected with the grid electrode of the MOS tube Mn 1.
The invention has the beneficial effects that the input voltage range can be 2.6V-40V, the output driving current can be up to 200mA, the off-chip capacitance is as low as 1uF, the power supply rejection ratio at the frequency point of 1MHz is as high as 50dB, the lowest voltage difference of the circuit is 250mV, and meanwhile, the fixed output voltage has low noise and is only 10.5uVrms at normal temperature. The circuit adopts an NMOS differential pair pipe input and a resistive source degradation common-source common-gate structure. The loop compensation of the circuit adopts dynamic zero compensation and a dynamic bias circuit, so that the no-load static power consumption is low, and the heavy-load loop is stable. Meanwhile, a feedforward zero point can be added at a high frequency point of 1MHz to improve PSR.
The circuit can greatly reduce the noise of the LDO fixed output voltage, and simultaneously adopts a matching and dynamic compensation mode to ensure the stability of the working point under the conditions of process, voltage, temperature and full load.
Drawings
FIG. 1 is a schematic circuit diagram of a high voltage, large drive, high power rejection ratio LDO according to the present invention;
fig. 2 is a reference low noise schematic of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
Detailed description of the inventionreferring to fig. 1, the present invention provides a high voltage, large drive, high power rejection ratio LDO, comprising a cascode resistive source degeneration circuit 100 and a dynamic compensation circuit 200,
The cascode resistive source degeneration circuit 100 adopts NMOS differential pair pipe input to obtain a low-dropout fixed primary output voltage;
the dynamic compensation circuit 200 adopts a dynamic zero compensation and dynamic bias mode to the primary output voltage to obtain a final output voltage.
Further, referring to FIG. 1, the cascode resistive source degeneration circuit (100) includes a MOS transistor Mn0, a MOS transistor Mn1, a MOS transistor Mn2, a MOS transistor Mn3, a MOS transistor Mp0, a MOS transistor Mp1, a resistor R0, a resistor R2, a resistor R3, and a current source,
The sources of the MOS tube Mn0 and the MOS tube Mn1 are commonly connected with one end of a current source, and the other end of the current source is grounded;
The grid electrode of the MOS tube Mn0 is connected with a primary output voltage connecting end VREF, and a resistor R0 is connected between the drain electrode of the MOS tube Mn1 and the low voltage source;
The drain electrode of the MOS tube Mn0 is connected with the source electrode of the MOS tube Mp0, the drain electrode of the MOS tube Mp0 is connected with the drain electrode of the MOS tube Mn2, and a resistor R2 is connected between the source electrode of the MOS tube Mn2 and a grounding point;
The grid electrode of the MOS tube Mp0 is connected with the grid electrode of the MOS tube Mp1, the source electrode of the MOS tube Mp1 is connected with the drain electrode of the MOS tube Mn1, the drain electrode of the MOS tube Mp1 is connected with the drain electrode of the MOS tube Mn3, the grid electrode of the MOS tube Mn3 is connected with the grid electrode of the MOS tube Mn2, and a resistor R3 is connected between the source electrode of the MOS tube Mn3 and a grounding point;
The drain electrode of the MOS transistor Mn3 is used as a primary output voltage connecting end VREF.
Still further, as shown in fig. 1, the cascode resistive source degeneration circuit 100 further includes a MOS transistor Mn5 and a capacitor C0,
The drain electrode of the MOS tube Mn3 is connected with the grid electrode of the MOS tube Mn5, the source electrode of the MOS tube Mn5 is grounded, and a capacitor C0 is connected between the drain electrode and the grid electrode.
Still further, as shown in fig. 1, the dynamic compensation circuit 200 includes a MOS transistor Mn4, a MOS transistor Mn6, a MOS transistor Mp2, a MOS transistor Mp3, a MOS transistor PMOSFET, a resistor R4, a resistor R5, and a capacitor C1,
The grid electrode of the MOS tube Mn5 is connected with the grid electrode of the MOS tube Mn4, the source electrode of the MOS tube Mn4 is grounded, the drain electrode of the MOS tube Mn5 is connected with the source electrode of the MOS tube Mn6, the grid electrode of the MOS tube Mn6 is connected with a fixed bias voltage, the drain electrode of the MOS tube Mn6 is connected with one end of a resistor R4, the other end of the resistor R5 is connected with a drain electrode of a MOS tube MP2, the other end of the resistor R5 is connected with a high-voltage power supply, a capacitor C1 is connected between the other end of the resistor R5 and the drain electrode of the MOS tube Mn4, the grid electrode of the MOS tube MP2 is connected with the grid electrode of a MOS tube MP3, the grid electrode of the MOS tube MP3 is connected with a high-voltage power supply, the grid electrode of the MOS tube MP3 is connected with the grid electrode of a MOS tube PMOSFET, the source electrode of the MOS tube PMOSFET is connected with the high-voltage power supply, and the drain electrode serves as an intermediate voltage output end.
The circuit of the embodiment adopts a diode following and dynamic compensation mode to realize broadband high PSR characteristics. The MOS tube Mn5, the MOS tube Mn4 and the capacitor C0 realize matching and dynamic compensation in a circuit.
Still further, as shown in connection with fig. 1, the dynamic compensation circuit 200 further includes an off-chip resistor R EXT 0, an off-chip resistor R EXT 1 and an off-chip capacitor C L,
An off-chip resistor R EXT and an off-chip resistor R EXT 0 are sequentially connected in series between the drain electrode of the MOS transistor PMOSFET and a grounding point, and an off-chip capacitor C L is connected in parallel with the off-chip resistor R EXT and the off-chip resistor R EXT;
The outgoing line between the off-chip resistor R EXT and the off-chip resistor R EXT 0 is used as a connecting end VFB, and the connecting end VFB is connected with the grid electrode of the MOS tube Mn 1.
The off-chip resistor R EXT is a variable resistor.
In order to realize large driving and ensure loop stability, the LDO circuit adopts a dynamic output resistance mode to increase the secondary pole point along with the increase of the load. The corresponding components comprise a MOS tube Mp2, a MOS tube Mp3, a resistor R4 and a resistor R5.
The process of implementing the low noise reference voltage circuit of the present invention is described below with reference to fig. 2:
In the LDO, a partial circuit for realizing noise shaping comprises a MOS tube Mn0, a MOS tube Mn1, a MOS tube MP0, a MOS tube MP1, a capacitor C0 and a bias current source. The circuit adopts an MOS tube asymmetric mirror image bias circuit, wherein the MOS tube Mn0 is a proportional tube, the MOS tube Mn1 is an inverse ratio tube, the MOS tube MP0 is a proportional tube, the MOS tube MP1 is an inverse ratio tube, and the circuit can judge that the VREF_NOISE to VREF in the circuit is equivalent to high impedance in fig. 2, and further forms a NOISE shaping circuit with the capacitor C0.
The LDO uses a resistive source degradation common-source common-gate structure, dynamic compensation and high-frequency compensation, has high PSR in a broadband, improves PSR by adding a feedforward zero point at a high frequency, simultaneously filters reference noise in a large RC mode in a circuit, greatly reduces the noise of the fixed output voltage of the LDO, has the characteristics of low power consumption and low noise, and ensures stable working points under no-load and full-load conditions and under the conditions of process, voltage and temperature fluctuation.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the different dependent claims and the features described herein may be combined in ways other than as described in the original claims. It is also to be understood that features described in connection with separate embodiments may be used in other described embodiments.
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| CN202183059U (en) * | 2011-06-23 | 2012-04-04 | 上海集成电路研发中心有限公司 | Low dropout linear regulator |
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