CN111812487B - Preparation method of failure analysis sample and failure analysis sample - Google Patents
Preparation method of failure analysis sample and failure analysis sample Download PDFInfo
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- CN111812487B CN111812487B CN202010673930.9A CN202010673930A CN111812487B CN 111812487 B CN111812487 B CN 111812487B CN 202010673930 A CN202010673930 A CN 202010673930A CN 111812487 B CN111812487 B CN 111812487B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2898—Sample preparation, e.g. removing encapsulation, etching
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Abstract
本发明提供一种失效分析样品的制备方法及失效分析样品，制备方法包括如下步骤：提供待分析的堆叠封装体，堆叠封装体中设置有多个堆叠的裸片，每一裸片具有设置焊垫的正面及与正面相对的背面，裸片的背面与其相邻的裸片的正面接触，所述裸片的焊垫与其相邻的裸片的焊垫电连接；去除目标裸片背面的其他裸片，至暴露出与所述目标裸片相邻的裸片的焊垫时停止；将暴露的焊垫电学引出，形成用于失效分析的样品。本发明优点是，对目标裸片背面进行去除操作，且利用非目标裸片焊垫作为电连接处，从而避免对目标裸片具有电路器件的正面进行去除操作，保护了正面的电路器件，能够制备出完整无损伤的目标裸片，大大提高了制样成功率，大大降低了制样难度。
The present invention provides a method for preparing a failure analysis sample and a failure analysis sample. The preparation method includes the following steps: providing a stack package to be analyzed, and the stack package body is provided with a plurality of stacked bare chips, and each bare chip has a set of solder joints. The front side of the pad and the back side opposite to the front side, the back side of the die is in contact with the front side of its adjacent die, and the pads of the die are electrically connected to the pads of the adjacent die; the other on the back side of the target die is removed Die, stop when the bonding pads of the bare chips adjacent to the target die are exposed; the exposed bonding pads are electrically pulled out to form samples for failure analysis. The advantage of the present invention is that the removal operation is performed on the backside of the target bare chip, and the non-target bare chip pad is used as an electrical connection, so as to avoid the removal operation on the front side of the target bare chip with circuit devices, protect the circuit devices on the front side, and can A complete and non-damaged target bare chip is prepared, which greatly improves the success rate of sample preparation and greatly reduces the difficulty of sample preparation.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a preparation method of a failure analysis sample and the failure analysis sample.
Background
As integrated circuit fabrication technology rapidly develops, the feature size of semiconductor devices is continuously decreasing, and the integration level is continuously increasing. Generally, in order to obtain a large-capacity memory chip, a plurality of memory dies (die) are stacked and packaged in the same chip, and at present, the number of the die can reach up to 16. The more dies that are stacked, the thinner the individual die needs to be. For failure analysis, a target single failure die needs to be obtained from a plurality of stacked dies to perform dynamic hotspot (dynamic hotspot) analysis, and the target die is required to be intact and capable of performing complete electrical test, which is extremely difficult for processing a thin sample of a single die in a stacked package.
Therefore, how to reduce the difficulty of sample preparation and improve the success rate of sample preparation becomes a problem which needs to be solved at present.
Disclosure of Invention
The invention aims to solve the technical problem of providing a preparation method of a failure analysis sample and the failure analysis sample, which can reduce the sample preparation difficulty and greatly improve the sample preparation success rate.
In order to solve the above problems, the present invention provides a method for preparing a failure analysis sample, comprising the steps of: providing a stacked package to be analyzed, wherein a plurality of stacked dies are arranged in the stacked package, each die is provided with a front surface provided with a welding pad and a back surface opposite to the front surface, the back surface of the die is contacted with the front surface of the adjacent die, and the welding pad of the die is electrically connected with the welding pad of the adjacent die; removing other bare chips on the back side of the target bare chip until the welding pads of the bare chips adjacent to the target bare chip are exposed; the exposed pads were electrically tapped to form samples for failure analysis.
Further, if the upper surface of the bonding pad of the die adjacent to the target die is higher than the back surface of the target die, the removing process is continued after the bonding pad of the die adjacent to the target die is exposed until the back surface of the target die is exposed.
Further, the back surface of the bare chip is provided with an adhesive layer, if the upper surface of the bonding pad of the bare chip adjacent to the target bare chip is higher than the lower surface of the adhesive layer, the removing treatment is continued after the bonding pad of the bare chip adjacent to the target bare chip is exposed, and the removing treatment is stopped until the adhesive layer of the target bare chip is exposed.
Further, the method of electrically leading out the exposed pad is to electrically lead out the pad by using a metal lead.
Further, after the step of removing the other dies, the method further comprises the steps of: turning over the stacked packaging body to enable the exposed welding pads to face upwards; in the step of electrically drawing out the exposed pad, a metal lead is soldered on the pad to electrically draw out the exposed pad.
Further, the method of removing other dies is grinding.
Further, before or after the step of removing the other dies on the back side of the target die, the method comprises the following steps: removing other dies on the front side of the target die.
Further, the bonding pads of the adjacent dies are electrically connected through metal leads.
Further, the pads of adjacent dies are electrically connected by conductive pillars through the dies.
The present invention also provides a failure analysis sample comprising: a package body; a target die disposed in the package, the target die having a front side on which bond pads are disposed and a back side opposite the front side; a test surface formed by removing other dies on the back surface of the target die from the back surface of the package body, wherein the bonding pads of the dies adjacent to the back surface of the target die are reserved, the reserved bonding pads are exposed to the test surface, and the bonding pads of the target die are electrically connected with the exposed bonding pads; and the electric connector is electrically connected with the reserved welding pad and electrically leads out the reserved welding pad.
Further, a back side of the target die is also exposed to the test side.
Further, a back side of the target die is provided with an adhesive layer exposed to the test side.
Further, the failure analysis sample further comprises a plurality of non-target dies, the non-target dies are arranged in the packaging body and are arranged on the front side of the target dies in a stacking mode, each non-target die is provided with a front side provided with a welding pad and a back side opposite to the front side, the back side of each non-target die is in contact with the front side of the adjacent non-target die or the target die, and the welding pad of each non-target die is electrically connected with the welding pad of the adjacent non-target die or the target die.
Further, the bonding pads of the target die and the reserved bonding pads are electrically connected through metal leads.
Further, the bonding pad of the target bare chip is electrically connected with the reserved bonding pad through the conductive pillar.
The method has the advantages that the back surface of the target bare chip is removed, and the welding pad of the non-target bare chip is used as the electric connection position, so that the front surface of the target bare chip with the circuit device is prevented from being removed, the circuit device on the front surface is protected, the complete and undamaged target bare chip can be prepared, the success rate of sample preparation is greatly improved, and the difficulty of sample preparation is greatly reduced.
Drawings
FIG. 1 is a schematic step diagram of a first embodiment of a method of preparing a failure analysis sample according to the present invention;
FIGS. 2A-2C are process flow diagrams of a first embodiment of a method of preparing a failure analysis sample according to the present invention;
fig. 3A to 3C are process flow diagrams of a second embodiment of the method for preparing a failure analysis sample according to the present invention.
Detailed Description
The following describes in detail the preparation method of the failure analysis sample and the specific embodiment of the failure analysis sample provided by the present invention with reference to the accompanying drawings.
At present, a conventional method for preparing a failure analysis sample is to grind a front side of a die to a bonding pad of a target die and grind a back side of the die to a back side of the target die by using a positive and negative grinding (polish) method to obtain a single target die, and then prick a probe card (prober card) for testing on the bonding pad to perform dynamic hotspot analysis.
However, this manufacturing method has a disadvantage of high sample preparation failure rate, and when a failure analysis sample is tested using a probe card, the probe card is damaged, resulting in an increase in analysis cost.
The inventors have found through research that the reason for the above problems is: due to the need to punch a probe card on the pads on the front side of the die, the front side of the die needs to be ground to within a few microns of the surface of the die, which results in a significant risk of damage to the circuitry on the surface of the die. Once the circuit on the surface of the bare chip is damaged, the sample preparation fails; when the probe card is bonded to the bonding pads on the front surface of the die, some bonding pads are not bonded yet and some bonding pads are deeply bonded, so that the probe card is damaged at a certain risk, and the analysis cost is increased.
In view of the above reasons, the invention provides a preparation method of a failure analysis sample, which greatly reduces the sample preparation difficulty and improves the sample preparation success rate.
FIG. 1 is a schematic step diagram of a first embodiment of a method of preparing a failure analysis sample according to the present invention. Referring to fig. 1, the method for preparing a failure analysis sample according to the present invention includes the following steps: step S10, providing a stacked package to be analyzed, wherein a plurality of stacked dies are arranged in the stacked package, each die has a front surface provided with a bonding pad and a back surface opposite to the front surface, the back surface of the die is contacted with the front surface of the adjacent die, and the bonding pad of the die is electrically connected with the bonding pad of the adjacent die; step S11, removing other bare chips on the back of the target bare chip until the bonding pads of the bare chips adjacent to the target bare chip are exposed; step S12, the exposed pads are electrically extracted to form a sample for failure analysis.
Fig. 2A to 2C are process flow diagrams of the first embodiment of the method for preparing a failure analysis sample according to the present invention.
Referring to step S10 and fig. 2A, a stacked package 20 to be analyzed is provided, in which a plurality of stacked dies are disposed in the stacked package 20. Four dice are shown in FIG. 2A, dice 201, 202, 203, and 204, respectively. Four dies 201, 202, 203, and 204 are arranged in a stack.
Each die includes a front side and a back side opposite the front side. For example, taking die 203 as an example, die 203 includes a front side 203B and a back side 203C opposite to front side 203B. The back side of the die is in contact with the front side of an adjacent die below it. Specifically, the back side of die 201 is in contact with the front side of die 202 adjacent therebelow, the back side of die 202 is in contact with the front side of die 203 adjacent therebelow, the back side of die 203 is in contact with the front side of die 204 adjacent therebelow, and the back side of die 204 is in structural contact with package substrate 300.
The front surface of the bare chip is provided with a welding pad. Specifically, a pad 201A is provided on the front surface of the die 201, a pad 202A is provided on the front surface of the die 202, a pad 203A is provided on the front surface of the die 203, and a pad 204A is provided on the front surface of the die 204. A circuit device is also disposed on the front side of the die.
The die pads are electrically connected to the die pads of an adjacent die below the die pads. Specifically, the pad 201A of the die 201 is electrically connected to the pad 202A of the die 201 adjacent to the lower side thereof, the pad 202A of the die 202 is electrically connected to the pad 203A of the die 203 adjacent to the lower side thereof, the pad 203A of the die 203 is electrically connected to the pad 204A of the die 204 adjacent to the lower side thereof, and the pad 204A of the die 204 is electrically connected to the pad 300A on the package substrate 300.
In this embodiment, the bonding pads of the die are electrically connected to the bonding pads of the die adjacent to the bonding pads below the die by metal wires. For example, the pad 203A of the die 203 is electrically connected to the pad 204A of the die 204 adjacent to the lower side thereof using the metal wire 206.
Referring to step S11 and fig. 2B, the other dies on the back side of the target die are removed until the bonding pads of the dies adjacent to the bottom of the target die are exposed. The target die refers to a die which needs to be subjected to failure analysis subsequently.
In the present embodiment, the die 203 is used as a target die for explanation. In this step, other dies on the back side of the die 203, such as the die 204, are removed until the bonding pads 204A of the die 204 adjacent to the bottom of the die 203 are exposed. It is understood that the package substrate 300 and the stacked package 20 under the die 203 are also removed in this step.
In this step, when the pad 204A of the die 204 adjacent to the lower side of the die 203 is exposed, the removal process is stopped so that the pad 204A is exposed to the surface of the stacked package 20. The surface is used as a testing surface of a failure analysis sample prepared by the preparation method, and the welding pad 204A is used as an external electric connection part of the failure analysis sample. The removal process may be polishing, including but not limited to mechanical polishing, chemical mechanical polishing, and the like.
Further, if the upper surface of the bonding pad of the die adjacent to the target die is higher than the back surface of the target die, the removing process can be continued after the bonding pad of the die adjacent to the lower part of the target die is exposed, and the removing process is stopped until the back surface of the target die is exposed. Specifically, in the present embodiment, the upper surface of the pad 204A of the die 204 is higher than the back surface of the die 203, so that when the pad 204A of the die 204 adjacent to the lower side of the die 203 is exposed, the removing process is continued until the back surface 203C of the die 203 is exposed, and at this time, the exposed area of the pad 204A is large, which can provide a sufficient connection area for subsequent electrical connection, thereby improving the yield of electrical connection.
Further, there is a bonding layer (DAF) on the back side of each of the dies. The die is bonded to other die by a bonding layer. For example, die 203 has an adhesive layer 205 on its back side, and die 203 is bonded to the front side of die 204 by adhesive layer 205. Then in step S11, if the upper surface of the bonding pad of the die adjacent to the target die is higher than the lower surface of the bonding layer, the removal process is continued after the bonding pad of the die adjacent to the bottom of the target die is exposed, and is stopped when the bonding layer of the target die is exposed. Specifically, if the upper surface of the pad 204A of the die 204 is higher than the lower surface of the adhesive layer 205, after the pad 204A of the die 204 adjacent to the lower side of the die 203 is exposed, the removing process is continued until the adhesive layer 205 of the die 203 is exposed, and at this time, the exposed area of the pad 204A is large, which can provide a sufficient connection area for subsequent electrical connection, thereby improving the yield of electrical connection.
In this embodiment, the other die on the front side of the target die is reserved, and optionally, in other embodiments of the present invention, before or after step S11, the following steps are included: removing other dies on the front side of the target die. For example, dice 201 and 202 are removed from the front side of die 203. It is understood that after dies 201 and 202 on the front side of die 203 are removed, the front side of die 203 is not fully exposed to protect circuit device 2031 on the front side of die 203 from damage.
Referring to step S12 and fig. 2C, the exposed pads are electrically extracted to form a sample for failure analysis. After step S11, the stacked package 20 is turned over so that the exposed pad 204A faces upward; metal leads 208 are soldered to the pads 204A to electrically lead the exposed pads out to the external conductive structure 400, which can be used for subsequent failure analysis.
The preparation method of the failure analysis sample removes the back of the target bare chip, and uses the welding pad of the non-target bare chip as the electric connection position, thereby avoiding removing the front of the target bare chip with the circuit device, protecting the circuit device on the front, preparing the complete and undamaged target bare chip, greatly improving the success rate of sample preparation, and greatly reducing the difficulty of sample preparation.
In a first embodiment, the bonding pads of the die are electrically connected with the bonding pads of the die adjacent to the bonding pads below the die by using metal leads. For example, the pad 203A of the die 203 is electrically connected to the pad 204A of the die 204 adjacent to the lower side thereof using the metal wire 206. In other embodiments of the present invention, the bonding pads of the die and the bonding pads of the die adjacent to the bonding pads under the die can be electrically connected by conductive pillars penetrating through the die.
Fig. 3A to 3C are process flow diagrams of a second embodiment of the method for preparing a failure analysis sample according to the present invention, wherein fig. 3A is a schematic structural diagram of a stacked package according to the second embodiment of the method for preparing a failure analysis sample according to the present invention, fig. 3B is a schematic structural diagram of the second embodiment of the method for preparing a failure analysis sample after removing another die on the back side of a target die, and fig. 3C is a schematic structural diagram of the second embodiment of the method for preparing a failure analysis sample according to the present invention after electrically leading out exposed bonding pads. Referring to fig. 3A, the bonding pad of the die is electrically connected to the bonding pad of the die adjacent to the bonding pad below the die by a conductive pillar penetrating through the die, and the bonding pad is disposed corresponding to the conductive pillar. For example, the pad 203A of the die 203 is electrically connected to the pad 204A of the die 204 adjacent to the lower side thereof by the conductive pillar 207 penetrating through the die 203, and the pad 204A is disposed corresponding to the conductive pillar 207. Referring to fig. 3B, after the die 204 on the back side of the die 203 is removed, the bonding pads 204A are exposed. Referring to fig. 3C, the pad 204A is soldered to the metal lead 208 to form a sample for failure analysis. The pad 204A and the pad 203A are electrically connected by a conductive pillar 207. Wherein the conductive pillars 207 may be formed through a Through Silicon Via (TSV) manufacturing process.
The invention also provides a failure analysis sample prepared by the preparation method. Referring to fig. 2C, the failure analysis sample includes the package 20, the target die 203, the testing surface 20A and the electrical connectors.
The target die 203 is disposed in the package 20. The target die 203 has a front side 203B and a back side 203C. A pad 203A is disposed on the front surface 203B, and a circuit device 2031 is disposed on the front surface 203B.
Further, in this embodiment, the failure analysis sample further includes a plurality of non-target dies, the non-target dies are disposed in the package body 20, and the stack is disposed above the target die 203. As shown in fig. 2C, two non-target dies, 201 and 202, are depicted, the non-dies 201 and 202 being disposed in a stack on the target die 203.
Each non-target die has a front side on which the bonding pads are disposed and a back side opposite the front side, the back side of the non-target die being in contact with the front side of an adjacent non-target die or a target die therebelow. Specifically, the die 201 is disposed on the die 202, and the back side of the die 201 is in contact with the front side of the die 202; the die 202 is disposed on a target die 203, and the back side of the die 202 is in contact with the front side of the target die 203.
The bonding pad of the non-target die is electrically connected with the bonding pad of the adjacent non-target die or target die below the non-target die. Specifically, a pad 201A of the die 201 is electrically connected to a pad 202A of the die 202, and a pad 202A of the die 202 is electrically connected to a pad 203A of the target die 203. In the present embodiment, the electrical connection is made by using the metal wire 206, and in another embodiment of the present invention, the electrical connection is made by using the conductive post 207 (see fig. 3C).
Further, in other embodiments of the present invention, in forming the failure analysis sample, the non-target dies 201 and 202 stacked on the front side of the target die 203 are removed, so that only the target die is in the package 20.
The test face 20A is formed by removing other dies from the back side of the target die 203 from the back side of the package 20. Wherein the bonding pads 204A of the die adjacent to the back side of the target die 203 are preserved. The remaining pads 204A are exposed to the test face 20A, and the pads 203A of the target die 203 are electrically connected to the exposed pads 204A. In the present embodiment, the electrical connection is made by using the metal wire 206, and in another embodiment of the present invention, the electrical connection is made by using the conductive pillar 207 (see fig. 3C).
The back side 203C of the target die 203 is also exposed to the test side 20A. Further, in the present embodiment, the back surface of the target die 203 is provided with an adhesive layer 205, and the adhesive layer 205 is exposed to the test surface 20A.
The electrical connector is electrically connected with the reserved pad 204A, and electrically leads out the reserved pad 204A. In this embodiment, the electrical connection is a metal lead 208, and the metal lead 208 can be connected to an external conductive structure for subsequent failure analysis.
In the failure analysis sample, the back side of the target bare chip is removed, and the welding pad of the non-target bare chip is used as an electric connection part, so that the removal operation of the front side of the target bare chip with the circuit device is avoided, and the circuit device on the front side is protected.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
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