CN111799323A - Superjunction insulated gate bipolar transistor structure and fabrication method thereof - Google Patents

Abstract

The invention discloses a super junction insulated gate bipolar transistor structure and a manufacturing method thereof. The super junction insulated gate bipolar transistor structure includes a collector region, a first epitaxial layer and a second epitaxial layer arranged in sequence along a first direction, the collector region is arranged in cooperation with the collector; the first epitaxial layer A plurality of super junction structures arranged at intervals are distributed inside, and the super junction structure includes two or more super junctions arranged in sequence along the first direction, and the two or more super junctions are staggered from each other in the second direction; A plurality of first trenches arranged at intervals are distributed in the second epitaxial layer, and a gate electrode is arranged in each of the first trenches. The super junction insulated gate bipolar transistor structure provided by the present invention can reduce the saturation voltage drop during turn-on, and the super junction insulated gate bipolar transistor structure provided by the embodiment of the present invention can speed up the emptying of the drift region when the device is turned off The recombination speed of the holes is reduced, the tail current is reduced, and the turn-off loss is reduced.

Description

Superjunction insulated gate bipolar transistor structure and fabrication method thereof

technical field

The invention relates to a transistor, in particular to a super junction insulated gate bipolar transistor structure and a fabrication method thereof, belonging to the technical field of semiconductors.

Background technique

The structure of a super junction insulated gate bipolar transistor in the current prior art is shown in Figure 1, wherein 1 is a P-collector region, 2 is an N-drift region, and 3 is a P-type super junction region or P-type Type super junction structure, 4 is N+ drift region, 5 is gate oxide layer, 6 is gate, 7 is P well region, 8 is N+ emitter, 9 is dielectric layer, 10 is emitter metal, 11 is P+ collector , 12 is the collector metal, the P-type super junction region in the existing super junction insulated gate bipolar transistor is on the same vertical line in the longitudinal direction, and the structure is the same as that of the super junction VDMOSFET device, of course, For super junction VDMOSFET, there is only one type of conductive carrier. For example, N-channel VDMOSFET only conducts electrons. In this case, electrons can pass through the middle of the P-type super junction region; but for super junction insulated gate bipolar For type transistors, there are two types of conductive carriers, both electrons and holes participate in conduction, such as N-channel insulated gate bipolar transistors, electrons from top to bottom, holes from bottom to top, must pass through Only the entire N-drift region can complete the recombination, so the conduction efficiency of the existing superjunction insulated gate bipolar transistor is very low.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide a super junction insulated gate bipolar transistor structure and a fabrication method thereof to overcome the deficiencies in the prior art.

In order to realize the foregoing invention purpose, the technical scheme adopted in the present invention includes:

An embodiment of the present invention provides a super junction insulated gate bipolar transistor structure, which includes a collector region, a first epitaxial layer and a second epitaxial layer arranged in sequence along a first direction, and the collector region cooperates with the collector set up,

A plurality of super junction structures arranged at intervals are distributed in the first epitaxial layer, the super junction structure includes two or more super junctions arranged in sequence along the first direction, and the two or more super junctions are arranged in the second staggered in direction;

A plurality of first trenches arranged at intervals are distributed in the second epitaxial layer, each first trench is provided with a gate, and the second epitaxial layer includes a first semiconductor layer and is formed on the first semiconductor layer the second semiconductor layer, the second semiconductor layer is a well region, a plurality of emitter electrodes arranged at intervals are distributed in the well region, each emitter electrode is arranged in cooperation with a trench, and a part of each first trench is an area is arranged in the well area;

Wherein, the collector region, the super junction structure, and the well region are all of the first conductivity type, and the first epitaxial layer, the first semiconductor layer, and the emitter are all of the second conductivity type.

Further, the first epitaxial layer includes more than two third semiconductor layers arranged along the first direction, each of the third semiconductor layers is provided with a plurality of super junctions, at least two adjacent third semiconductor layers The superjunctions within the layers are staggered from each other in the second direction.

Further, the super junction includes a second trench disposed in the third semiconductor layer and a P-type pillar filled in the second trench, or the super junction is implanted and heated by P-type The P-type pillar is formed by processing a part of the third semiconductor layer by means of diffusion.

Further, the first semiconductor layer is an N+ drift region, and the third semiconductor layer is an N- drift region, wherein the concentrations of the first semiconductor layer and the third semiconductor layer may be the same or different. of. If not, generally the concentration of the first semiconductor layer is higher.

Further, a continuous insulating layer is provided between the gate electrode and the inner wall of the first trench, and the insulating layer is a gate oxide layer.

Further, the second semiconductor layer and the first semiconductor layer are integrally formed, the first trench extends from the surface of the second semiconductor layer into the first semiconductor layer, and the emitter is formed in the surface region of the second semiconductor layer and surrounds Corresponding first grooves are provided.

Further, a dielectric layer is also provided on the well region, the dielectric layer is distributed between the gate electrode and the emitter metal, the emitter metal is electrically connected to the emitter, and the collector region is connected to the collector electrode. Metal electrical connection.

In some specific implementations, the superjunction insulated gate bipolar transistor structure includes a collector metal, a P+ collector, a P- collector, a first N-drift region, a first N-drift region, a first two N-drift regions, a first semiconductor layer, a P-well region and an emitter metal;

A plurality of first P-type pillars arranged at intervals are distributed in the first N-drift region, and a plurality of second P-type pillars arranged at intervals are distributed in the second N-drift region. The pillar corresponds to a second P-type pillar and forms a super junction structure, and the first P-type pillar and the second P-type pillar are offset from each other in the second direction, and the first P-type pillar is also connected to the second N-drift region is in contact or connection, and the second P-type pillar is also in contact or connection with the first N-drift region and the first semiconductor layer, respectively;

There are a plurality of N+ emitters arranged at intervals in the P well region, each N+ emitter is arranged in cooperation with a first trench, and the upper and lower ends of each first trench are respectively arranged in the P well region, In the first semiconductor layer, a gate is arranged in the first trench, and the P well region and the N+ emitter are arranged around the first trench;

And, a dielectric layer is also arranged on the P well region, the dielectric layer is distributed between the gate electrode and the emitter metal, and the P+ collector electrode is electrically combined with the collector electrode metal and the P- collector region, The P well region is homogeneously combined with the N+ emitter and the emitter metal; wherein, the first semiconductor layer and the P well region are integrally formed.

Further, the ratio of the depth of the first P-type pillar to the thickness of the first N-drift region is 3/5-9/10.

Further, the ratio of the depth of the P well region and the N+ emitter to the depth of the first trench is 2/5-4/5 and 1/10-1/4, respectively.

Embodiments of the present invention also provide a method for fabricating a super junction insulated gate bipolar transistor structure, which includes:

providing a substrate, the substrate comprising a P-collector region, and an N-drift region epitaxially formed on a first side of the substrate;

A plurality of P-type super junction structures are formed in the N-drift region, each of the P-type super junction structures includes two or more P-type pillars arranged along the longitudinal direction of the N-drift region, the two More than one P-type pillars are staggered from each other in the lateral direction of the N-drift region;

epitaxially forming an N+ drift region on the N-drift region;

A plurality of first trenches are etched in the N+ drift region, a continuous insulating layer is formed on the inner wall of the first trench, and polysilicon is filled in the first trench to form a gate;

A P well region and an N+ emitter are formed by processing in the N+ drift region, and the P well region can respectively form a PN junction with the N+ drift region and the N+ emitter;

forming a dielectric layer and an emitter metal on the P-well region, and the dielectric layer is distributed between the gate electrode and the emitter metal;

A P+ collector and a collector metal are formed on the second side of the substrate, and the P+ collector is electrically combined with the collector metal and the P- collector, and the first side and the second side face away from each other. set up.

Further, the manufacturing method specifically includes: sequentially epitaxially forming two or more N-drift regions on the first surface of the substrate, and processing and forming a plurality of P-type pillars in each of the N-drift regions, at least The P-type pillars in two adjacent N-drift regions are staggered from each other in the lateral direction of the N-drift regions.

Further, the manufacturing method specifically includes: using a photolithography process to etch and form a plurality of second trenches in the N-drift region, and then filling the second trenches with P-type silicon to form the P-type pillars, or the P-type pillars are formed in the N-drift region by means of P-type implantation and thermal diffusion.

Further, the manufacturing method=specifically includes: forming a P well region in the region of the N+ drift region close to the upper surface by ion implantation and high temperature diffusion process, and forming a P well region in the P well region by ion implantation and high temperature diffusion process A plurality of N+ emitters arranged at intervals, wherein the P well region and the N+ emitter are distributed around the first trench, and the depths of the P well region and the N+ emitter are respectively 2 times the depth of the first trench. /5-4/5, 1/10-1/4.

Further, the manufacturing method specifically includes: firstly performing a thinning process on the substrate from the second surface of the substrate, and forming a P-type implant in a region of the substrate close to the second surface A P+ collector on which a collector metal is then formed.

Further, the dielectric layer includes a silicon dioxide layer.

Compared with the prior art, the advantages of the present invention include:

In the super junction insulated gate bipolar transistor structure provided by the embodiment of the present invention, electrons and holes can recombine after a shorter distance. Therefore, the super junction insulated gate bipolar transistor structure provided by the embodiment of the present invention can The saturation voltage drop during turn-on is reduced, and the super junction insulated gate bipolar transistor structure provided by the embodiment of the present invention can speed up the recombination speed of holes in the drift region when the device is turned off, reduce the tail current, and reduce the power consumption. turn-off loss.

Description of drawings

1 is a schematic structural diagram of a super junction insulated gate bipolar transistor in the prior art;

2 is a schematic structural diagram of a super junction insulated gate bipolar transistor structure in a typical embodiment of the present invention;

Description of reference numerals: 1-P-collector region, 2-N-drift region, 21-first N-drift region, 22-second N-drift region, 3-P-type super junction structure, 31-first P-type pillar, 32-second P-type pillar, 4-N+ drift region, 5-gate oxide layer, 6-gate, 7-P well region, 8-N+ emitter, 9-dielectric layer, 10-emitter Metal, 11-P+ collector, 12- collector metal.

Detailed ways

In view of the deficiencies in the prior art, the inventor of the present application was able to propose the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

IGBT: Insulated Gate Bipolar Transistor, insulated gate bipolar transistor;

VDMOSFET: Vertical Diffused Metal-Oxide-Semiconductor Field-EffectTransistor, vertical diffusion metal oxide semiconductor field effect transistor.

An embodiment of the present invention provides a super junction insulated gate bipolar transistor structure, wherein the P-type pillar (or understood as a P-type super junction structure) of the super junction region of the super junction insulated gate bipolar transistor structure is longitudinally Divided into several sections, the sections of the P-type pillar or P-type super junction structure are staggered from each other in the lateral direction.

An embodiment of the present invention provides a super junction insulated gate bipolar transistor structure, which includes a collector region, a first epitaxial layer and a second epitaxial layer arranged in sequence along a first direction, and the collector region cooperates with the collector set up,

A plurality of super junction structures arranged at intervals are distributed in the first epitaxial layer, the super junction structure includes two or more super junctions arranged in sequence along the first direction, and the two or more super junctions are arranged in the second staggered in direction;

A plurality of first trenches arranged at intervals are distributed in the second epitaxial layer, each first trench is provided with a gate, and the second epitaxial layer includes a first semiconductor layer and is formed on the first semiconductor layer the second semiconductor layer, the second semiconductor layer is a well region, a plurality of emitter electrodes arranged at intervals are distributed in the well region, each emitter electrode is arranged in cooperation with a trench, and a part of each first trench is an area is arranged in the well area;

Wherein, the collector region, the super junction structure, and the well region are all of the first conductivity type, and the first epitaxial layer, the first semiconductor layer, and the emitter are all of the second conductivity type.

The technical solution, its implementation process and principle, etc. will be further explained below in conjunction with the accompanying drawings. It should be noted that the ion implantation, high temperature diffusion process, etching and other processes used in the present invention are all skilled in the art. For the known existing process, the specific process condition parameters and the like can be adjusted according to specific requirements, which are not specifically limited here.

Example 1

Please refer to FIG. 2 , a super junction insulated gate bipolar transistor structure including a collector metal 12 , a P+ collector 11 , a P- collector region 1 , and a first N- drift region 21 arranged in sequence along a first direction , the second N-drift region 22, the N+ drift region 4, the P-well region 7 and the emitter metal 10;

A plurality of first P-type super junctions 31 are distributed in the first N-drift region 21 at intervals, and a plurality of second P-type pillars 32 are distributed in the second N-drift region 22 at intervals. A first P-type pillar 31 corresponds to at least one second P-type pillar 32 and forms a P-type super junction structure, and the first P-type pillar 31 and the second P-type pillar 32 are in the second direction Staggered from each other, the first P-type pillar 31 is also in contact with or connected to the second N-drift region 22 , and the second P-type pillar 32 is also in contact with the first N-drift region 21 and the N+ drift region 4 respectively. or connection;

A plurality of N+ emitters 8 arranged at intervals are distributed in the P well region 7, each N+ emitter 8 is arranged in cooperation with a first trench, and the upper and lower ends of each first trench are respectively arranged on the P In the well region 7 and the N+ drift region 4, a gate 6 is arranged in the first trench, and the P well region 7 and the N+ emitter 8 are arranged around the first trench;

And, the P well region 7 is also provided with a dielectric layer 9, the dielectric layer 9 is distributed between the gate 6 and the emitter metal 10, the P+ collector 11 and the collector metal 12, P- The collector region 1 is electrically combined, and the P well region 7 is electrically combined with the N+ emitter 8 and the emitter metal 10 ; wherein the N+ drift region 4 and the P well region 7 are integrally formed.

Specifically, the ratio of the depth of the first P-type pillar 31 to the thickness of the first N-drift region 21 is 3/5-9/10, and the depth of the P-well region 7 and the N+ emitter 8 is the same as the thickness of the first N-drift region 21 . The ratios of the depths of the first trenches are respectively 2/5-4/5 and 1/10-1/4; a continuous insulating layer 5 is arranged between the gate 6 and the inner wall of the first trench. The layer is a gate oxide layer; wherein, the gate 6 is polysilicon filled in the first trench.

Specifically, a method for fabricating a super junction insulated gate bipolar transistor structure may include the following steps:

1) providing a substrate comprising a P-collector region 1;

2) A first N-drift region 21 is epitaxially formed on the first surface of the substrate, and is engraved from the surface of the first N-drift region 21 along its thickness direction (which can be understood as the longitudinal direction, the first direction) A plurality of trenches are formed by etching, and P-type silicon is filled in the trenches to form a plurality of first P-type silicon pillars 31, or, directly through the ion implantation and high temperature diffusion process in the first N-drift region 21 forming a plurality of first P-type silicon pillars 31;

3) Epitaxially forming a second N-drift region 22 on the first N-drift region 21, and from the surface of the second N-drift region 22 along its thickness direction (which can be understood as the longitudinal direction, the first direction ) etching to form a plurality of trenches, and filling the trenches with P-type silicon to form a plurality of second P-type silicon pillars 32, or directly through the ion implantation and high temperature diffusion process in the second N-drift A plurality of second P-type silicon pillars 32 are formed in the region 22, and the second P-type silicon pillars 32 and the first P-type silicon pillars 31 are staggered from each other in the lateral direction (ie, the aforementioned second direction);

4) epitaxially forming an N+ drift region 4 on the second N-drift region 22;

5) A plurality of first trenches are etched in the N+ drift region 4, a continuous insulating layer 5 is formed on the inner wall of the first trench, and polysilicon is filled in the first trench to form a gate pole 6;

6) forming a P well region 7 and an N+ emitter 8 in the N+ drift region 4, and the P well region 7 can respectively form a PN junction with the N+ drift region 4 and the N+ emitter 8;

7) forming a dielectric layer 9 and an emitter metal 10 on the P-well region 7, and the dielectric layer 9 is distributed between the gate 6 and the emitter metal 10;

8) A P+ collector 11 and a collector metal 12 are formed on the second surface of the substrate, and the P+ collector 11 is electrically combined with the collector metal 12 and the P- collector region 1, and the first The face and second face are set away from each other.

Comparative Example 1

As shown in FIG. 1, a super junction insulated gate bipolar transistor structure includes a collector metal 12, a P+ collector 11, a P- collector region 1, an N- drift region 2, N+ drift region 4, P well region 7 and emitter metal 10;

A plurality of P-type super structures 3 arranged at intervals are distributed in the N-th drift region 2, and the P-type super structures 3 are also in contact or connection with the N+ drift region 4;

A plurality of N+ emitters 8 arranged at intervals are distributed in the P well region 7, each N+ emitter 8 is arranged in cooperation with a first trench, and the upper and lower ends of each first trench are respectively arranged on the P In the well region 7 and the N+ drift region 4, a gate 6 is arranged in the first trench, and the P well region 7 and the N+ emitter 8 are arranged around the first trench;

And, the P well region 7 is also provided with a dielectric layer 9, the dielectric layer 9 is distributed between the gate 6 and the emitter metal 10, the P+ collector 11 and the collector metal 12, P- The collector region 1 is electrically combined, and the P well region 7 is electrically combined with the N+ emitter 8 and the emitter metal 10 ; wherein the N+ drift region 4 and the P well region 7 are integrally formed.

The super junction IGBT products of 650V75A were fabricated according to the super junction insulated gate bipolar transistor structures in Example 1 and Comparative Example 1 respectively, and the obtained super junction IGBT products were tested. The turn-on voltage drop of the junction IGBT product is 1.15V and the turn-off loss is 1.9mJ, while the turn-on voltage drop of the 650V75A super junction IGBT product in Comparative Example 1 is 1.45V and the turn-off loss is 2mJ.

An embodiment of the present invention provides a super junction insulated gate bipolar transistor structure, wherein the P-type pillar (or understood as a P-type super junction structure) of the super junction region of the super junction insulated gate bipolar transistor structure is longitudinally Divided into several sections, the sections of the P-type pillar or P-type super junction structure are staggered from each other in the lateral direction.

Since electrons and holes in the insulated gate bipolar transistor structure participate in conduction at the same time, the embodiments of the present invention provide a super junction insulated gate bipolar transistor structure where electrons and holes can recombine after a shorter distance , therefore, the super junction insulated gate bipolar transistor structure provided by the embodiment of the present invention can reduce the saturation voltage drop during turn-on, and accelerate the recombination speed of holes in the drift region when the device is turned off, reduce the tail current, and reduce the turn-off Compared with the super junction insulated gate bipolar transistor in the prior art, the embodiment of the present invention provides a super junction insulated gate bipolar transistor whose on-voltage is reduced by about 20%, The breaking loss is reduced by about 5%.

It should be understood that the above-mentioned embodiments are only intended to illustrate the technical concept and characteristics of the present invention, and the purpose thereof is to enable those who are familiar with the art to understand the content of the present invention and implement it accordingly, and cannot limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included within the protection scope of the present invention.

Claims (10)

1. A super junction insulated gate bipolar transistor structure, characterized in that it comprises a collector region, a first epitaxial layer and a second epitaxial layer that are arranged in sequence along a first direction, and the collector region is arranged in coordination with a collector electrode; A plurality of super junction structures arranged at intervals are distributed in the first epitaxial layer, the super junction structure includes two or more super junctions arranged in sequence along the first direction, and the two or more super junctions are arranged in the second staggered in direction; A plurality of first trenches arranged at intervals are distributed in the second epitaxial layer, each first trench is provided with a gate, and the second epitaxial layer includes a first semiconductor layer and is formed on the first semiconductor layer the second semiconductor layer, the second semiconductor layer is a well region, a plurality of emitter electrodes arranged at intervals are distributed in the well region, each emitter electrode is arranged in cooperation with a first trench, and each first trench The local area is set in the well area; Wherein, the collector region, the super junction structure, and the well region are all of the first conductivity type, and the first epitaxial layer, the first semiconductor layer, and the emitter are all of the second conductivity type. 2 . The superjunction insulated gate bipolar transistor structure according to claim 1 , wherein the first epitaxial layer comprises two or more third semiconductor layers arranged along the first direction, and each of the third semiconductor layers. 3 . Each of the semiconductor layers is provided with a plurality of super junctions, and the super junctions in at least two adjacent third semiconductor layers are staggered from each other in the second direction. 3 . The super junction insulated gate bipolar transistor structure according to claim 2 , wherein the super junction comprises a second trench disposed in the third semiconductor layer and a second trench filled in the second trench. 4 . The inner P-type pillar, or the super junction is a P-type pillar formed by processing a part of the third semiconductor layer by means of P-type implantation and thermal diffusion. 4 . The superjunction insulated gate bipolar transistor structure of claim 2 , wherein the first semiconductor layer is an N+ drift region, and the third semiconductor layer is an N− drift region. 5 . 5. The superjunction insulated gate bipolar transistor structure according to claim 1, wherein a continuous insulating layer is provided between the gate and the inner wall of the first trench; and/or the second semiconductor The layer is integrally formed with the first semiconductor layer, the first trench extends from the surface of the second semiconductor layer into the first semiconductor layer, and the emitter is formed in the surface region of the second semiconductor layer and surrounds the corresponding first trench; And/or, a dielectric layer is further provided on the well region, the dielectric layer is distributed between the gate electrode and the emitter metal, the emitter metal is electrically connected to the emitter, and the collector region is connected to the collector. Electrode metal electrical connection. 6. The superjunction insulated gate bipolar transistor structure according to claim 1, characterized by comprising a collector metal, a P+ collector, a P- collector region, a first N-drift region, a collector metal, a P+ collector, a P- collector region, a first N-drift region, a second N-drift region, a first semiconductor layer, a P-well region, and an emitter metal; A plurality of first P-type pillars arranged at intervals are distributed in the first N-drift region, and a plurality of second P-type pillars arranged at intervals are distributed in the second N-drift region. The pillar corresponds to a second P-type pillar and forms a super junction structure, and the first P-type pillar and the second P-type pillar are offset from each other in the second direction, and the first P-type pillar is also connected to the second N-drift region is in contact or connection, and the second P-type pillar is also in contact or connection with the first N-drift region and the first semiconductor layer, respectively; There are a plurality of N+ emitters arranged at intervals in the P well region, each N+ emitter is arranged in cooperation with a first trench, and the upper and lower ends of each first trench are respectively arranged in the P well region, In the first semiconductor layer, a gate is arranged in the first trench, and the P well region and the N+ emitter are arranged around the first trench; And, a dielectric layer is also arranged on the P well region, the dielectric layer is distributed between the gate electrode and the emitter metal, and the P+ collector electrode is electrically combined with the collector electrode metal and the P- collector region, The P well region is homogeneously combined with the N+ emitter and the emitter metal; wherein, the first semiconductor layer and the P well region are integrally formed. 7 . The level junction insulated gate bipolar transistor structure of claim 6 , wherein the ratio of the depth of the first P-type pillar to the thickness of the first N-drift region is 3/5-9. 8 . /10; and/or, the ratio of the depth of the P well region and the N+ emitter to the depth of the first trench is 2/5-4/5 and 1/10-1/4, respectively. 8. A method for fabricating a super junction insulated gate bipolar transistor structure, comprising: providing a substrate, the substrate comprising a P-collector region, and an N-drift region epitaxially formed on a first side of the substrate; A plurality of P-type super junction structures are formed in the N-drift region, each of the P-type super junction structures includes two or more P-type pillars arranged along the longitudinal direction of the N-drift region, the two More than one P-type pillars are staggered from each other in the lateral direction of the N-drift region; epitaxially forming an N+ drift region on the N-drift region; A plurality of first trenches are etched in the N+ drift region, a continuous insulating layer is formed on the inner wall of the first trench, and polysilicon is filled in the first trench to form a gate; A P well region and an N+ emitter are formed by processing in the N+ drift region, and the P well region can respectively form a PN junction with the N+ drift region and the N+ emitter; forming a dielectric layer and an emitter metal on the P-well region, and the dielectric layer is distributed between the gate electrode and the emitter metal; A P+ collector and a collector metal are formed on the second side of the substrate, and the P+ collector is electrically combined with the collector metal and the P- collector, and the first side and the second side face away from each other. set up. 9 . The manufacturing method according to claim 8 , further comprising: sequentially epitaxially forming two or more N-drift regions on the first surface of the substrate, and processing each of the N-drift regions to form them. 10 . A plurality of P-type pillars, the P-type pillars in at least two adjacent N-drift regions are staggered from each other in the lateral direction of the N-drift region; preferably, the manufacturing method specifically includes: using a photolithography process to The N-drift region is etched to form a plurality of second trenches, and then the second trenches are filled with P-type silicon to form the P-type pillars. The P-type pillar is formed in the N-drift region. 10. The manufacturing method according to claim 8, characterized in that it specifically comprises: forming a P well region in a region of the N+ drift region close to the upper surface by ion implantation and high temperature diffusion process, and forming a P well region in the region by ion implantation and high temperature diffusion process. A plurality of N+ emitters arranged at intervals are formed in the P-well region, wherein the P-well region and the N+ emitter are distributed around the first trench, and the depths of the P-well region and the N+ emitter are respectively 2/5-4/5, 1/10-1/4 of the depth of the trench; and/or, the manufacturing method specifically includes: firstly reducing the depth of the substrate from the second surface of the substrate Thin treatment, and adopt P-type implantation to form a P+ collector in the region of the substrate close to the second surface, and then form a collector metal on the P+ collector; and/or, the dielectric layer includes dioxide silicon layer.

Images