CN111797031A - Method for recording power-on accumulated time of task machine by using EEPROM (electrically erasable programmable read-Only memory) under battery-free condition - Google Patents
Method for recording power-on accumulated time of task machine by using EEPROM (electrically erasable programmable read-Only memory) under battery-free condition Download PDFInfo
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- CN111797031A CN111797031A CN202010552930.3A CN202010552930A CN111797031A CN 111797031 A CN111797031 A CN 111797031A CN 202010552930 A CN202010552930 A CN 202010552930A CN 111797031 A CN111797031 A CN 111797031A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A method for utilizing EEPROM to record task machine power-on accumulated time under the condition of no battery sets a set of recording system to finish the storage of the data, the recording system includes a processor and an EEPROM, the processor is connected with the EEPROM, and a timer for finishing the timing function is arranged in the processor; the accumulated time of the main controller power-up is recorded by the EEPROM, so that the data can be retained when the equipment is powered down. The storage strategy is completed through Ping-Pong storage operation of the EEPROM, data in the EEPROM is refreshed every 5s, a timer and an IIC interface inside the processor are matched with the EEPROM to complete a data recording function, a peripheral circuit is effectively simplified, and project cost is saved; and the Ping-Pong operation is adopted to store the power-on accumulated time, so that the power-off of the EEPROM can be ensured to successfully record the power-on accumulated time when the memory is refreshed.
Description
Technical Field
The invention relates to the technical field of storage and memory, in particular to a method for recording the power-on accumulated time of a task machine by using an EEPROM (electrically erasable programmable read-Only memory) under the condition of no battery.
Background
With the development and innovation of technology, more and more processors of the pop-up electronic device need to evaluate the service life and the failure rate. Traditional recording time device all carries small-size battery through the clock chip and accomplishes time accumulation work, however, plays core control processor circuit generally more small and exquisite, does not have great space to lay down battery and clock chip circuit, moreover, the life-span of battery generally is less than the treater life-span, can't record controller life in full cycle.
Disclosure of Invention
The present invention provides a method for recording the accumulated time of power-on of a task machine by using an EEPROM without a battery, so as to solve the above problems in the background art.
The technical problem solved by the invention is realized by adopting the following technical scheme:
a method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery comprises the following specific steps:
1) in order to record the power-on accumulated time of the missile-borne controller, a set of recording system is arranged to finish the storage of the data, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM through an internal IIC interface to finish the communication of the processor and the EEPROM, and a timer for finishing the timing function is arranged in the processor;
2) the method comprises the steps that the power-on accumulated time of a main controller is recorded through an EEPROM, so that the data can be retained under the condition of power failure of equipment, in order to avoid the situation that the data cannot be updated to the EEPROM due to sudden power failure of the EEPROM in the process of executing write operation, two addresses are adopted to store the power-on accumulated time data, the two addresses are 0x0100 of a main equipment address 0x56 and 0x0100 of a slave equipment address 0x57, and the two addresses are backed up with each other to prevent the occurrence of data loss recorded in the EEPROM due to accidental power failure of one of the two addresses;
3) according to threshold analysis of power-on accumulated time, one 32-bit data can meet requirements (more than 136 years), so that a stored value of the power-on accumulated time is stored by one 32-bit data, but only one 8-bit data can be stored in one address in the EEPROM, the 32-bit data is divided into 4 8-bit data during storage and stored in the first 4 addresses starting from 0x0100, and in order to ensure the correctness of the data, a checksum of the first 4 bytes of data is stored in the 5 th address (the checksum = byte 1+ byte 2+ byte 3+ byte 4, and if the checksum exceeds the 8-bit threshold, the lower 8 bits are taken);
4) operating the EEPROM for the first time, flashing all 5 addresses starting from 0x0100 of the master device address 0x56 to 0x00, flashing all 5 addresses starting from 0x0100 of the device address 0x57 to 0x00, setting the initial power-on accumulated time to 0, and setting the checksum to 0 (the operation is not needed subsequently);
5) the Ping-Pong operation storage is carried out by utilizing two addresses, accumulated time data stored in the address of the master device and the address of the slave device are read out firstly each time the power is on, the checksum of the accumulated time data is calculated, whether the checksum is correct or not is judged at the same time, and the numerical value is updated according to three conditions of the checksum judgment:
firstly, the checksum of two values of a master equipment address and a slave equipment address is correct, the values of the two addresses are compared, the larger value of the two addresses is taken as reference data to be updated to the two addresses;
secondly, if the master device address value checksum is correct, and the slave device address value checksum is wrong, the master device address value is used as reference data to be updated to the two addresses;
thirdly, if the master device address value checksum is wrong and the slave device address value checksum is correct, the slave device address value is used as reference data to be updated to the two addresses;
6) after the processor normally operates, refreshing the data in the EEPROM every 5s, and after the interruption of the first timing 5s occurs, adding 5s on the basis of the reference time and then flashing the data into the address of the main equipment; and after the interruption of the second time is timed for 5s, reading the data in the address of the master device, adding 5s on the basis of the data, and then writing the data into the address of the slave device, and by parity of reasoning, performing ping-pong EEPROM writing, thereby completing the recording of the power-on accumulated time of the task machine by using the EEPROM under the condition of no battery.
Has the advantages that: the invention uses the timer and IIC interface inside the processor to match with EEPROM to complete the data recording function, thus effectively simplifying peripheral circuit and saving project cost; meanwhile, the Ping-Pong address is adopted to store data, the phenomenon that the whole stored data is invalid due to power failure when the memory is refreshed is avoided, and the stability of data storage of power-on accumulated time is enhanced.
Drawings
FIG. 1 is a diagram illustrating the components of a recording system according to a preferred embodiment of the present invention.
FIG. 2 is a diagram illustrating the Ping-Pong operation time in the preferred embodiment of the present invention.
FIG. 3 is a flow chart illustrating the accumulated time of power-up of the recording processor in the preferred embodiment of the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
A method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery comprises the following specific steps:
1) in order to record the power-on accumulated time of the missile-borne controller, a set of recording system is arranged to finish the storage of the data, the composition module of the recording system is shown in fig. 1, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM through an internal IIC interface of the processor to finish the communication between the processor and the EEPROM (the EEPROM is M24M01 in model), and the timing function is finished through a timer arranged in the processor;
2) the method includes the steps that the power-on accumulated time of a main controller is recorded through an EEPROM, so that the data can be kept under the condition that the equipment is powered down, in order to avoid the situation that the data cannot be updated to the EEPROM due to sudden power failure of the EEPROM in the process of executing write operation, two addresses are used for storing the power-on accumulated time data, the two addresses are 0x0100 of a main equipment address 0x56 and 0x0100 of a slave equipment address 0x57, and the two addresses are backed up with each other to prevent the occurrence of data loss recorded in the EEPROM due to accidental power failure of one of the two addresses;
3) according to threshold analysis of power-on accumulated time, one 32-bit data can meet requirements (more than 136 years), so that a stored value of the power-on accumulated time is stored in one 32-bit data, but one address in the EEPROM can only store one 8-bit data, the 32-bit data needs to be divided into 4 8-bit data and stored in the first 4 addresses starting from 0x0100, and in order to ensure the correctness of the data, a checksum of the first 4 bytes of data is stored in the 5 th address (checksum = byte 1+ byte 2+ byte 3+ byte 4, and if the stored value exceeds the 8-bit threshold, the lower 8 bits are taken);
4) operating the EEPROM for the first time, flashing all 5 addresses starting from 0x0100 of the master device address 0x56 to 0x00, flashing all 5 addresses starting from 0x0100 of the device address 0x57 to 0x00, setting the initial power-on accumulated time to 0, and setting the checksum to 0 (the operation is not needed subsequently);
5) as shown in fig. 3, each time of power-on, the accumulated time data stored in the two addresses, namely address a and address B, is read out first, the checksum of the accumulated time data is calculated, whether the checksum is correct or not is judged at the same time, and the value is updated according to three conditions determined by the checksum:
firstly, the two numerical values of an address A and an address B are correct in checksum, the two numerical values of the address A and the address B are compared, the address A is larger than the address B, the address A is used as reference data to be updated into the two addresses, the address A is smaller than the address B, and the address B is used as reference data to be updated into the two addresses;
secondly, if the address A value is checked to be correct and the address B value is checked to be wrong, the address A value is used as reference data to be updated to the two addresses;
thirdly, if the address A value is checked to be wrong and the address B value is checked to be correct, the address B value is used as reference data to be updated to the two addresses;
6) after the processor normally operates, refreshing the data in the EEPROM every 5s, as shown in FIG. 2, after the interruption of the first timing 5s occurs, adding 5s on the basis of the reference time and then flashing to the address A; and after the interruption of the second time of 5s, reading the data in the address A, adding 5s on the basis of the data, and then flashing the data to the address B, and repeating the steps to perform ping-pong flashing of the EEPROM, thereby completing the recording of the power-on accumulated time of the task machine by using the EEPROM under the condition of no battery.
In this embodiment, the master address 0x56 is address a and the slave address 0x57 is address B.
Claims (8)
1. A method for recording the power-on accumulated time of a task machine by using an EEPROM under the condition of no battery is characterized by comprising the following specific steps:
1) in order to record the power-on accumulated time of the missile-borne controller, a set of recording system is arranged to finish the storage of the data, the recording system comprises a processor and an EEPROM, the processor is connected with the EEPROM, and a timer for finishing the timing function is arranged in the processor;
2) recording the power-on accumulated time of the main controller through the EEPROM, and in order to avoid that the data cannot be updated to the EEPROM due to sudden power failure of the EEPROM in the process of executing write operation, storing the power-on accumulated time data by adopting two addresses, wherein the two addresses are 0x0100 of a master device address 0x56 and 0x0100 of a slave device address 0x57, and the two addresses are mutually backed up;
3) according to the threshold analysis of the power-on accumulated time, one 32-bit data can meet the requirement, so the stored value of the power-on accumulated time is stored in one 32-bit data, but one address in the EEPROM can only store one 8-bit data, the 32-bit data is divided into 4 8-bit data during storage and stored in the first 4 addresses starting from 0x0100, and in order to ensure the correctness of the data, the checksum of the first 4 bytes of data is stored in the 5 th address;
4) operating the EEPROM for the first time, and initializing the power-on accumulated time of the master equipment address and the slave equipment address;
5) the Ping-Pong operation storage is carried out by utilizing the two addresses, the accumulated time data stored in the master equipment address and the slave equipment address are read out firstly each time the power is on, the checksum of the accumulated time data is calculated, whether the checksum is correct or not is judged at the same time, and then the numerical value is updated according to the result of the checksum judgment;
6) after the processor normally operates, refreshing the data in the EEPROM at the same time interval, and after the interruption of the same time of the first timing occurs, adding the same time on the basis of the reference time and then flashing the data into the address of the main equipment; and after the interruption of the same time of the second timing occurs, reading the data in the address of the master device, increasing the same time on the basis of the data, and then writing the data into the address of the slave device, and by parity of reasoning, performing ping-pong writing of the EEPROM, thereby completing the recording of the power-on accumulated time of the task machine by using the EEPROM under the condition of no battery.
2. The method for recording the accumulated time of the task machine power-on by using the EEPROM under the battery-free condition as claimed in claim 1, wherein in the step 1), the processor is connected with the EEPROM through an internal IIC interface thereof.
3. The method for recording the accumulated time of the task machine power-on by using the EEPROM under the battery-free condition as claimed in claim 1, wherein in the step 3), the checksum = byte 1+ byte 2+ byte 3+ byte 4.
4. The method as claimed in claim 1, wherein in step 3), the stored value of the accumulated power-on time is lower by 8 bits when the stored value of the accumulated power-on time exceeds the 8-bit threshold.
5. The method according to claim 1, wherein the step 4) of initializing the power-on cumulative time of the master device address and the slave device address comprises: all of the 5 addresses starting from 0x0100 of the master address 0x56 are flashed to 0x00, all of the 5 addresses starting from 0x0100 of the device address 0x57 are flashed to 0x00, the initial power-up accumulated time is 0, and the checksum is also 0.
6. The method for recording the accumulated time of the task machine on power supply by using the EEPROM in the battery-free condition as claimed in claim 1, wherein in the step 5), the value is updated according to the result of the checksum judgment, specifically as follows:
firstly, the checksum of two values of a master equipment address and a slave equipment address is correct, the values of the two addresses are compared, the larger value of the two addresses is taken as reference data to be updated to the two addresses;
secondly, if the master device address value checksum is correct, and the slave device address value checksum is wrong, the master device address value is used as reference data to be updated to the two addresses;
third, if the master address value checksum is incorrect and the slave address value checksum is correct, the slave address value is updated to the two addresses as the reference data.
7. The method for recording the accumulated time of the task machine power-on by using the EEPROM under the battery-free condition as claimed in claim 1, wherein in the step 6), the same time is 4-6 s.
8. The method as claimed in claim 7, wherein the same time is 5s, and the method for recording the accumulated time of the task machine power-on by using the EEPROM under the condition of no battery.
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