CN111796655A - Automatic frequency conversion method and system for DDR memory controller - Google Patents
Automatic frequency conversion method and system for DDR memory controller Download PDFInfo
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Abstract
The application discloses a DDR memory controller automatic frequency conversion method. Step S10: and initializing the DDR memory controller. Step S20: and the DDR memory controller calculates the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur in each frequency conversion time interval t _ interval. Step S30: and the DDR memory controller calculates a frequency conversion step length Freq _ step, a new value of a frequency conversion time interval t _ interval and a new frequency point value Freq _ new. Step S40: and the DDR memory controller adjusts the new frequency point value Freq _ new by respectively taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits. Step S50: and the DDR memory controller initiates or does not initiate hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new and updates the last frequency conversion state last _ fc. Step S60: the DDR memory controller updates the frequency conversion time interval t _ interval to its new value, and returns to step S20. The method provides a method for realizing DDR SDRAM automatic frequency conversion in a hardware mode.
Description
Technical Field
The present application relates to a Memory Controller (Memory Controller) implementation method.
Background
DDR SDRAM (Double Data Rate Synchronous Random-Access Memory) is a common type of Memory in electronic devices. The term DDR (double data rate) refers to data transfer on both the rising and falling edges of the system clock signal. A DDR memory controller (DDR memory controller) is used to drive DDR SDRAM.
The operating frequency of the DDR SDRAM has a large influence on the power consumption of the electronic device. If the frequency of the DDR SDRAM is always in a high state, the electronic device may cause resource waste and large power consumption when the electronic device is in a standby state or does not call an application program. If the frequency of the DDR SDRAM is always in a low state, the need to run the application cannot be met. Therefore, in order to optimize the system power consumption, the frequency of the DDR SDRAM needs to be converted.
The traditional DDR memory controller adopts a software frequency conversion method, software reads parameters of the DDR memory controller in a fixed time to calculate the utilization rate of DDR SDRAM, and determines whether frequency conversion is carried out or not and which frequency point is changed, and then frequency conversion is started. The method has the disadvantages that the whole frequency conversion process is long in time and needs to be repeatedly executed, the resources of a CPU are consumed, and the power consumption of a system is increased.
Disclosure of Invention
The technical problem to be solved by the application is to provide an automatic frequency conversion method for a DDR memory controller, wherein the DDR memory controller calculates the bandwidth utilization rate of a DDR SDRAM by counting the number of read-write commands and the number of clocks in a period of time. When the bandwidth utilization rate exceeds the set upper and lower thresholds, a new frequency point value of the DDR SDRAM is set, and the DDR memory controller automatically initiates the DDRSDRAM to convert the frequency to the new frequency point value.
In order to solve the above technical problem, the present application provides an automatic frequency conversion method for a DDR memory controller, which includes the following steps. Step S10: initializing a DDR memory controller, setting a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl and a minimum acquisition time interval t _ min _ itvl, and making an initial value of a variable 'frequency conversion time interval t _ interval' equal to the acquisition time interval t _ def _ itvl. Step S20: the DDR memory controller automatically counts the number rw _ command _ number and the clock number clock _ cycle of the read-write commands in each frequency conversion time interval t _ interval; and calculating the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle every time a frequency conversion time interval t _ interval passes, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0. Step S30: and the DDR memory controller calculates a frequency conversion step length Freq _ step, a new value of a frequency conversion time interval t _ interval and a new frequency point value Freq _ new. Step S40: and the DDR memory controller adjusts the new frequency point value Freq _ new by respectively taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits. Step S50: and the DDR memory controller initiates or does not initiate hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new and updates the last frequency conversion state last _ fc. Step S60: the DDR memory controller updates the frequency conversion time interval t _ interval to its new value, and returns to step S20 to start the next statistics and calculation with the new value of the frequency conversion time interval as the time period. The method provides a method for realizing DDR SDRAM automatic frequency conversion in a hardware form (DDR memory controller).
Further, in step S10, Freq _ min is not less than 0 and not more than Freq _ max < Freq _ number; wherein, Freq _ number refers to the number of frequency points supported by the DDR memory controller, and each frequency point corresponds to a different frequency. This is the condition Freq _ min and Freq _ max should preferably be met.
Further, in step S10, the frequency values corresponding to all the frequency points are arranged according to an ascending order or a descending order. This is the preferred arrangement of the frequency bins.
Further, in the step S10, u _ min [ i ] is more than 0 and less than or equal to u _ max [ i ] and less than 100, and the value of i is between 0 and Freq _ num-1. This is the condition that u _ min [ i ] and u _ max [ i ] should preferably satisfy.
Further, in step S20, when the current frequency point Freq _ cur is the frequency point i, i is greater than or equal to 0 and less than Freq _ num, and the calculation formula of u _ cal is u _ cal [ i ] = ((rw _ command _ number burst _ size)/(clock _ cycle/frequency [ i ])))/full _ bandwidth [ i ] > 100%; wherein, burst _ size is the data size of one read-write access initiated by the DDR memory controller; frequency [ i ] is the frequency of the DDR memory controller at frequency point i; full _ bandwidth [ i ] is the theoretical full bandwidth at frequency point i. An exemplary calculation of the bandwidth utilization u _ cal of the DDR SDRAM is given here.
Further, in step S30, the DDR memory controller calculates new values of the frequency conversion step size freq _ step and the frequency conversion time interval t _ interval as follows. The DDR memory controller compares the bandwidth utilization rate u _ cal of the DDRSDRAM under the current frequency point Freq _ cur with an upper utilization rate threshold u _ max [ Freq _ cur ] and a lower utilization rate threshold u _ min [ Freq _ cur ] under the current frequency point Freq _ cur. Condition one means that last _ fc is 1 and u _ cal > u _ max [ Freq _ cur ]. Condition two refers to last _ fc ═ 1 and u _ cal < u _ min [ Freq _ cur ]. Wherein last _ fc refers to the last frequency conversion state of the DDR memory controller; last _ fc is 0, which means that the DDR memory controller has no frequency conversion last time; last _ fc value is 1, which indicates that the last frequency conversion of the DDR memory controller is the frequency increase; the last _ fc value is-1, which indicates that the last frequency conversion of the DDR memory controller is down. If condition one or condition two is satisfied, then freq _ step ═ freq _ step + 1; at this time, if t _ interval/2> t _ min _ itvl is satisfied, t _ interval is t _ interval/2; if t _ interval/2> t _ min _ itvl is not satisfied, t _ interval = t _ min _ itvl. If the condition one is not met and the condition two is not met, freq _ step is 1; t _ interval ═ t _ def _ itvl. This is a preferred implementation of step S30.
Further, in step S30, the DDR memory controller calculates the new frequency bin value Freq _ new as follows. When last _ fc is-1: if u _ cal < u _ min [ Freq _ cur ], the new frequency point value Freq _ new ═ Freq _ cur-Freq _ step; if u _ cal > u _ max [ Freq _ cur ] + u _ anti _ jitter, the new frequency point value Freq _ new ═ Freq _ cur + Freq _ step; if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ] + u _ anti _ jitter, the new bin value Freq _ new ═ Freq _ cur. When last _ fc is 1: if u _ cal > u _ max [ Freq _ cur ], the new frequency point value Freq _ new ═ Freq _ cur + Freq _ step; if u _ cal < u _ min [ Freq _ cur ] -u _ anti _ jitter, the new frequency point value Freq _ new is Freq _ cur-Freq _ step; if u _ min [ Freq _ cur ] -u _ anti _ jitter ≦ u _ cal ≦ u _ max [ Freq _ cur ], the new bin value Freq _ new ═ Freq _ cur. When last _ fc is 0: if u _ cal < u _ min [ Freq _ cur ], the new frequency point value Freq _ new = Freq _ cur-Freq _ step; if u _ cal > u _ max [ Freq _ cur ], new bin value Freq _ new = Freq _ cur + Freq _ step; and if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ], the new frequency point value Freq _ new ═ Freq _ cur. Wherein u _ anti _ jitter refers to a utilization rate anti-jitter parameter of the DDR memory controller. This is a preferred implementation of step S30.
Further, u _ anti _ jitter is smaller than any u _ min [ i ] and u _ anti _ jitter + u _ max [ i ] < 100, and the value of i is between 0 and Freq _ num-1. This is the condition that u _ anti _ jitter should preferably satisfy.
Further, in the step S40, if Freq _ min ≦ Freq _ new ≦ Freq _ max, Freq _ new is not changed. If Freq _ new < Freq _ min, let Freq _ new equal Freq _ min. If Freq _ new > Freq _ max, let Freq _ new equal Freq _ max. This is a preferred implementation of step S40.
Further, in step S50, if Freq _ new > Freq _ cur, automatic frequency up-conversion is initiated, and last _ fc is made 1. If Freq _ new < Freq _ cur, then automatic down-conversion is initiated and let last _ fc = -1. If Freq _ new is Freq _ cur, then no automatic frequency conversion is initiated and let last _ fc = 0. This is a preferred implementation of step S50.
Further, if the frequency points are arranged in descending order, the frequency increasing operation is executed, and the frequency increasing operation is changed from increasing the frequency to decreasing the frequency; the down conversion operation is performed with decreasing Freq step changed to increasing Freq step. This is an alternative implementation.
The application also provides an automatic frequency conversion system of the DDR memory controller, which comprises an initialization unit, a period counting unit, a calculation unit, an adjustment unit, a frequency conversion unit and an updating unit. The initialization unit is used for initializing the DDR memory controller, setting a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl and a minimum acquisition time interval t _ min _ itvl, and making an initial value of a variable frequency conversion time interval t _ interval equal to the acquisition time interval t _ def _ itvl. The period counting unit is used for automatically counting the number rw _ command _ number and the clock number clock _ cycle of the read-write commands in each frequency conversion time interval t _ interval; and calculating the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle every time a frequency conversion time interval t _ interval passes, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0. The calculating unit is used for calculating a new value of a frequency conversion step length Freq _ step, a new frequency conversion time interval t _ interval and a new frequency point value Freq _ new. The adjusting unit is used for adjusting the new frequency point value Freq _ new by taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits respectively. The frequency conversion unit is used for initiating or not initiating hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new and updating the last frequency conversion state last _ fc. The updating unit is used for updating the frequency conversion time interval t _ interval as a new value, and the period counting unit starts the next counting and calculation by taking the new value of the frequency conversion time interval as a time period.
The technical effects achieved by the present application include the following aspects. Firstly, the automatic frequency conversion operation is independently and automatically completed by an automatic frequency conversion module (located in a DDR memory controller), the frequency conversion decision is completed without receiving control information from a CPU or other control modules, the processing time is short, and the execution overhead and the power consumption of the CPU are saved. The DDR automatic frequency conversion module is not limited to a control module or an access module, and frequency conversion control or decision is not performed by the modules, and the core of the frequency conversion decision is monitoring and calculating the flow of DDR SDRAM. The access module includes, for example, a CPU (central processing unit), a GPU (graphics processing unit), an LCD (liquid crystal display), an AI (artificial intelligence), a VPU (vision processing unit), an XM6 image, a vision processor, and other dedicated processing modules. The existing software frequency conversion method usually depends on the request of a CPU to make frequency conversion decision, needs more interaction, brings more processing delay and increases the complexity of a system. And secondly, the frequency conversion is realized flexibly, the frequency conversion can be carried out in the range of the highest frequency point and the lowest frequency point appointed by the scene, and more applicable scenes are provided. And thirdly, the automatic learning function realizes quick frequency conversion by shortening the frequency conversion time interval and increasing the frequency conversion step length. And fourthly, the anti-shake device is arranged, so that frequent shaking caused by frequency conversion back and forth is prevented. Fifthly, the implementation is simple.
Drawings
Fig. 1 is a flowchart of a method for DDR memory controller to automatically frequency convert according to the present application.
Fig. 2 is a schematic diagram of the DDR memory controller calculating new values of the frequency conversion step size and the frequency conversion time interval in step S30.
Fig. 3 is a diagram illustrating the DDR memory controller calculating the new frequency point value in step S30.
Fig. 4 is a schematic structural diagram of an automatic frequency conversion system of a DDR memory controller according to the present application.
The reference numbers in the figures illustrate: 10 is an initialization unit; 20 is a period statistic unit; 30 is a calculating unit; 40 is an adjusting unit; 50 is a frequency conversion unit; and 60 is an update unit.
Detailed Description
Referring to fig. 1, the method for DDR memory controller to automatically convert frequency provided by the present application includes the following steps.
Step S10: initializing a DDR memory controller, setting a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl and a minimum acquisition time interval t _ min _ itvl, and making an initial value of a variable 'frequency conversion time interval t _ interval' equal to the acquisition time interval t _ def _ itvl.
Wherein, Freq _ min is more than or equal to 0 and less than Freq _ max and less than Freq _ number. Freq _ number refers to the number of frequency points supported by the DDR memory controller, and each frequency point corresponds to a different frequency. For example, the DDR memory controller supports the frequency bins with Freq _ number, which are respectively referred to as frequency bin 0, frequency bin 1, … …, and frequency bin Freq _ number-1, and the frequency values corresponding to these frequency bins may be arranged in an ascending order or a descending order. For convenience of description, the frequency points are arranged in an ascending order, that is, the frequency value corresponding to the frequency point i +1 is higher than the frequency value corresponding to the frequency point i. As an example, the lowest frequency bin Freq _ min is, for example, frequency bin 0, and the highest frequency bin Freq _ max is, for example, frequency bin Freq _ number-1.
Wherein, u _ max [ i ] and u _ min [ i ] respectively represent an upper threshold of the utilization rate of the frequency point i and a lower threshold of the utilization rate of the frequency point i. U _ min [ i ] is more than 0 and less than or equal to u _ max [ i ] and less than 100, and the value of i is between 0 and Freq _ num-1.
Step S20: enabling the DDR memory controller to have an automatic frequency conversion function, and enabling the DDR memory controller to automatically count the number rw _ command _ number of read-write commands and the number clock _ cycle of clocks in each frequency conversion time interval t _ interval. And calculating the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle every time a frequency conversion time interval t _ interval passes, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0.
According to the theoretical full bandwidth (provided by manufacturers) of the DDR SDRAM under different frequency points, the theoretical full bandwidth corresponding to the frequency point i (i is more than or equal to 0 and less than Freq _ num) is full _ bandwidth [ i ], and when the current frequency point Freq _ cur is the frequency point i, the calculation formula of u _ cal is as follows: u _ cal [ i ] = ((rw _ command _ number _ burst _ size)/(clock _ cycle/frequency [ i ]))/full _ bandwidth [ i ] + 100%. The burst _ size is the data size of a single read-write access initiated by the DDR memory controller, and the unit is byte, and the burst _ size can be set by the DDR memory controller, and will not change dynamically during use, nor change according to different frequency points. frequency [ i ] is the frequency of the DDR memory controller at frequency point i. The frequency points are different, and the frequency of the corresponding DDR memory controller is also different. The frequency of DDR memory controllers with the same frequency point is the same. The percentage data is obtained by multiplying by 100%.
Step S30: and the DDR memory controller calculates a frequency conversion step length Freq _ step, a new value of a frequency conversion time interval t _ interval and a new frequency point value Freq _ new.
A first part: referring to fig. 2, the DDR memory controller calculates new values of the frequency conversion step size freq _ step and the frequency conversion time interval t _ interval. The default value of the frequency conversion step length freq _ step of the DDR memory controller is 1, namely, one frequency point is increased when the frequency is increased (for example, the frequency point is increased to the frequency point i + 1) and one frequency point is decreased when the frequency is decreased (for example, the frequency point i is decreased to the frequency point i-1).
The DDR memory controller compares the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur with an upper utilization rate threshold u _ max [ Freq _ cur ] and a lower utilization rate threshold u _ min [ Freq _ cur ] under the current frequency point Freq _ cur.
Condition one means that last _ fc is 1 and u _ cal > u _ max [ Freq _ cur ].
Condition two refers to last _ fc ═ 1 and u _ cal < u _ min [ Freq _ cur ].
Wherein last _ fc is the last frequency conversion state of the DDR memory controller, and the default value is 0. last _ fc is 0, which means that the DDR memory controller has no frequency conversion last time; last _ fc value is 1, which indicates that the last frequency conversion of the DDR memory controller is the frequency increase; the last _ fc value is-1, which indicates that the last frequency conversion of the DDR memory controller is down.
If condition one or condition two is satisfied, then freq _ step ═ freq _ step + 1; this indicates an increase in the frequency conversion step size. At this time, if t _ interval/2> t _ min _ itvl is satisfied, t _ interval is t _ interval/2; this means that the frequency conversion time interval is shortened. If t _ interval/2> t _ min _ itvl is not satisfied, t _ interval = t _ min _ itvl; this means that the frequency conversion time interval is kept constant.
When the condition one is met, the last frequency conversion of the DDR memory controller is the frequency boosting, the bandwidth utilization rate of the DDR SDRAM in the current frequency conversion interval time is higher than the utilization rate upper threshold set by the current frequency point, and the frequency should be boosted again; the decision is to increase the frequency conversion step length, and the new value of the frequency conversion time interval is shortened or kept unchanged, so that the purpose of accelerating the frequency increase is achieved.
When the second condition is met, the last frequency conversion of the DDR memory controller is frequency reduction, and the bandwidth utilization rate of the DDR SDRAM in the current frequency conversion interval time is lower than the lower utilization rate threshold set by the current frequency point, and the frequency reduction should be carried out again; the decision is to increase the frequency conversion step length, and the new value of the frequency conversion time interval is shortened or kept unchanged, so that the purpose of accelerating the frequency reduction is achieved.
If the condition one is not met and the condition two is not met, freq _ step is 1; this indicates that the frequency conversion step size is restored to the default value. Meanwhile, t _ interval is t _ def _ itvl; this indicates that the variable frequency time interval has returned to its original value.
And if the conditions I and II are not met, the frequency conversion trends of the DDR memory controller in the last frequency conversion interval time and the current frequency conversion interval time are different, or the current frequency point of the DDR SDRAM can meet the system requirement, and the frequency conversion is not required to be accelerated. Therefore, the frequency conversion step length is recovered to the default value, and the new value of the frequency conversion time interval is set as the initial value.
A second part: referring to fig. 3, the DDR memory controller calculates a new bin value Freq _ new.
If last _ fc ═ 1 holds: if u _ cal < u _ min [ Freq _ cur ], which indicates that the bandwidth utilization rate of the DDR SDRAM in the current sampling period (namely the frequency conversion time interval) is lower than the lower utilization rate threshold set by the current frequency point, the frequency point is lowered, a new frequency point value Freq _ new is set to be Freq _ cur-Freq _ step, and the step size of lowering the new frequency point is the Freq _ step calculated by the first part; if u _ cal > u _ max [ Freq _ cur ] + u _ anti _ jitter indicates that the bandwidth utilization rate of the DDR SDRAM in the current sampling period is higher than the sum of the utilization rate upper threshold and the utilization rate anti-jitter parameter set by the current frequency point, and the frequency should be increased, preparing to increase the frequency point, setting a new frequency point value Freq _ new as Freq _ cur + Freq _ step, and setting the increasing step length of the new frequency point as the Freq _ step calculated by the first part; if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ] + u _ anti _ jitter indicates that the bandwidth utilization rate of the DDR SDRAM in the current sampling period is between the sum of the utilization rate lower threshold, the utilization rate upper threshold and the utilization rate anti-jitter parameter of the current frequency point, and the current frequency point of the DDR SDRAM meets the system requirement, frequency conversion is not performed, and a new frequency point value Freq _ new ═ Freq _ cur is set. After the execution is completed, the process proceeds to step S40.
If last _ fc ═ 1 holds: if u _ cal > u _ max [ Freq _ cur ], the bandwidth utilization rate of the DDR SDRAM in the current sampling period is higher than the utilization rate upper threshold set by the current frequency point, and the frequency point is to be increased, a new frequency point value Freq _ new is set to be Freq _ cur + Freq _ step, and the increasing step size of the new frequency point is Freq _ step calculated by the first part; if u _ cal < u _ min [ Freq _ cur ] -u _ anti _ jitter indicates that the bandwidth utilization rate of the DDRSDRAM in the current sampling period is lower than the difference between the utilization rate lower threshold set by the current frequency point and the utilization rate anti-jitter parameter, and the frequency should be reduced, preparing to reduce the frequency point, setting a new frequency point value Freq _ new as Freq _ cur-Freq _ step, and setting the reduction step size of the new frequency point as the Freq _ step calculated by the first part; if u _ min [ Freq _ cur ] -u _ anti _ jitter is less than or equal to u _ cal and less than or equal to u _ max [ Freq _ cur ], the bandwidth utilization rate of the DDR SDRAM in the current sampling period is between the utilization rate lower threshold, the utilization rate anti-jitter parameter difference and the utilization rate upper threshold of the current frequency point, and the current frequency point meets the requirement, frequency conversion is not prepared, and a new frequency point value Freq _ new is set as Freq _ cur. After the execution is completed, the process proceeds to step S40.
If last _ fc ═ 0 holds: if u _ cal < u _ min [ Freq _ cur ], which indicates that the bandwidth utilization rate of the DDR SDRAM in the current sampling period is lower than the lower utilization rate threshold set by the current frequency point, the frequency point is prepared to be reduced, a new frequency point value Freq _ new = Freq _ cur-Freq _ step is set, and the step length for reducing the new frequency point is the Freq _ step calculated by the first part; if u _ cal > u _ max [ Freq _ cur ], which indicates that the bandwidth utilization rate of the DDR SDRAM in the current sampling period is higher than the upper utilization rate threshold set by the current frequency point, and the frequency point is to be increased, a new frequency point value Freq _ new = Freq _ cur + Freq _ step is set, and the increasing step size of the new frequency point is the Freq _ step calculated by the first part; if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ], the bandwidth utilization rate of the DDR SDRAM in the current sampling period is between the lower utilization rate threshold and the upper utilization rate threshold of the current frequency point, and the current frequency point meets the requirement, frequency conversion is not performed, and a new frequency point value Freq _ new ═ Freq _ cur is set. After the execution is completed, the process proceeds to step S40.
Wherein u _ anti _ jitter refers to a utilization rate anti-jitter parameter of the DDR memory controller, and satisfies that u _ anti _ jitter is smaller than any u _ min [ i ] and u _ anti _ jitter + u _ max [ i ] < 100, and the value of i is between 0 and Freq _ num-1. The u _ anti _ jitter parameter has the meaning of preventing the DDR SDRAM from frequency translating too frequently, i.e. from jitter.
Step S40: and the DDR memory controller adjusts the new frequency point value Freq _ new by respectively taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits.
If Freq _ min is less than or equal to Freq _ new is less than or equal to Freq _ max, then Freq _ new is unchanged.
If Freq _ new < Freq _ min, let Freq _ new equal Freq _ min.
If Freq _ new > Freq _ max, let Freq _ new equal Freq _ max.
Step S50: and the DDR memory controller initiates or does not initiate hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new and updates the last frequency conversion state last _ fc.
If Freq _ new > Freq _ cur, then auto-upscaling is initiated and let last _ fc be 1. After the frequency conversion is completed, the process proceeds to step S60.
If Freq _ new < Freq _ cur, then automatic down-conversion is initiated and let last _ fc = -1. After the frequency conversion is completed, the process proceeds to step S60.
If Freq _ new ═ Freq _ cur, then no automatic frequency conversion is initiated and let last _ fc = 0, jump to step S60.
Step S60: the DDR memory controller updates the frequency conversion time interval t _ interval to its new value, and returns to step S20 to start the next statistics and calculation with the new value of the frequency conversion time interval as the time period. Wherein the new value of the frequency conversion time interval t _ interval is calculated in step S30.
In each step, if the frequency points are arranged in a descending order, namely the frequency corresponding to the frequency point i +1 is lower than the frequency corresponding to the frequency point i, the frequency increasing operation is executed by changing + Freq _ step into-Freq _ step; the down conversion operation should be performed with-Freq step changed to + Freq step.
Referring to fig. 4, the system for DDR memory controller to automatically convert frequency includes an initialization unit 10, a period counting unit 20, a calculating unit 30, an adjusting unit 40, a frequency converting unit 50 and an updating unit 60.
The initialization unit 10 is configured to initialize a DDR memory controller, set a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl, and a minimum acquisition time interval t _ min _ itvl, and make an initial value of a variable "frequency conversion time interval t _ interval" equal to the acquisition time interval t _ def _ itvl.
The period counting unit 20 is used for automatically counting the number rw _ command _ number and the clock number clock _ cycle of the read/write commands in each variable frequency time interval t _ interval. And calculating the bandwidth utilization rate u _ cal of the DDRSDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle every time a frequency conversion time interval t _ interval passes, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0.
The calculating unit 30 is configured to calculate a new value of the frequency conversion step length Freq _ step, the frequency conversion time interval t _ interval, and a new frequency point value Freq _ new.
The adjusting unit 40 is configured to adjust the new frequency point value Freq _ new by using the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits, respectively.
The frequency conversion unit 50 is used for initiating or not initiating hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new, and updating the last frequency conversion state last _ fc.
The updating unit 60 is used to update the frequency conversion time interval t _ interval to its new value, and return to the period counting unit 20 to start counting and calculating the next time period with the new value of the frequency conversion time interval.
According to the method and the device, the DDR memory controller is used for finishing the automatic frequency conversion of the DDR SDRAM according to the preset frequency conversion parameters, software is not needed, the utilization rate of the DDR SDRAM is monitored by hardware in real time, therefore, the expense and time for CPU to execute software calculation are saved, and the frequency conversion time is shortened. In addition, according to the method and the device, automatic frequency conversion of hardware in a frequency point range required in a specific scene can be ensured according to the preset lowest frequency point and the preset highest frequency point; through learning frequency conversion historical records, the values of frequency conversion time intervals and frequency conversion step lengths are automatically adjusted, and rapid frequency conversion to appropriate frequency points is realized; through learning frequency conversion historical records and setting of utilization ratio anti-jitter parameters, frequency conversion jitter and the like are prevented, and stable frequency conversion is achieved.
The above are merely preferred embodiments of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A DDR memory controller automatic frequency conversion method, its characteristic is, including the following steps;
step S10: initializing a DDR memory controller, setting a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl and a minimum acquisition time interval t _ min _ itvl, and making an initial value of a variable 'frequency conversion time interval t _ interval' equal to the acquisition time interval t _ def _ itvl;
step S20: the DDR memory controller automatically counts the number rw _ command _ number and the clock number clock _ cycle of the read-write commands in each frequency conversion time interval t _ interval; every time a frequency conversion time interval t _ interval passes, calculating the bandwidth utilization rate u _ cal of the DDRSDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0;
step S30: the DDR memory controller calculates a frequency conversion step length Freq _ step, a new value of a frequency conversion time interval t _ interval and a new frequency point value Freq _ new;
step S40: the DDR memory controller adjusts the new frequency point value Freq _ new by taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits respectively;
step S50: the DDR memory controller initiates or does not initiate hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new, and updates the last frequency conversion state last _ fc;
step S60: the DDR memory controller updates the frequency conversion time interval t _ interval to its new value, and returns to step S20 to start the next statistics and calculation with the new value of the frequency conversion time interval as the time period.
2. The DDR memory controller auto-frequency conversion method as claimed in claim 1, wherein in step S10, 0 ≦ Freq _ min ≦ Freq _ max < Freq _ number; wherein, Freq _ number refers to the number of frequency points supported by the DDR memory controller, and each frequency point corresponds to a different frequency.
3. The method of claim 2, wherein in step S10, the frequency values corresponding to all the frequency points are arranged in ascending or descending order.
4. The method as claimed in claim 2, wherein in step S10, u _ min [ i ] is 0 to u _ max [ i ] < 100, and i is between 0 and Freq _ num-1.
5. The method of claim 2, wherein in step S20, when the current frequency bin Freq _ cur is frequency bin i, 0 ≦ i < Freq _ num, and the calculation formula of u _ cal is u _ cal [ i ] = ((rw _ command _ number ≦ burst _ size)/(clock _ cycle/frequency [ i ]))/full _ bandwidth [ i ] + 100%; wherein, burst _ size is the data size of one read-write access initiated by the DDR memory controller; frequency [ i ] is the frequency of the DDR memory controller at frequency point i; full _ bandwidth [ i ] is the theoretical full bandwidth at frequency point i.
6. The method as claimed in claim 2, wherein in step S30, the DDR memory controller calculates new values of frequency conversion step size freq _ step and frequency conversion time interval t _ interval as follows;
the DDR memory controller compares the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur with an upper utilization rate threshold u _ max [ Freq _ cur ] and a lower utilization rate threshold u _ min [ Freq _ cur ] under the current frequency point Freq _ cur;
condition one means that last _ fc is 1 and u _ cal > u _ max [ Freq _ cur ];
condition two means that last _ fc ═ 1 and u _ cal < u _ min [ Freq _ cur ];
wherein last _ fc refers to the last frequency conversion state of the DDR memory controller; last _ fc is 0, which means that the DDR memory controller has no frequency conversion last time; last _ fc value is 1, which indicates that the last frequency conversion of the DDR memory controller is the frequency increase; last _ fc value is-1, which indicates that the last frequency conversion of the DDR memory controller is frequency reduction;
if condition one or condition two is satisfied, then freq _ step ═ freq _ step + 1; at this time, if t _ interval/2> t _ min _ itvl is satisfied, t _ interval is t _ interval/2; if t _ interval/2> t _ min _ itvl is not satisfied, t _ interval = t _ min _ itvl;
if the condition one is not met and the condition two is not met, freq _ step is 1; t _ interval ═ t _ def _ itvl.
7. The method for automatically frequency converting of DDR memory controller as claimed in claim 6, wherein in step S30, the DDR memory controller calculates the new frequency point value Freq _ new using the following method;
when last _ fc is-1: if u _ cal < u _ min [ Freq _ cur ], the new frequency point value Freq _ new ═ Freq _ cur-Freq _ step; if u _ cal > u _ max [ Freq _ cur ] + u _ anti _ jitter, the new frequency point value Freq _ new ═ Freq _ cur + Freq _ step; if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ] + u _ anti _ jitter, the new frequency bin value Freq _ new ═ Freq _ cur;
when last _ fc is 1: if u _ cal > u _ max [ Freq _ cur ], the new frequency point value Freq _ new ═ Freq _ cur + Freq _ step; if u _ cal < u _ min [ Freq _ cur ] -u _ anti _ jitter, the new frequency point value Freq _ new is Freq _ cur-Freq _ step; if u _ min [ Freq _ cur ] -u _ anti _ jitter ≦ u _ cal ≦ u _ max [ Freq _ cur ], the new bin value Freq _ new ═ Freq _ cur;
when last _ fc is 0: if u _ cal < u _ min [ Freq _ cur ], the new frequency point value Freq _ new = Freq _ cur-Freq _ step; if u _ cal > u _ max [ Freq _ cur ], new bin value Freq _ new = Freq _ cur + Freq _ step; if u _ min [ Freq _ cur ] ≦ u _ cal ≦ u _ max [ Freq _ cur ], the new frequency bin value Freq _ new ═ Freq _ cur;
wherein u _ anti _ jitter refers to a utilization rate anti-jitter parameter of the DDR memory controller.
8. The DDR memory controller auto-frequency conversion method of claim 7, wherein u _ anti _ jitter is less than any u _ min [ i ] and u _ anti _ jitter + u _ max [ i ] < 100, i is between 0 and Freq _ num-1.
9. The DDR memory controller auto-frequency conversion method of claim 1, wherein in step S40, if Freq _ min ≦ Freq _ new ≦ Freq _ max, Freq _ new is not changed;
if Freq _ new is less than Freq _ min, then let Freq _ new be Freq _ min;
if Freq _ new > Freq _ max, let Freq _ new equal Freq _ max.
10. The method for DDR memory controller to automatically frequency convert as claimed in claim 1, wherein in step S50, if Freq _ new > Freq _ cur, then initiate an automatic frequency up conversion, and let last _ fc be 1;
if Freq _ new is less than Freq _ cur, initiating automatic frequency reduction, and enabling last _ fc = -1;
if Freq _ new is Freq _ cur, then no automatic frequency conversion is initiated and let last _ fc = 0.
11. The DDR memory controller automatic frequency conversion method as claimed in claim 6 or 7, wherein if the frequency points are arranged in descending order, then when the frequency increasing operation is executed, the Freq _ step is changed to be decreased; the down conversion operation is performed with decreasing Freq step changed to increasing Freq step.
12. A DDR memory controller automatic frequency conversion system is characterized by comprising an initialization unit, a period counting unit, a calculating unit, an adjusting unit, a frequency conversion unit and an updating unit;
the initialization unit is used for initializing the DDR memory controller, setting a highest frequency point Freq _ max, a lowest frequency point Freq _ min, an upper utilization threshold u _ max [ i ] of each frequency point, a lower utilization threshold u _ min [ i ] of each frequency point, an acquisition time interval t _ def _ itvl and a minimum acquisition time interval t _ min _ itvl, and making an initial value of a variable frequency conversion time interval t _ interval equal to the acquisition time interval t _ def _ itvl;
the period counting unit is used for automatically counting the number rw _ command _ number and the clock number clock _ cycle of the read-write commands in each frequency conversion time interval t _ interval; every time a frequency conversion time interval t _ interval passes, calculating the bandwidth utilization rate u _ cal of the DDR SDRAM under the current frequency point Freq _ cur by using the read-write command number rw _ command _ number and the clock number clock _ cycle, and simultaneously recovering the read-write command number rw _ command _ number and the clock number clock _ cycle to a default value of 0;
the calculating unit is used for calculating a new value of a frequency conversion step length Freq _ step, a new frequency conversion time interval t _ interval and a new frequency point value Freq _ new;
the adjusting unit is used for adjusting the new frequency point value Freq _ new by respectively taking the highest frequency point Freq _ max and the lowest frequency point Freq _ min as upper and lower limits;
the frequency conversion unit is used for initiating or not initiating hardware frequency conversion to the DDR SDRAM according to the new frequency point value Freq _ new and updating the last frequency conversion state last _ fc;
the updating unit is used for updating the frequency conversion time interval t _ interval as a new value, and the period counting unit starts the next counting and calculation by taking the new value of the frequency conversion time interval as a time period.
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