CN111785717A - SCR electrostatic protection structure and method of forming the same - Google Patents

Abstract

An SCR electrostatic protection structure and a method for forming the same, the structure includes: a first unit and a second unit; the first unit includes: a first P-type doped region located at the top of a first N-type well; located in the first P-type well The first N-type doped region at the top of the middle; the second unit includes: a second P-type doped region and a third N-type doped region located at the top of the second N-type well; the top of the second P-type well The second N-type doping region and the third P-type doping region; the bridge doping group; the bridge doping group includes: a plurality of fourth P-type doping regions arranged along the second direction, each fourth P-type doping region The impurity region is located at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; the fourth N-type between adjacent fourth P-type doped regions Doping region; a conductive structure electrically connecting the fourth N-type doping region and the fourth P-type doping region. The performance of the SCR electrostatic protection structure is improved.

Description

SCR electrostatic protection structure and method of forming the same

technical field

The invention relates to the field of electrostatic protection, in particular to an SCR electrostatic protection structure and a method for forming the same.

Background technique

In the production and application of integrated circuit chips, with the continuous improvement of VLSI process technology, the current CMOS integrated circuit manufacturing technology has entered the deep sub-micron stage, the size of MOS devices is continuously reduced, and the thickness of the gate oxide layer increases. Thinner and thinner, the withstand voltage capability of MOS devices is significantly reduced, and the harm of electrostatic discharge (Electrostatic Discharge, ESD) to integrated circuits becomes more and more significant. Therefore, ESD protection of integrated circuits becomes particularly important.

In order to strengthen the protection against static electricity, an electrostatic protection circuit is usually connected to the input and output interface (I/O pad) of the chip. The electrostatic protection circuit is a discharge path for the internal circuit in the chip to provide electrostatic current, so as to prevent static electricity from damaging the inside of the chip. circuit breakdown.

However, the performance of the existing electrostatic protection structures is poor.

SUMMARY OF THE INVENTION

The problem solved by the present invention is to provide an SCR electrostatic protection structure and a method for forming the same, so as to improve the performance of the SCR electrostatic protection structure.

In order to solve the above problems, the present invention provides an SCR electrostatic protection structure, comprising: a semiconductor substrate; a first unit and a second unit separated in the semiconductor substrate; the first unit includes: a first N unit in the semiconductor substrate type well and first P-type well, the first P-type well is located at the side of the first N-type well along the first direction and is adjacent to the first N-type well; the first P-type well located at the top of the first N-type well is doped region; a first N-type doped region located at the top of the first P-type well; the second unit includes: a second N-type well and a second P-type well located in the semiconductor substrate, and the second P-type well is located along the first The direction is located at the side of the second N-type well and is adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are located at the top of the second N-type well and are separated from each other; located in the second P-type well A second N-type doped region and a third P-type doped region that are separated from each other at the top of the well; bridge the doping group; for the adjacent first and second cells, the first N-type doped region, The second P-type doped region and the third N-type doped region are electrically connected; the bridge doping group includes: a plurality of discrete fourth P-type doped regions arranged along the second direction, each fourth P-type doped region The impurity region is located at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; it is located between adjacent fourth P-type doped regions and is connected to the fourth A fourth N-type doped region adjacent to the P-type doped region, the fourth N-type doped region is located at the top of a part of the second N-type well and extends to the top of a part of the second P-type well; located on the semiconductor substrate The conductive structure is electrically connected to the fourth N-type doped region and the fourth P-type doped region.

Optionally, the number of the second unit is one; both the second N-type doped region and the third P-type doped region are connected to the cathode potential.

Optionally, the number of the second units is multiple; the multiple second units are respectively the first-level second unit to the Q-th level second unit, where Q is an integer greater than or equal to 2; the i-th level second unit The second N-type doped region and the third P-type doped region are electrically connected to the second P-type doped region and the third N-type doped region in the i+1th level second unit, i is greater than or equal to 1 and an integer less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the second unit of the Q-th stage are connected to the cathode potential, and the first N-type doped region and the first-level second The second P-type doped region and the third N-type doped region in the cell are electrically connected.

Optionally, the first P-type doped region is connected to an anode potential.

Optionally, the first unit further includes: a fifth N-type doped region located at the top of the first N-type well, the fifth N-type doped region and the first P-type doped region are separated from each other, and the fifth N-type doped region is separated from the first P-type doped region. The N-type doped region is electrically connected to the first P-type doped region.

Optionally, the first unit further includes: a fifth P-type doping region located at the top of the first P-type well, the fifth P-type doping region and the first N-type doping region are separated from each other, and the fifth P-type doping region is separated from the first N-type doping region. The P-type doped region is electrically connected to the first N-type doped region.

Optionally, the first unit further includes: a first isolation group layer located in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located in part of the first The top in the N-type well and extending to part of the top in the first P-type well.

Optionally, the first isolation group layer includes a sixth P-type doped region and a first isolation insulating layer respectively located on both sides of the sixth P-type doped region along the first direction, and the sixth P-type doped region is located in the A portion of the top portion of the first N-type well extends to a portion of the top portion of the first P-type well, the first isolation insulating layer on one side of the sixth P-type doped region is located in the first N-type well, and the sixth P-type doped region The first isolation insulating layer on the other side of the impurity region is located in the first P-type well.

Optionally, the first isolation group layer has a single-layer structure, and the material of the first isolation group layer includes silicon oxide.

Optionally, the first unit further includes: a first side isolation well located in the semiconductor substrate, the first side isolation well is located at the side of the first P-type well along the first direction and is adjacent to the first P-type well, The first P-type well is located between the first side isolation well and the first N-type well, and the conductivity type of the first side isolation well is N-type; the first bottom isolation well, the first bottom isolation well is located between the first P-type well The bottom is adjacent to the first P-type well, the first bottom isolation well is also connected to the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is N-type.

Optionally, the second unit further includes: a second side isolation well located in the semiconductor substrate, the second side isolation well is located at the side of the second P-type well along the first direction and is adjacent to the second P-type well, The second P-type well is located between the second side isolation well and the second N-type well, and the conductivity type of the second side isolation well is N-type; the second bottom isolation well, the second bottom isolation well is located between the second P-type well The bottom is adjacent to the second P-type well, the second bottom isolation well is also connected to the bottom of the second N-type well and the bottom of the second side isolation well, and the conductivity type of the second bottom isolation well is N-type.

Optionally, it further includes: a seventh P-type doped region located at the top of part of the semiconductor substrate, and the seventh P-type doped region is respectively located between the adjacent first unit and second unit, and the seventh P-type doped region On both sides of the two units along the first direction, each seventh P-type doped region is grounded.

Optionally, the conductive structure is located on the surface of the fourth N-type doping region and extends to the surface of the fourth P-type doping region; the material of the conductive structure is metal silicide.

Optionally, the semiconductor substrate has substrate trap ions, and the conductivity type of the substrate trap ions is P-type.

The present invention also provides a method for forming any one of the above-mentioned SCR electrostatic protection structures, including: providing a semiconductor substrate; forming a discrete first unit and a second unit in the semiconductor substrate; the method for forming the first unit includes: forming a first unit on the semiconductor substrate A first N-type well is formed in the bottom; a first P-type well adjacent to the first N-type well is formed at the side of the first N-type well along the first direction; a first P-type well is formed at the top of the first N-type well A first N-type doped region is formed on top of the first P-type well; the method for forming a second unit includes: forming a second N-type well in a semiconductor substrate; along the edge of the second N-type well A second P-type well adjacent to the second N-type well is formed on the side in the first direction; a second P-type doped region and a third N-type doped region that are separated from each other are formed on the top of the second N-type well; Forming a second N-type doped region and a third P-type doped region separate from each other on top of the second P-type well; forming a bridge doping group; for adjacent first and second cells, the first The N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected; the method of forming the bridging doping group includes: forming a plurality of discrete fourth P-type doped regions arranged along the second direction Doping regions, each fourth P-type doping region is located at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is perpendicular to the first direction; in the adjacent fourth P-type well A fourth N-type doped region adjacent to the fourth P-type doped region is formed between the doped regions, and the fourth N-type doped region is located at the top of part of the second N-type well and extends to part of the second P-type doped region The top in the well; a conductive structure is formed on the semiconductor substrate, and the conductive structure is electrically connected to the fourth N-type doped region and the fourth P-type doped region.

Optionally, the method for forming the first unit further includes: forming a fifth N-type doped region located at the top of the first N-type well, and the fifth N-type doped region and the first P-type doped region are separated from each other , and the fifth N-type doped region is electrically connected to the first P-type doped region; a fifth P-type doped region located at the top of the first P-type well is formed, and the fifth P-type doped region is connected to the first N-type doped region. The doping regions are separated from each other, and the fifth P-type doping region is electrically connected to the first N-type doping region.

Optionally, the method for forming the first unit further includes: forming a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located in the semiconductor substrate. A portion of the top portion of the first N-type well and extending to a portion of the top portion of the first P-type well.

Optionally, the method for forming the first unit further includes: before forming the first P-type doped region and the first N-type doped region, forming a first side isolation well and a first bottom isolation in the semiconductor substrate well, the first side isolation well is located at the side of the first P-type well along the first direction and is adjacent to the first P-type well, the first P-type well is located between the first side isolation well and the first N-type well, the first The bottom isolation well is located at the bottom of the first P-type well and is adjacent to the first P-type well. The first bottom isolation well is also connected to the bottom of the first N-type well and the bottom of the first side isolation well respectively. The first side isolation well The conductivity types of the first bottom isolation well and the first bottom isolation well are both N-type.

Optionally, the method for forming the second unit further includes: before forming the second P-type doped region, the second N-type doped region, the third N-type doped region and the third P-type doped region, A second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located at the side of the second P-type well along the first direction and is adjacent to the second P-type well, and the second P-type well is located in Between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is adjacent to the second P-type well, and the second bottom isolation well is also respectively connected to the second N-type well. The bottom is connected to the bottom of the second side isolation well, and the conductivity types of the second side isolation well and the second bottom isolation well are both N type.

Optionally, it further includes: forming a seventh P-type doped region on the top of part of the semiconductor substrate, and the seventh P-type doped region is respectively located between adjacent first units and second units, and On both sides of the second unit along the first direction, each seventh P-type doped region is grounded.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the SCR electrostatic protection structure provided by the technical solution of the present invention, the SCR electrostatic protection structure includes a first current discharge structure and a second current discharge structure. The first current discharge structure is a PNPN structure, the first current discharge structure includes a first PNP tube and a first NPN tube, the first P-type doped region is used as the emitter of the first PNP tube, and the first P-type doped region The first N-type well at the bottom is used as the base of the first PNP transistor, the first P-type well at the bottom of the first N-type doped region is used as the collector of the first PNP transistor, and the first P-type well at the bottom of the first P-type doped region is used as the collector of the first PNP transistor. The N-type well is used as the collector of the first NPN tube, the first P-type well at the bottom of the first N-type doped region is used as the base of the first NPN tube, and the first N-type doped region is used as the emitter of the first NPN tube . The second current bleeder structure is a PNPN structure, the second current bleeder structure includes a second PNP transistor and a second NPN transistor, the second P-type doped region is used as the emitter of the second PNP transistor, and the second P-type doped region The second N-type well at the bottom is used as the base of the second PNP transistor, the second P-type well at the bottom of the second N-type doped region is used as the collector of the second PNP transistor, and the second P-type well at the bottom of the second P-type doped region is used as the collector of the second PNP transistor. The N-type well is used as the collector of the second NPN transistor, the second P-type well at the bottom of the second N-type doped region is used as the base of the second NPN transistor, and the second N-type doped region is used as the emitter of the second NPN transistor . The second current discharge structures in the second units of each stage are connected in series. The SCR electrostatic protection structure further includes a resistive conducting structure, and the resistive conducting structure includes: a third N-type doped region, a second N-type well, a bridge doping group, a second P-type well and a third P-type doped region . The first current discharge path corresponds to the first current discharge structure, and the second current discharge path corresponds to the second current discharge structure. The resistive conducting structure has a resistive conducting path, and the resistive conducting path includes: from the third N-type doping region to the second N-type well, and from the second N-type well to the fourth N-type doping in the bridge doping group Impurity region, from the fourth N-type doped region through the conductive structure to the fourth P-type doped region, from the fourth P-type doped region to the second P-type well, from the second P-type well to the third P-type doped region Miscellaneous area. The resistance diversion paths in the second units of each stage are connected in series. Since the first current discharge path and the second current discharge path are superimposed in series, the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the holding voltage of the first current discharge structure and the second current discharge structure. Therefore, the holding voltage of the SCR electrostatic protection structure is increased. Since the holding voltage of the SCR electrostatic protection structure is increased, the normal operating voltage range of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure. A trigger voltage is applied to the cathode and the anode. In the initial stage, the second current discharge path in the second unit is not conducting, the resistance conducting structure in the second unit is conducting, and the voltage drop on the second unit is small. At this time, most of the trigger voltage is applied to the first cell, and most of the trigger voltage is applied to the first cell to make the first current bleeder path in the first cell conduct, thus triggering the first current bleeder The path discharges current, and subsequently, the conduction of the first current discharge path triggers the conduction of the second current discharge path, thus triggering the first current discharge path to discharge current. In this way, the trigger voltage required for the conduction of the first current discharge path in the SCR electrostatic protection structure to trigger the conduction of the second current discharge path is reduced. In conclusion, the performance of the SCR electrostatic protection structure is improved.

Description of drawings

1 to 4 are schematic structural diagrams of a process of forming an SCR electrostatic protection structure according to an embodiment of the present invention.

Detailed ways

As mentioned in the background, semiconductor devices formed by the prior art have poor performance.

There are two important parameters in the SCR electrostatic protection structure, namely the holding voltage and the trigger voltage. Higher holding voltage and lower trigger voltage are the technological directions that the SCR electrostatic protection structure is constantly pursuing.

The existing SCR electrostatic protection structure includes: a P-type semiconductor substrate; an SCR unit located in the semiconductor substrate; the SCR unit includes: a first N-type well located in the semiconductor substrate; a first N-type well located in the first N-type well P-type well, the first P-type well is located on the side of the first N-type well and is adjacent to the first N-type well; the second N-type well surrounding the first P-type well and the first N-type well; Located in the first N-type well P-type doped region at the top in the first P-type well; N-type doped region at the top of the first P-type well.

In order to increase the holding voltage of the SCR electrostatic protection structure, usually the SCR electrostatic protection structure has multiple SCR units, and the multiple SCR units are connected in series. is an integer greater than or equal to 2, the N-type doped region in the j-th SCR unit is electrically connected to the P-type doped region in the j+1-th SCR unit, and j is an integer greater than or equal to 1 and less than or equal to W-1 , the P-type doped region in the first-level SCR unit is connected to the anode potential, and the N-type doped region in the W-th level SCR unit is connected to the cathode potential.

However, the above structure will increase the trigger voltage of the SCR electrostatic protection structure while increasing the holding voltage.

On this basis, the present invention provides an SCR electrostatic protection structure, including: a first unit and a second unit located in a semiconductor substrate; the first unit includes: a first N-type well located in the semiconductor substrate and a first unit P-type well, the first P-type well is located at the side of the first N-type well along the first direction and is adjacent to the first N-type well; the first P-type doped region located at the top of the first N-type well; located in the first N-type well The first N-type doped region at the top in the P-type well; the second unit includes: a second N-type well and a second P-type well located in the semiconductor substrate, and the second P-type well is located in the second N-type well along the first direction The side part of the type well is adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are located at the top of the second N-type well and are separated from each other; are located at the top of the second P-type well and are separated from each other. The second N-type doped region and the third P-type doped region are separated from each other; the doping group is bridged; for the adjacent first and second cells, the first N-type doped region and the second P-type doped region The impurity region and the third N-type impurity region are electrically connected; the bridge doping group includes: a plurality of discrete fourth P-type impurity regions arranged along the second direction, and each fourth P-type impurity region is located in a part of the first The tops of the two N-type wells extend to the tops of part of the second P-type wells, the second direction is perpendicular to the first direction; it is located between the adjacent fourth P-type doped regions and is connected to the fourth P-type doped regions The adjacent fourth N-type doped region; the conductive structure electrically connecting the fourth N-type doped region and the fourth P-type doped region. The performance of the SCR electrostatic protection structure is improved.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

1 to 4 are schematic structural diagrams of a process of forming an SCR electrostatic protection structure according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 200 is provided.

The semiconductor substrate 200 has substrate trap ions, and the conductivity type of the substrate trap ions is P-type.

The material of the semiconductor substrate 200 is single crystal silicon, single crystal germanium or single crystal silicon germanium.

The semiconductor substrate 200 includes a first unit area A and a second unit area B, and the first unit area A and the second unit area B are separated from each other.

The number of the second unit area B is one or more. In this embodiment, the number of the second unit area B is multiple as an example for description. When the number of the second unit area B is multiple, the number of the second unit area B is multiple. The second unit regions B are separated from each other.

The first unit area A and the second unit area B are arranged along the first direction X, and the plurality of second unit areas B are arranged along the first direction X.

Next, discrete first and second cells are formed in the semiconductor substrate 200 . Specifically, the first unit is formed in the first unit area A, and the second unit is formed in the second unit area B.

In this embodiment, the number of the second unit regions B is multiple, and correspondingly, the number of the second unit is multiple. In other embodiments, the number of second units is one.

The method of forming the first unit includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well on a side of the first N-type well along a first direction; A first P-type doped region is formed on the top of an N-type well; a first N-type doped region is formed on the top of the first P-type well;

The method of forming the second unit includes: forming a second N-type well in a semiconductor substrate; forming a second P-type well adjacent to the second N-type well on a side of the second N-type well along the first direction; The top of the two N-type wells form a second P-type doped region and a third N-type doped region that are separate from each other; the top of the second P-type well is formed to form a mutually separate second N-type doped region and a third N-type doped region. P-type doped region; forming a bridge doping group; for adjacent first and second cells, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected .

2, a first N-type well 201 is formed in a semiconductor substrate 200; a first P-type well 202 adjacent to the first N-type well 201 is formed on the side of the first N-type well 201 along the first direction X; A second N-type well 301 is formed in the semiconductor substrate 200 ; a second P-type well 302 adjacent to the second N-type 301 well is formed on the side of the second N-type well 301 along the first direction X.

The surface of the semiconductor substrate 200 exposes the first N-type well 201 , the first P-type well 202 , the second N-type well 301 and the second P-type well 302 , that is, the first N-type well 201 The top surface is flush with the surface of the semiconductor substrate 200 , the top surface of the first P-type well 202 is flush with the surface of the semiconductor substrate 200 , the top surface of the second N-type well 301 is flush with the surface of the semiconductor substrate 200 , The top surface of the second P-type well 302 is flush with the surface of the semiconductor substrate 200 .

In this embodiment, referring to FIG. 2 , the method for forming the first unit further includes: forming a first side isolation well 203 and a first bottom isolation well 204 in the semiconductor substrate 200 , and the first side isolation well 203 is along the first direction X Located on the side of the first P-type well 202 and adjacent to the first P-type well 202, the first P-type well 202 is located between the first side isolation well 203 and the first N-type well 201, and the first bottom isolation well 204 is located in the first P-type well 202. The bottom of a P-type well 202 is adjacent to the first P-type well 202 , and the first bottom isolation well 204 is also connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203 , respectively.

The conductivity type of the first side isolation well 203 is N-type, and the conductivity type of the first bottom isolation well 204 is N-type.

The first bottom isolation well 204 is located at the bottom of the first P-type well 202 and is adjacent to the first P-type well 202 . The first bottom isolation well 204 is also connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203 respectively. connected, so that the first bottom isolation well 204, the first N-type well 201 and the first side isolation well 203 surround the first P-type well 202, so that the first P-type well 202 and the semiconductor substrate at the bottom of the first bottom isolation well 204 The bottom 200 is isolated so that the first P-type well 202 is isolated from the semiconductor substrate 200 on the side of the first side isolation well 203 .

In this embodiment, referring to FIG. 2 , the method for forming the second unit further includes: forming a second side isolation well 303 and a second bottom isolation well 304 in the semiconductor substrate 200 , and the second side isolation well 303 is along the first side isolation well 303 . The direction is located on the side of the second P-type well 302 and adjacent to the second P-type well 302, the second P-type well 302 is located between the second side isolation well 303 and the second N-type well 301, and the second bottom isolation well 304 is located in The bottom of the second P-type well 302 is adjacent to the second P-type well 302 , and the second bottom isolation well 304 is also connected to the bottom of the second N-type well 301 and the bottom of the second side isolation well 303 , respectively.

The conductivity type of the second side isolation well 303 is N-type, and the conductivity type of the second bottom isolation well 304 is N-type.

The second bottom isolation well 304 is located at the bottom of the second P-type well 302 and is adjacent to the second P-type well 302. The second bottom isolation well 304 is also connected to the bottom of the second N-type well 301 and the bottom of the second side isolation well 303, respectively. , so that the second bottom isolation well 304 , the second N-type well 301 and the second side isolation well 303 surround the second P-type well 302 , so that the second P-type well 302 and the semiconductor substrate at the bottom of the second bottom isolation well 304 200 isolation, so that the second P-type well 302 is isolated from the semiconductor substrate 200 on the side of the second side isolation well 303 .

In this embodiment, the method for forming the first unit further includes: forming a first isolation insulating layer 510 and a second isolation insulating layer 520 in the first unit region of the semiconductor substrate 200 . In this embodiment, the first isolation insulating layer 510 is used to form a part of the subsequent first isolation group layers.

Part of the second isolation insulating layer 520 is located in the first N-type well 201, part of the second isolation insulating layer 520 is located in the first P-type well 202, part of the second isolation insulating layer 520 is located on top of the first side isolation well 203 and extending into part of the first P-type well 202 .

In this embodiment, the method for forming the second cell further includes: forming a third isolation insulating layer 530 in the second cell region of the semiconductor substrate 200 .

Part of the third isolation insulating layer 530 is located in the second N-type well 301, part of the third isolation insulating layer 530 is located in the second P-type well 302, part of the third isolation insulating layer 530 is located on top of the second side isolation well 303 and extends into part of the second P-type well 302 .

The material of the first isolation insulating layer 510 includes silicon oxide. The material of the second isolation insulating layer 520 includes silicon oxide. The material of the third isolation insulating layer 530 includes silicon oxide.

Referring to FIG. 3, a first P-type doped region 210 is formed on the top of the first N-type well 201; a first N-type doped region 220 is formed on the top of the first P-type well 202; The top of the second P-type well 301 forms a second P-type doping region 310 and a third N-type doping region 330; Three P-type doping regions 340; forming a bridge doping group.

For the adjacent first and second cells, the first N-type doped region 220 , the second P-type doped region 310 and the third N-type doped region 330 are electrically connected.

The method for forming the bridge doping group includes: forming a plurality of discrete fourth P-type doping regions 350 arranged along the second direction Y, each fourth P-type doping region 350 is located in a part of the second N-type well 301 and extending to the top of part of the second P-type well 302, the second direction Y is perpendicular to the first direction X; The adjacent fourth N-type doped region 360 is located at the top of a part of the second N-type well 301 and extends to the top of a part of the second P-type well 302 .

The method of forming the first unit further includes: forming a fifth N-type doped region 230 located at the top of the first N-type well 201 , and the fifth N-type doped region 230 is separated from the first P-type doped region 210 , and the fifth N-type doping region 230 is electrically connected to the first P-type doping region 210 .

In this embodiment, the first P-type doping region 210 and the fifth N-type doping region 230 are both connected to the anode potential.

The method of forming the first unit further includes: forming a fifth P-type doped region 240 located at the top of the first P-type well 202 , and the fifth P-type doped region 240 is separated from the first N-type doped region 220 , and the fifth P-type doping region 240 is electrically connected to the first N-type doping region 220 .

In this embodiment, the method for forming the first unit further includes: forming a sixth P-type doped region 250 in the semiconductor substrate 200 , and the sixth P-type doped region 250 is located in part of the first N-type well 201 and extends to a portion of the top of the first P-well 202 .

In this embodiment, the first isolation insulating layer is located on both sides of the sixth P-type doped region 250 in the first direction X, respectively, and the first isolation insulating layer on one side of the sixth P-type doped region 250 is located at the first N In the type well 201 , the first isolation insulating layer on the other side of the sixth P-type doped region 250 is located in the first P-type well 202 .

In this embodiment, the first isolation insulating layer and the sixth P-type doped region 250 constitute a first isolation group layer, and the first isolation group layer is located between the first P-type doped region 210 and the first N-type doped region 220 In the intermediate semiconductor substrate 200 , the first isolation group layer is located on top of a portion of the first N-type well 201 and extends to the top of a portion of the first P-type well 202 .

The concentration of P-type ions in the sixth P-type doped region 250 is much larger than the concentration of P-type ions in the first P-type well 202 .

In other embodiments, the first isolation group layer is a single-layer structure, the material of the first isolation group layer includes silicon oxide, and the first isolation group layer is located between the first P-type doping region and the first N-type doping region In the semiconductor substrate, the first isolation group layer is located on top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.

In this embodiment, the first P-type doping region 210 , the first N-type doping region 220 , the fifth N-type doping region 230 , the fifth P-type doping region 240 and the sixth P-type doping region 250 are mutually Discrete, fifth P-type doped region 240, first P-type doped region 210, sixth P-type doped region 250, first N-type doped region 220, and fifth N-type doped region 230 along the first direction X arrangement.

In a specific embodiment, the first P-type doping region 210 is located between the fifth N-type doping region 230 and the first isolation group layer, and the first N-type doping region 220 is located in the fifth P-type doping region 240 and the first isolation group layer.

A second isolation insulating layer 520 is provided between the first P-type doping region 210 and the fifth N-type doping region 230 and between the first N-type doping region 220 and the fifth P-type doping region 240 .

The second P-type doping region 310 , the second N-type doping region 320 , the third N-type doping region 330 , the third P-type doping region 340 and the bridge doping group are separated from each other.

In a specific embodiment, the second P-type doping region 310 is located between the bridge doping group and the third N-type doping region 330, and the second N-type doping region 320 is located across the bridge connected between the doping group and the third P-type doping region 340 .

Between the second P-type doping region 310 and the third N-type doping region 330, between the second P-type doping region 310 and the bridge doping group, and between the second N-type doping region 320 and the third doping group A third isolation insulating layer 530 is provided between the P-type doping regions 340 and between the second N-type doping regions 320 and the bridge doping group.

The concentration of P-type ions in the fourth P-type doped region 350 is greater than the concentration of P-type ions in the second P-type well 302 . The concentration of N-type ions in the fourth N-type doped region 360 is greater than the concentration of N-type ions in the second N-type well 301 .

For the adjacent first and second cells, the first N-type doped region 220 , the second P-type doped region 310 and the third N-type doped region 330 are electrically connected.

In this embodiment, the number of the second units is multiple as an example, and the multiple second units are respectively the first-level second unit to the Q-th level second unit, where Q is an integer greater than or equal to 2; The second N-type doped region 320 and the third P-type doped region 340 in the level 2 cell and the second P-type doped region 310 and the third N-type doped region in the i+1-th level second cell 330 is electrically connected, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the second unit of the Q-th stage are connected to the cathode potential, the first N The doped region is electrically connected to the second P-type doped region 310 and the third N-type doped region 330 in the first-level second cell.

In this embodiment, it is described by taking Q equal to 2 as an example, the number of the second cells is two, and the plurality of second cells are the first-level second cells to the second-level second cells respectively.

In other embodiments, Q may be 3, 4, 5, 6, or an integer greater than or equal to 7.

In other embodiments, the number of the second unit is one, and both the second N-type doped region and the third P-type doped region are connected to a cathode potential.

The method for forming the SCR electrostatic protection structure further includes: forming a seventh P-type doped region 400 on the top of a part of the semiconductor substrate 200 , and the seventh P-type doped region 400 is respectively located in the adjacent first cells Between the second unit and the second unit and on both sides of the second unit along the first direction X, each seventh P-type doped region 400 is grounded.

Each of the seventh P-type doped regions 400 is grounded, so that the semiconductor substrate 200 is grounded, so as to avoid a latch-up effect.

In this embodiment, there is a second isolation insulating layer 520 between the seventh P-type doping region 400 and the fifth P-type doping region 240 . A second isolation insulating layer 520 is provided between the P-type doped region 400 and the fifth P-type doped region 240 in the first cell.

In this embodiment, a third isolation insulating layer 530 is provided between the seventh P-type doped region 400 and the third N-type doped region 330 . Specifically, a third isolation insulating layer 530 is provided between the seventh P-type doped region 400 between the first cell and the first-level second cell and the third N-type doped region 330 in the first-level second cell ; The seventh P-type doped region 400 between the i-th level second unit and the i+1-th level second unit and the third N-type doped region 330 in the i+1-th level second unit have The third isolation insulating layer 530 .

In this embodiment, there is a third isolation insulating layer 530 between the seventh P-type doped region 400 and the third P-type doped region 340 . Specifically, the i-th second unit and the i+1-th second unit There is a third isolation insulating layer 530 between the seventh P-type doped region 400 therebetween and the third P-type doped region 340 in the i-th second cell.

Referring to FIG. 4 , a conductive structure 500 is formed on the semiconductor substrate 200 , and the conductive structure 500 is electrically connected to the fourth N-type doped region and the fourth P-type doped region.

In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the material of the conductive structure 500 is metal silicide.

In other embodiments, the conductive structure includes: a first metal silicide layer on the surface of the fourth N-type doped region; a second metal silicide layer on the surface of the fourth P-type doped region, the first metal silicide layer and the second metal silicide layer are separated from each other; a metal connection layer located on the first metal silicide layer and the second metal silicide layer, the metal connection layer is respectively connected to the first metal silicide layer and the second metal silicide layer .

When the conductive structure 500 is located on the surface of the fourth N-type doping region and extends to the surface of the fourth P-type doping region, and the material of the conductive structure 500 is metal silicide, the structure of the conductive structure 500 is relatively simple, Production costs are reduced.

In this embodiment, it further includes: a first connection layer on the semiconductor substrate, the first connection layer is connected to the first P-type doping region 210 and the fifth N-type doping region 230 respectively, and the first connection layer is connected to Anode potential. The material of the first connection layer includes metals such as copper or aluminum.

In this embodiment, it further includes: a second connection layer on the semiconductor substrate, the second connection layer is respectively connected with the fifth P-type doped region 240 , the first N-type doped region 220 , and the first-level second unit. The second P-type doped region 310 and the third N-type doped region 330 are connected, and the material of the second connection layer refers to the material of the first connection layer.

In this embodiment, it further includes: an i-th level connection layer on the semiconductor substrate, and the i-th level connection layer connects the second N-type doping region 320 and the third P-type doping region in the i-th level second unit 340 , and the second P-type doped region 310 and the third N-type doped region 330 in the i+1-th level second unit, where i is an integer greater than or equal to 1 and less than or equal to Q−1. The material of the i-th connection layer refers to the material of the first connection layer.

In this embodiment, it further includes: a third connection layer on the semiconductor substrate, the third connection layer is connected to the second N-type doping region 320 and the third P-type doping region 340 in the second unit of the Q-th level, The third connection layer is connected to the cathode potential. The material of the third connection layer refers to the material of the first connection layer.

In this embodiment, it further includes: a fourth connection layer on the semiconductor substrate 200, the fourth connection layer is connected to the seventh P-type doped regions 400, and the material of the fourth connection layer refers to the material of the first connection layer.

The SCR electrostatic protection structure of this embodiment includes a first current discharge structure and a second current discharge structure.

The first current bleed structure is a PNPN structure, the first current bleed structure includes a first PNP transistor and a first NPN transistor, the first P-type doped region 210 is used as the emitter of the first PNP transistor, and the first P-type doped region The first N-type well 201 at the bottom of the region 210 is used as the base of the first PNP transistor, the first P-type well 202 at the bottom of the first N-type doped region 220 is used as the collector of the first PNP transistor, and the first P-type doping The first N-type well 201 at the bottom of the region 210 is used as the collector of the first NPN transistor, the first P-type well 202 at the bottom of the first N-type doped region 220 is used as the base of the first NPN transistor, and the first N-type doping Region 220 serves as the emitter of the first NPN transistor.

The second current bleeder structure is a PNPN structure, the second current bleeder structure includes a second PNP transistor and a second NPN transistor, the second P-type doped region 310 serves as the emitter of the second PNP transistor, and the second P-type doped region The second N-type well 301 at the bottom of the region 310 is used as the base of the second PNP transistor, the second P-type well 302 at the bottom of the second N-type doped region 320 is used as the collector of the second PNP transistor, and the second P-type doping The second N-type well 301 at the bottom of the region 310 is used as the collector of the second NPN transistor, the second P-type well 302 at the bottom of the second N-type doped region 320 is used as the base of the second NPN transistor, and the second N-type doping Region 320 acts as the emitter of the second NPN transistor. The second current discharge structures in the second units of each stage are connected in series.

The SCR electrostatic protection structure of this embodiment further includes a resistive current conducting structure, and the resistive current conducting structure includes: a third N-type doped region 330 , a second N-type well 301 , a bridge doping group, a second P-type well 302 and The third P-type doped region 340 .

In the SCR electrostatic protection structure of this embodiment, there are a first current discharge path L1 and a second current discharge path L2, the first current discharge path L1 corresponds to the first current discharge structure, and the second current discharge path L2 corresponds to The second current discharge structure. The resistive conducting structure has a resistive conducting path L3, and the resistive conducting path L3 includes: from the third N-type doped region 330 to the second N-type well, and from the second N-type well to the fourth one in the straddle doping group N-type doped region 360, from the fourth N-type doped region 360 through the conductive structure 500 to the fourth P-type doped region 350, from the fourth P-type doped region 350 to the second P-type well 302, from the second The P-type well 302 to the third P-type doped region 340 . The resistance diversion paths in the second units of each stage are connected in series.

In this embodiment, since the first current discharge path L1 and the second current discharge path L2 are superimposed in series, the holding voltage of the SCR electrostatic protection structure is increased, and the holding voltage of the SCR electrostatic protection structure is the same as that of the first current discharge structure. The sum of the holding voltage and the holding voltage of the second current discharge structure, thus increasing the holding voltage of the SCR electrostatic protection structure. Since the holding voltage of the SCR electrostatic protection structure is increased, the normal operating voltage range of the semiconductor device is expanded for the semiconductor device protected by the SCR electrostatic protection structure.

In this embodiment, a trigger voltage is applied to the cathode and the anode. In the initial stage, the second current discharge path in the second unit is non-conductive, the resistance current conducting structure in the second unit is conductive, and the The voltage drop is small. At this time, most of the voltage in the trigger voltage is applied to the first unit, and most of the voltage in the trigger voltage is applied to the first unit, so that the first current discharge path in the first unit is turned on, thus triggering The first current bleeder path performs the bleeder, and subsequently, the conduction of the second current bleeder path is triggered due to the conduction of the first current bleeder path, thus triggering the first current bleeder path to perform the bleeder. In this way, the trigger voltage required for the conduction of the first current discharge path in the SCR electrostatic protection structure to trigger the conduction of the second current discharge path is reduced.

Further, the concentration of P-type ions in the sixth P-type doped region 250 is much greater than the concentration of P-type ions in the first P-type well 202 , so that the space between the sixth P-type doped region 250 and the first N-type well 201 is The breakdown voltage is lower, so the trigger voltage required to make the first current discharge path L1 in the first cell turn on is further reduced.

Correspondingly, this embodiment also provides an SCR electrostatic protection structure, please refer to FIG. 3 and FIG. 4 in combination, including:

semiconductor substrate 200;

discrete first and second units located in the semiconductor substrate 200;

The first unit includes: a first N-type well 201 and a first P-type well 202 located in the semiconductor substrate 200. The first P-type well 202 is located at the side of the first N-type well 201 along the first direction X and is connected to the first N-type well 201. The N-type well 201 is adjacent; the first P-type doped region 210 located at the top of the first N-type well 201; the first N-type doped region 220 located at the top of the first P-type well 202;

The second unit includes: a second N-type well 301 and a second P-type well 302 located in the semiconductor substrate 200. The second P-type well 302 is located at the side of the second N-type well 301 along the first direction X and is connected to the second N-type well 301. The N-type well 301 is adjacent; the second P-type doped region 310 and the third N-type doped region 330 are located at the top of the second N-type well 301 and are separated from each other; Two N-type doping regions 320 and a third P-type doping region 340; bridge doping groups; for adjacent first and second cells, the first N-type doping region 220 and the second P-type doping region the region 310 and the third N-type doped region 330 are electrically connected;

The bridge doping group includes: a plurality of discrete fourth P-type doping regions 350 arranged along the second direction Y, each fourth P-type doping region 350 is located on top of a portion of the second N-type well 301 and extends To the top part of the second P-type well 302 , the second direction Y is perpendicular to the first direction X; N-type doped region 360, the fourth N-type doped region 360 is located on the top part of the second N-type well 301 and extends to the top part of the second P-type well 302;

The conductive structure 500 on the semiconductor substrate 200 is electrically connected to the fourth N-type doped region 360 and the fourth P-type doped region 350 .

The semiconductor substrate 200 has substrate trap ions, and the conductivity type of the substrate trap ions is P-type.

In this embodiment, the number of the second units is multiple as an example, and the multiple second units are respectively the first-level second unit to the Q-th level second unit, where Q is an integer greater than or equal to 2; The second N-type doped region 320 and the third P-type doped region 340 in the level 2 cell and the second P-type doped region 310 and the third N-type doped region in the i+1-th level second cell 330 is electrically connected, i is an integer greater than or equal to 1 and less than or equal to Q-1, the second N-type doped region 320 and the third P-type doped region 340 in the second unit of the Q-th stage are connected to the cathode potential, the first N The doped region is electrically connected to the second P-type doped region 310 and the third N-type doped region 330 in the first-level second cell.

In other embodiments, the number of the second unit is one, and both the second N-type doped region and the third P-type doped region are connected to a cathode potential.

The first P-type doped region 210 and the fifth N-type doped region 230 are both connected to the anode potential.

The first unit further includes: a fifth N-type doped region 230 located at the top of the first N-type well 201, the fifth N-type doped region 230 and the first P-type doped region 210 are separated from each other, and the fifth N-type doped region 230 is separated from the first P-type doped region 210. The N-type doped region 230 is electrically connected to the first P-type doped region 210 .

The first unit further includes: a fifth P-type doped region 240 located at the top of the first P-type well 202, the fifth P-type doped region 240 and the first N-type doped region 220 are separated from each other, and the fifth The P-type doped region 240 is electrically connected to the first N-type doped region 220 .

The first unit further includes: a first isolation group layer located in the semiconductor substrate 200 between the first P-type doping region 210 and the first N-type doping region 220, and the first isolation group layer is located in part of the first N-type doping region. type well 201 and extends to the top in part of the first P-type well 202 .

In this embodiment, the first isolation group layer includes a sixth P-type doped region 250 and a first isolation insulating layer 510 located on both sides of the sixth P-type doped region 250 along the first direction X, respectively. The doped region 250 is located at the top of part of the first N-type well 201 and extends to the top of part of the first P-type well 202, and the first isolation insulating layer 510 on the side of the sixth P-type doped region 250 is located at the first In the N-type well 201 , the first isolation insulating layer 510 on the other side of the sixth P-type doped region is located in the first P-type well 202 .

In other embodiments, the first isolation group layer is a single-layer structure, and the material of the first isolation group layer includes silicon oxide.

The first unit further includes: a first side isolation well 203 located in the semiconductor substrate 200 , the first side isolation well 203 is located on the side of the first P-type well 202 along the first direction X and is connected to the first P-type well 202 . Adjacent, the first P-type well 202 is located between the first side isolation well 203 and the first N-type well 201, and the conductivity type of the first side isolation well is N-type; the first bottom isolation well 204, the first bottom isolation well 204 Located at the bottom of the first P-type well 202 and adjacent to the first P-type well 202, the first bottom isolation well 204 is also connected to the bottom of the first N-type well 201 and the bottom of the first side isolation well 203, respectively. The conductivity type of the isolation well is N-type.

The second unit further includes: a second side isolation well 303 located in the semiconductor substrate 200 , the second side isolation well 303 is located at the side of the second P-type well 302 along the first direction X and is connected to the second P-type well 302 . Adjacent, the second P-type well 302 is located between the second side isolation well 303 and the second N-type well 301, the conductivity type of the second side isolation well 303 is N-type; the second bottom isolation well 304, the second bottom isolation well 304 is located at the bottom of the second P-type well 302 and is adjacent to the second P-type well 302. The second bottom isolation well 304 is also connected to the bottom of the second N-type well 301 and the bottom of the second side isolation well 303, respectively. The conductivity type of the isolation well 304 is N-type.

The SCR electrostatic protection structure further includes: a seventh P-type doped region 400 located at the top of a part of the semiconductor substrate 200 , and the seventh P-type doped region 400 is located in the adjacent first unit and the second cell, respectively Between the cells and on both sides of the second cell along the first direction, each of the seventh P-type doped regions 400 is grounded.

In this embodiment, the conductive structure 500 is located on the surface of the fourth N-type doped region and extends to the surface of the fourth P-type doped region; the material of the conductive structure 500 is metal silicide.

In other embodiments, the conductive structure includes: a first metal silicide layer on the surface of the fourth N-type doped region; a second metal silicide layer on the surface of the fourth P-type doped region, the first metal silicide layer and the second metal silicide layer are separated from each other; a metal connection layer located on the first metal silicide layer and the second metal silicide layer, the metal connection layer is respectively connected to the first metal silicide layer and the second metal silicide layer .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (20)

1. An SCR electrostatic protection structure, comprising:

a semiconductor substrate;

a first unit and a second unit which are separated and located in a semiconductor substrate;

the first unit includes: a first N-type well and a first P-type well in the semiconductor substrate, the first P-type well being located along a first direction at a side of the first N-type well and adjacent to the first N-type well; a first P-type doped region located on top of the first N-type well; a first N-type doped region located on top of the first P-type well;

the second unit includes: a second N-type well and a second P-type well in the semiconductor substrate, the second P-type well being located along a first direction at a side of the second N-type well and adjacent to the second N-type well; the second P-type doped region and the third N-type doped region are positioned on the top of the second N-type well and are mutually separated; the second N-type doped region and the third P-type doped region are positioned on the top of the second P-type well and are separated from each other; bridging the doped group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;

the cross-over doping group comprises: a plurality of discrete fourth P-type doped regions arranged along a second direction, each fourth P-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well, the second direction being perpendicular to the first direction; a fourth N-type doped region located between adjacent fourth P-type doped regions and adjacent to the fourth P-type doped region, the fourth N-type doped region being located at the top of a portion of the second N-type well and extending to the top of a portion of the second P-type well;

and the conductive structure is positioned on the semiconductor substrate and is electrically connected with the fourth N-type doped region and the fourth P-type doped region.

2. The SCR electrostatic protection structure of claim 1, wherein the number of the second cells is one; and the second N-type doped region and the third P-type doped region are both connected with a cathode potential.

3. The SCR electrostatic protection structure of claim 1, wherein the number of the second cells is plural; the plurality of second units are respectively a first-stage second unit to a Q-th-stage second unit, and Q is an integer greater than or equal to 2; the second N-type doped region and the third P-type doped region in the ith-level second unit are electrically connected with the second P-type doped region and the third N-type doped region in the (i + 1) th-level second unit, i is an integer which is more than or equal to 1 and less than or equal to Q-1, the second N-type doped region and the third P-type doped region in the Q-level second unit are connected with a cathode potential, and the first N-type doped region is electrically connected with the second P-type doped region and the third N-type doped region in the first-level second unit.

4. The SCR electrostatic protection structure of claim 1, wherein said first P-type doped region is connected to an anode potential.

5. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: and the fifth N-type doped region is positioned at the top in the first N-type well, the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region.

6. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: and the fifth P-type doped region is positioned at the top in the first P-type well, the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.

7. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: a first isolation group layer in the semiconductor substrate between the first P-type doped region and the first N-type doped region, the first isolation group layer being on top of a portion of the first N-type well and extending to top of a portion of the first P-type well.

8. The SCR electrostatic protection structure of claim 7, wherein the first isolation group layer comprises a sixth P-type doped region and first isolation insulation layers respectively located at two sides of the sixth P-type doped region along the first direction, the sixth P-type doped region is located at the top of a portion of the first N-type well and extends to the top of a portion of the first P-type well, the first isolation insulation layer at one side of the sixth P-type doped region is located in the first N-type well, and the first isolation insulation layer at the other side of the sixth P-type doped region is located in the first P-type well.

9. The SCR electrostatic protection structure of claim 7, wherein the first isolation group layer is a single layer structure, and the material of the first isolation group layer comprises silicon oxide.

10. The SCR electrostatic protection structure of claim 1, wherein the first unit further comprises: the first side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the first P-type well along the first direction and is adjacent to the first P-type well, the first P-type well is positioned between the first side isolation well and the first N-type well, and the conductivity type of the first side isolation well is N-type; and the first bottom isolation well is positioned at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is also respectively connected with the bottom of the first N-type well and the bottom of the first side isolation well, and the conductivity type of the first bottom isolation well is an N type.

11. The SCR electrostatic protection structure of claim 1, wherein the second unit further comprises: the second side isolation well is positioned in the semiconductor substrate, is positioned on the side part of the second P-type well along the first direction and is adjacent to the second P-type well, is positioned between the second side isolation well and the second N-type well, and has an N-type conductivity type; and the second bottom isolation well is positioned at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is also respectively connected with the bottom of the second N-type well and the bottom of the second side isolation well, and the conductivity type of the second bottom isolation well is an N type.

12. The SCR electrostatic protection structure of claim 1, further comprising: and the seventh P-type doped region is positioned at the top part of the semiconductor substrate, is respectively positioned between the adjacent first unit and the second unit and on two sides of the second unit along the first direction, and is grounded.

13. The SCR electrostatic protection structure of claim 1, wherein the conductive structure is located on a surface of the fourth N-type doped region and extends to a surface of the fourth P-type doped region; the conductive structure is made of metal silicide.

14. The SCR electrostatic protection structure of claim 1, wherein said semiconductor substrate has substrate trap ions therein, said substrate trap ions being of a P-type conductivity type.

15. A method of forming an SCR electrostatic protection structure according to any one of claims 1 to 14, comprising:

providing a semiconductor substrate;

forming a first unit and a second unit which are separated in a semiconductor substrate;

the method of forming the first cell includes: forming a first N-type well in a semiconductor substrate; forming a first P-type well adjacent to the first N-type well at a side portion of the first N-type well in a first direction; forming a first P-type doped region on top of the first N-type well; forming a first N-type doped region on top of the first P-type well;

the method of forming the second cell includes: forming a second N-type well in the semiconductor substrate; forming a second P-type well adjacent to the second N-type well at a side portion of the second N-type well in the first direction; forming a second P-type doped region and a third N-type doped region which are separated from each other on the top in the second N-type well; forming a second N-type doped region and a third P-type doped region which are separated from each other on the top in the second P-type well; forming a cross-over doping group; for the adjacent first unit and the second unit, the first N-type doped region, the second P-type doped region and the third N-type doped region are electrically connected;

the method for forming the cross-over doping group comprises the following steps: forming a plurality of discrete fourth P-type doped regions arranged along a second direction, wherein each fourth P-type doped region is positioned at the top of part of the second N-type well and extends to the top of part of the second P-type well, and the second direction is vertical to the first direction; forming a fourth N-type doped region adjacent to the fourth P-type doped region between the adjacent fourth P-type doped regions, wherein the fourth N-type doped region is positioned on the top of part of the second N-type well and extends to the top of part of the second P-type well;

and forming a conductive structure on the semiconductor substrate, wherein the conductive structure is electrically connected with the fourth N-type doped region and the fourth P-type doped region.

16. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: forming a fifth N-type doped region on the top of the first N-type well, wherein the fifth N-type doped region and the first P-type doped region are mutually separated, and the fifth N-type doped region is electrically connected with the first P-type doped region; and forming a fifth P-type doped region on the top of the first P-type well, wherein the fifth P-type doped region and the first N-type doped region are mutually separated, and the fifth P-type doped region is electrically connected with the first N-type doped region.

17. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: a first isolation group layer is formed in the semiconductor substrate between the first P-type doped region and the first N-type doped region, and the first isolation group layer is located on top of a portion of the first N-type well and extends to the top of a portion of the first P-type well.

18. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the first unit further comprises: before a first P-type doped region and a first N-type doped region are formed, a first side isolation well and a first bottom isolation well are formed in a semiconductor substrate, the first side isolation well is located on the side portion of the first P-type well along a first direction and is abutted to the first P-type well, the first P-type well is located between the first side isolation well and the first N-type well, the first bottom isolation well is located at the bottom of the first P-type well and is abutted to the first P-type well, the first bottom isolation well is further connected with the bottom of the first N-type well and the bottom of the first side isolation well respectively, and the conductivity types of the first side isolation well and the first bottom isolation well are both N-type.

19. The method of forming an SCR electrostatic protection structure of claim 15, wherein the method of forming the second unit further comprises: before forming a second P-type doped region, a second N-type doped region, a third N-type doped region and a third P-type doped region, a second side isolation well and a second bottom isolation well are formed in the semiconductor substrate, the second side isolation well is located on the side portion of the second P-type well along the first direction and is abutted to the second P-type well, the second P-type well is located between the second side isolation well and the second N-type well, the second bottom isolation well is located at the bottom of the second P-type well and is abutted to the second P-type well, the second bottom isolation well is further connected with the bottom of the second N-type well and the bottom of the second side isolation well respectively, and the conductivity types of the second side isolation well and the second bottom isolation well are both N-type.

20. The method for forming an SCR electrostatic protection structure of claim 15, further comprising: and forming seventh P-type doped regions on the top of part of the semiconductor substrate, wherein the seventh P-type doped regions are respectively positioned between the adjacent first unit and second unit and on two sides of the second unit along the first direction, and all the seventh P-type doped regions are grounded.

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