CN111782562A - Data transmission method, DMA controller, NPU chip and computer equipment - Google Patents
Data transmission method, DMA controller, NPU chip and computer equipment Download PDFInfo
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Abstract
The embodiment of the application discloses a data transmission method, a DMA (direct memory access) controller, an NPU (network processor unit) chip and computer equipment, and belongs to the technical field of chips. The method comprises the following steps: acquiring a first data transmission instruction, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter; sending a first data reading command to a bus according to the first reading address parameter; responding to the received first data returned by the bus, and writing the first data into the destination terminal according to the first write address parameter; and in response to the first data returned by the bus not being received, writing the first interpolation data into the destination terminal according to the first interpolation address parameter. Compared with data interpolation after data transmission is finished, the data interpolation function is integrated into the DMA controller, so that the data interpolation is carried out by utilizing the time delay period of sending the command to the data return, the delay of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of chips, in particular to a data transmission method, a DMA (direct memory access) controller, an NPU (network processor unit) chip and computer equipment.
Background
A Direct Memory Access (DMA) controller is a component used for realizing data transmission in a computer system, and can reduce the performance impact of data transmission on a Central Processing Unit (CPU).
When the DMA controller is used for data transmission, the DMA controller firstly acquires the control right of a system bus from the CPU, and then reads data from a source data address through the system bus, so that the read data is written into a destination address. For example, when partial data in the external memory needs to be written into a Neural-Network Processing Unit (NPU), the DMA controller reads data from the external memory through the system bus according to the source data address, and writes the read data into an internal buffer of the NPU according to the destination address.
Disclosure of Invention
The embodiment of the application provides a data transmission method, a DMA (direct memory access) controller, an NPU (network processor unit) chip and computer equipment. The technical scheme comprises the following steps:
in one aspect, an embodiment of the present application provides a data transmission method, where the method is used for a direct memory access DMA controller, and the method includes:
acquiring a first data transmission instruction, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter, the first read address parameter is used for indicating an address of first data in a source end, the first write address parameter is used for indicating an address of the first data in a destination end, and the first interpolation address parameter is used for indicating an address of first interpolation data in the destination end;
sending a first data read command to a bus according to the first read address parameter, where the bus is used to read the first data from the source end according to the first data read command;
in response to receiving the first data returned by the bus, writing the first data into the destination terminal according to the first write address parameter;
and in response to the first data returned by the bus is not received, writing the first interpolation data into the target end according to the first interpolation address parameter.
In another aspect, an embodiment of the present application provides a DMA controller, where the DMA controller includes: the device comprises a command sending module and a data writing module;
the command sending module is configured to obtain a first data transmission instruction, where the first data transmission instruction includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of the first data in a destination end, and the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end;
the command sending module is configured to send a first data read command to a bus according to the first read address parameter, where the bus is configured to read the first data from the source according to the first data read command;
the data writing module is used for writing the first data into the target end according to the first writing address parameter when the first data returned by the bus is received;
and the data writing module is further configured to write the first interpolation data into the destination according to the first interpolation address parameter when the first data returned by the bus is not received.
In another aspect, an embodiment of the present application provides an NPU chip, where the DMA controller is disposed in the NPU chip.
On the other hand, the embodiment of the application provides computer equipment, which comprises a CPU chip, an NPU chip and a memory, wherein the CPU chip, the NPU chip and the memory are connected through a bus; the NPU chip includes a DMA controller as described in the above aspects.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
in the embodiment of the application, when the DMA controller performs data transmission and the transmitted data has interpolation requirements, the DMA controller sends a data reading command to the bus, instructs the bus to read the data from the source end, writes the interpolation data into the destination end according to the interpolation address in the process of waiting for the bus to return the read data, and preferentially writes the read data into the destination end when receiving the data returned by the bus; compared with data interpolation after data transmission is finished, the data interpolation function is integrated into the DMA controller, so that the data interpolation is carried out by utilizing the time delay period of sending the command to the data return, the delay of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
Drawings
FIG. 1 is a schematic diagram of a DMA controller for data transfer in the related art;
FIG. 2 illustrates a method flow diagram of a data transmission method provided by an exemplary embodiment of the present application;
FIG. 3 is a schematic diagram of a three-dimensional data block provided by an exemplary embodiment;
FIG. 4 is a schematic diagram of a three-dimensional data block storage scheme shown in FIG. 3;
FIG. 5 illustrates a method flow diagram of a data transmission method provided by another exemplary embodiment of the present application;
FIG. 6 illustrates a method flow diagram of a data transmission method provided by another exemplary embodiment of the present application;
FIG. 7 is a diagram illustrating a DMA controller according to an exemplary embodiment of the present application;
FIG. 8 is a block diagram illustrating a DMA controller according to another exemplary embodiment of the present application;
fig. 9 shows a schematic structural diagram of a computer device provided in an exemplary embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Reference herein to "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
In the related art, the DMA controller only has a data transfer (or called data transfer) function, that is, after the DMA controller transfers data from the source end to the destination end, further processing of the data needs to be performed by the destination end. In a possible scenario, as shown in fig. 1, when data in the memory 11 needs to be transferred to the NPU chip 12, the CPU chip 13 sends a data transfer instruction to the DMA controller 14, the DMA controller 14 reads data from the memory 11 through the bus 15 according to the data transfer instruction, and writes the read data into an internal buffer of the NPU chip 12, so that the NPU chip 12 performs an operation on the written data.
Before the NPU chip processes data, it is often necessary to interpolate the data. For example, before the NPU chip performs convolution processing on the written image data, data padding (padding) is required on the image data, and the data padding operation is required to be performed by the NPU chip after the data transmission is completed.
However, when the DMA controller performs data transmission through the bus, there are bus delay and data reading delay, so that the above-mentioned manner of performing interpolation after transmission will cause higher delay, and affect the working efficiency of the destination (such as the NPU chip).
In order to reduce the delay and improve the work efficiency of the destination, the DMA controller provided in the embodiment of the present application has a data interpolation function in addition to a data transmission function. When the DMA controller is used for data transmission, in the process of reading data from a destination end through a bus, if data returned by the bus is not received, the DMA controller writes interpolated data into the destination end according to an interpolated address, and if the data returned by the bus is received, the DMA controller writes the read data into the destination end according to a write data address. By utilizing bus delay and data reading delay time interval to perform data interpolation instead of performing data interpolation after data transmission is finished, the total time consumption of data transmission and data interpolation can be reduced, and the working efficiency of a destination end is improved; moreover, because the DMA controller completes data interpolation, the destination end can omit data interpolation operation, thereby reducing the complexity of the operation executed by the destination end.
Referring to fig. 2, a flowchart of a method for transmitting data according to an exemplary embodiment of the present application is shown. The present embodiment is described by taking the method as an example for a DMA controller, and the method may include the following steps.
In some embodiments, the DMA controller receives a data transfer instruction sent by the CPU chip and caches the data transfer instruction in the instruction storage module, and accordingly, the DMA controller reads the first data transfer instruction from the instruction storage module.
In this embodiment, the first data transmission instruction, in addition to the read address of the first data at the source end and the write address at the destination end, also includes an interpolation address of the first data at the destination end, where the interpolation data is used to be inserted into the first data written by the destination end.
In one possible implementation, the first read address parameter, the first write address parameter, and the first interpolation address parameter all include a data start address and an address offset, so as to reduce the instruction length of the first data transfer instruction.
After the first data transmission instruction is acquired, the DMA controller acquires the control right of the bus, further determines the read address of the first data according to the first read address parameter, and further sends a first data read command containing the read address to the bus to indicate the bus to read the first data from the source end.
In one possible implementation, before sending the first data read command to the bus, the DMA controller converts the first data read command into a bus read command interface format, ensuring that the bus can recognize the command.
And step 203, responding to the received first data returned by the bus, and writing the first data into the destination terminal according to the first write address parameter.
When the first data returned by the bus is received, in order to avoid the first data from blocking the bus, the DMA controller preferentially writes the first data returned by the bus into the destination. And the DMA controller determines the write address of the first data in the destination terminal according to the first write address parameter, and then completes the writing of the first data according to the write address.
And step 204, in response to that the first data returned by the bus is not received, writing the first interpolation data into the destination terminal according to the first interpolation address parameter.
When the first data returned by the bus is not received (caused by bus delay or data reading delay), the DMA controller determines the interpolation address of the interpolation data in the destination end according to the first interpolation address parameter while waiting for the first data, and writes the interpolation data into the interpolation address, namely, performs data interpolation by using the bus and the data reading delay time.
It should be noted that, when the first data returned by the bus is received in the interpolation process, the DMA controller stops the data interpolation operation and writes the returned first data to the destination, that is, the write priority of the first data is higher than the write priority of the interpolated data.
In a possible application scenario, when image data in the memory needs to be transmitted to the NPU chip, the CPU chip sends a data transmission instruction (indicating a data read address, a data write address, and a data interpolation address) to the DMA controller, and the DMA controller reads the image data from the memory through the bus according to the data transmission instruction. In the process of waiting for the image data returned by the bus, the DMA controls to write the interpolation data into the NPU chip when the image data returned by the bus is not received, and to write the image data into the NPU chip when the image data returned by the bus is received. By performing data interpolation in the data transmission process, the time for the NPU chip to acquire image data and complete data interpolation is shortened, and the efficiency of subsequent convolution operation of the NPU chip is improved.
To sum up, in the embodiment of the present application, when the DMA controller performs data transmission and there is an interpolation requirement on the transmitted data, the DMA controller sends a data read command to the bus, instructs the bus to read data from the source end, writes the interpolated data into the destination end according to the interpolation address in the process of waiting for the bus to return the read data, and preferentially writes the read data into the destination end when receiving the data returned by the bus; compared with data interpolation after data transmission is finished, the data interpolation function is integrated into the DMA controller, so that the data interpolation is carried out by utilizing the time delay period of sending the command to the data return, the delay of the data transmission and the data interpolation is reduced, and the efficiency of the data transmission and the data interpolation is improved.
In one possible embodiment, the first data to be transmitted is composed of a number of data lines, and the DMA controller generates a corresponding first data read command for each data line and sends it to the bus. Optionally, step 202 includes the following steps.
Step 202A, determining a read data address corresponding to at least one data line in the first data according to the first read address parameter.
In some embodiments, the first read address parameter includes a data start address of a first data line in the first data and an address offset of the other data lines with respect to the first data line, and accordingly, the DMA controller determines a read data address of the first data line according to the data start address and determines read data addresses of the other data lines according to the data start address and the address offset.
In one possible embodiment, the first data is a three-dimensional data block, i.e. the first data is stacked by a number of three-dimensional data lines. As shown in fig. 3, the first data is a three-dimensional data block stacked by 6 × 5 data lines 31 (hatched filling), and accordingly, the three-dimensional data block is stored as shown in fig. 4.
As shown in fig. 4, the data start address (or called BASE address) of the first data line in the three-dimensional data block is BASE _ ADDR; d1_ NUM is the data length (e.g., number of bytes) of the data line in the first dimension (D1); d2_ NUM is the number of data rows in the second dimension (D2); d2_ OFFSET is the address OFFSET between adjacent data lines in the second dimension; d3_ NUM is the number of data rows in the third dimension (D3); d3_ OFFSET is the address OFFSET between adjacent data lines in the third dimension (i.e., the address OFFSET between two-dimensional data planes).
In some embodiments, the first read address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data lines in a two-dimensional direction, a three-dimensional address offset, and a number of data lines in a three-dimensional direction. Accordingly, in determining the read data addresses of the respective data rows in the three-dimensional data block, the following manner may be employed.
Firstly, determining the read data address of the data row in the first dimension according to the data start address in the first read address parameter.
Illustratively, as shown in fig. 4, the DMA controller may determine the read data address of the first data line in the first dimension according to the data start address included in the first read address parameter.
And secondly, determining the read data address of the data line in the second dimension according to the data start address and the two-dimensional address offset in the first read address parameter, wherein the two-dimensional address offset is the address offset between adjacent data lines in the second dimension.
When the read data addresses of the data rows in the second dimension are determined, the DMA controller performs address offset calculation on the data start address in the second dimension according to the two-dimensional address offset, and the read data addresses of the data rows are obtained through calculation.
In one possible implementation, the read data address of the ith data row in the second dimension is: BASE _ ADDR + (i-1). times.D 2_ OFFSET, i is more than or equal to 1 and less than or equal to D2_ NUM.
And thirdly, determining the read data address of the data row in the third dimension according to the data start address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
When the read data addresses of all data rows in the third dimension are determined, the DMA controller performs address offset calculation on the data initial address in the third dimension according to the three-dimensional address offset, and the read data addresses of the data rows are obtained through calculation.
In a possible implementation manner, the read data address of the jth data plane in the third dimension is: BASE _ ADDR + (j-1) xD 3_ OFFSET + (k-1) xD 2_ OFFSET, j is more than or equal to 1 and less than or equal to D3_ NUM, and k is more than or equal to 1 and less than or equal to D2_ NUM.
Step 202B, at least one first data read command is sent to the bus according to the read data address and the data length of the data row.
After the read data addresses corresponding to the data rows in the first data are determined, the DMA controller further generates first data read commands corresponding to the data rows according to the read data addresses and the data lengths of the data rows, and sends the first data read commands to the bus one by one. After the bus receives the first data reading command, the data is read from the data reading address, and the length of the read data is the data length in the command.
In one illustrative example, as shown in FIG. 3, since the first data consists of 30 lines of data, the DMA controller generates 30 first data read commands and sends them to the bus one by one.
In this embodiment, the DMA controller determines the read data address of each data line according to the data start address in the first read address parameter and the address offset of the data line in each dimension, so as to generate a corresponding data read command according to the read data address and the data length, and reduce the data size of the data transmission instruction on the premise of ensuring the data reading accuracy.
In order to further improve the bandwidth and transmission performance of the DMA controller, in a possible implementation manner, the destination is provided with n buffers, and the DMA controller is correspondingly provided with an instruction storage module with a depth of n, and the DMA controller can write read data and interpolation data into the n buffers simultaneously according to a data transmission instruction in the instruction storage module, thereby achieving the effect of pipeline data transmission. The following description will be made using exemplary embodiments.
Referring to fig. 5, a flowchart of a method for data transmission according to another exemplary embodiment of the present application is shown. The present embodiment is described by taking the method as an example for a DMA controller, and the method may include the following steps.
In a possible implementation manner, an instruction storage module is arranged in the DMA controller, and the instruction storage module is used for storing a data transmission instruction issued by the CPU chip. Moreover, the instruction storage module adopts a first-in-first-out (FIFO) design, and the depth is related to the number of the buffers in the destination.
And for the received data transmission instruction, the DMA controller acquires the first data transmission instruction from the instruction storage module according to the FIFO principle.
The process of generating and sending the first data read command by the DMA controller may refer to steps 202A and 202B, which is not described herein again in this embodiment.
Since the destination is provided with n buffers, the DMA controller needs to write the data returned by the bus into the corresponding buffer. In a possible implementation manner, the first data transfer instruction further includes a buffer identifier, and the DMA controller determines the buffer to which the first data is to be written according to the buffer identifier.
In some embodiments, the first write address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data lines in a two-dimensional direction, a three-dimensional address offset, and a number of data lines in a three-dimensional direction. Correspondingly, the DMA controller calculates the write data address of each data line according to the data, where the calculation manner of the write data address may refer to the calculation manner of the read data address, and this embodiment is not described herein again.
In some embodiments, the first interpolation address parameter includes a data start address, a data length, a two-dimensional address offset, a number of data lines in a two-dimensional direction, a three-dimensional address offset, and a number of data lines in a three-dimensional direction of the interpolated data. Correspondingly, the DMA controller calculates the interpolation address of each interpolation data line according to the data, where the calculation manner of the interpolation address may refer to the calculation manner of the read data address, and this embodiment is not described herein again.
Illustratively, as shown in fig. 3, the DMA controller may interpolate a three-dimensional data block in three directions of D1, D2, and D3. The DMA controller determines the interpolation address of each interpolation data line according to the data start address of the first interpolation data line 32 in the first interpolation address parameter and the address offset of the other interpolation data lines with respect to the first interpolation data line 32.
In a possible embodiment, the destination register stores interpolation data, and when the DMA controller interpolates data, the DMA controller reads the interpolation data from the destination register. For example, the DMA controller reads the interpolated data from the register of the NPU chip to 0.
In other possible embodiments, the interpolation data may also be indicated by the CPU chip in the data transmission instruction, which is not described herein again.
In a possible implementation manner, after sending a first data read command to a bus, a DMA controller detects whether a second data transmission instruction exists in an instruction storage module, and if so, further obtains the second data transmission instruction, so as to write data and interpolation data into a second buffer of a destination according to the second data transmission instruction, thereby implementing parallel writing of the first data and the second data.
The parameters included in the second data transmission command are similar to those of the first data transmission command, and are not described herein again in this embodiment.
The DMA controller in the embodiment of the present application has a synchronous write function, that is, when first data is not completely written into the first buffer, if second data returned from the bus is received, the DMA controller may write the second data into the second buffer, that is, when the write operation on the first buffer is not completed, the write operations of the first buffer and the second buffer are executed synchronously, so that the transmission bandwidth of the destination and external data is increased, and the effect of pipelined read-write is achieved.
The process of sending the second data read command to the bus by the DMA controller may refer to the process of sending the first data read command to the bus, which is not described herein again in this embodiment.
In step 507, in response to receiving the second data returned by the bus, the second data is written into the second buffer according to the second write address parameter.
Similar to writing the first data into the first buffer, when the second data returned by the bus is received, the DMA controller writes the second data into the second buffer, and the returned data is prevented from blocking the bus.
And step 508, in response to that the second data returned by the bus is not received, writing the second interpolation data into the second buffer according to the second interpolation address parameter.
Similar to the writing of the first interpolation data into the first buffer, when the second data returned by the bus is not received, the DMA controller writes the second interpolation data into the second buffer, and the influence caused by the bus delay and the read data delay is reduced.
In a possible implementation manner, when the first data is completely written and the first interpolation data is completely written, the DMA controller releases the first data transmission instruction in the instruction storage module so as to store a subsequent data transmission instruction sent by the CPU chip, and further perform subsequent data transmission and data interpolation operations.
In this embodiment, by setting at least two buffers at the destination and setting the instruction storage module capable of accommodating at least two instructions in the DMA controller, the DMA controller can synchronously execute read operations of different data when receiving a plurality of data transmission instructions, so that the read data is written into the corresponding buffers, and data interpolation operation is performed in the data writing process, thereby improving transmission bandwidth between the destination and external data, further improving efficiency of subsequent data processing at the destination, and improving work efficiency and performance at the destination.
In an illustrative example, taking a source end as a memory, a destination end as an NPU chip, and two buffers arranged in the NPU chip, and a depth of an instruction storage module in the DMA controller is 2 as an example, a process of the DMA controller transmitting data to the NPU chip is shown in fig. 6.
Step 601, receiving a data transmission instruction sent by the CPU chip, and storing the data transmission instruction in an instruction storage module.
Step 602, a first data transmission instruction in the instruction storage module is executed.
Step 603, calculate the first read data address.
At step 604, a first write data address is calculated.
Step 605, calculate a first interpolation address.
Step 606, a first data read command is sent to the bus according to the first read data address.
Step 607, whether the first data returned by the bus is received.
In step 608, when the first data returned by the bus is received, the first data is written into the first buffer of the NPU chip.
In step 609, when the first data returned by the bus is not received, the first interpolation data is written into the first buffer of the NPU chip.
Step 610, whether all the write operations of the first data are completed or not is performed, if so, step 612 is performed, and if not, step 607 is performed.
Step 611, determine whether all the write operations of the first interpolation data are completed, if so, execute step 612, and if not, execute step 607.
In step 612, if the write operation of the first data and the first interpolation data is completed, the first data transmission instruction is released.
Step 613, when the sending of the first data reading command is completed, executing a second data transmission instruction in the command storage module.
Step 614, calculating the second read data address.
At step 615, a second write data address is calculated.
At step 616, a second interpolated address is calculated.
Step 617, a second data read command is sent to the bus according to the second read data address.
And step 618, whether the second data returned by the bus is received.
Step 619, when receiving the second data returned by the bus, writing the second data into a second buffer of the NPU chip.
And step 620, when the second data returned by the bus is not received, writing the second interpolation data into a second buffer of the NPU chip.
Step 621, whether all the write operations of the second data are completed or not is performed, if so, step 618 is performed, and if not, step 623 is performed.
In step 622, whether all the write operations of the second interpolation data are completed is determined, if yes, step 618 is executed, and if not, step 623 is executed.
Step 623, if the write operation of the second data and the second interpolation data is completed, the second data transmission instruction is released.
At step 624, when the sending of the second data read command is completed, it is detected whether the first data transmission command has been released.
If the data transmission command is released, step 625, the next data transmission command in the command storage module is executed.
Referring to fig. 7, a schematic structural diagram of a DMA controller according to an exemplary embodiment of the present application is shown. The DMA controller includes: a command sending module 701 and a data writing module 702.
The command sending module 701 is configured to obtain a first data transmission instruction, where the first data transmission instruction includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of the first data in a destination end, and the first interpolation address parameter is used to indicate an address of the first interpolation data in the destination end.
The command sending module 701 is configured to send a first data read command to a bus according to the first read address parameter, where the bus is configured to read the first data from a source according to the first data read command.
A data writing module 702, configured to write first data to a destination according to a first write address parameter when receiving the first data returned by the bus;
the data writing module 702 is further configured to write the first interpolation data to the destination according to the first interpolation address parameter when the first data returned by the bus is not received.
In a possible implementation manner, the command sending module 701 is configured to determine, according to the first read address parameter, a read data address corresponding to at least one data line in the first data; and sending at least one first data read command to the bus according to the read data address and the data length of the data line.
In one possible embodiment, the first data is a three-dimensional data block;
the command sending module 701 is further configured to:
determining the read data address of the data line in a first dimension according to the data initial address in the first read address parameter;
determining the read data address of the data row in the second dimension according to the data start address and the two-dimensional address offset in the first read address parameter, wherein the two-dimensional address offset is the address offset between adjacent data rows in the second dimension;
and determining the read data address of the data row in the third dimension according to the data start address and the three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is the address offset between adjacent data rows in the third dimension.
In a possible implementation manner, the destination is provided with n buffers, and the DMA controller includes an instruction storage module with a depth of n, where n is an integer greater than or equal to 2;
a command sending module 701, configured to obtain a first data transmission command from a command storage module;
a data writing module 702, configured to determine, when first data returned by the bus is received, a data writing address of the first data in the first buffer according to the first write address parameter; writing first data into the first buffer according to the write data address;
the data writing module 702 is further configured to determine, when first data returned by the bus is not received, an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter; and writing the first interpolation data into the first buffer according to the interpolation address.
In a possible implementation manner, the command sending module 701 is further configured to obtain a second data transmission instruction from the instruction storage module, where the second data transmission instruction includes a second read address parameter, a second write address parameter, and a second interpolation address parameter; sending a second data reading command to the bus according to the second reading address parameter, wherein the bus is used for reading second data from the source end according to the second data reading command;
the data writing module 702 is further configured to write second data into the second buffer according to the second write address parameter when the second data returned by the bus is received;
the data writing module 702 is further configured to write second interpolation data into the second buffer according to the second interpolation address parameter when the second data returned by the bus is not received;
when the writing operation on the first buffer is not finished, the writing operation of the first buffer and the writing operation of the second buffer are synchronously executed.
In a possible implementation manner, the instruction storage module is further configured to release the first data transmission instruction when the first data is completely written and the first interpolation data is completely written.
The above method embodiment may be referred to for the function implementation process of each module in the DMA controller, and this embodiment is not described herein again.
In one illustrative example, as shown in FIG. 8, DMA controller 800 comprises: an instruction storage module 801, a read address generation module 802, a read command processing module 803, an interpolation address generation module 804, a write address generation module 805, a write command processing module 806, and a data caching module 807. The write command processing module 806 corresponds to the data write module 702 of the DMA controller in fig. 7.
The instruction storage module 801 is configured to store a data transmission instruction issued by the CPU chip, and the instruction storage module 801 stores the instruction in an FIFO manner.
The read address generating module 802 is configured to generate an address of data to be transmitted in the external data memory 820 according to a read address parameter included in an instruction in the instruction storing module 801.
The read command processing module 803 is configured to send a read command to the bus 830 according to the read address generated by the read address generating module 802, so that the bus 830 reads data to be transmitted from the external data storage 820. The read address generation module 802 and the read command processing module 803 correspond to a command transmission module of the DMA controller in fig. 7.
The interpolation address generating module 804 is configured to generate an interpolation address of the interpolation data in the data buffer according to the interpolation address parameter included in the instruction storing module 801.
The write address generating module 805 is configured to generate a data write address of the data to be transmitted in the data buffer according to a write address parameter included in the instruction storing module 801.
The data buffer module 807 is used to buffer the data to be transmitted returned by the bus 830 and provide control signals for writing data and data interpolation to the write command processing module 806.
The write command processing module 806 may process at least two write instructions simultaneously. When the data buffer module 807 is empty, that is, when data returned by the bus is not received, the write command processing module 806 writes the interpolated data into the data buffer according to the interpolated address generated by the interpolated address generating module 804; when the data buffer module 807 is not empty, that is, when data returned by the bus is received, the write command processing module 806 writes the data to be transmitted into the data buffer according to the write address generated by the write address generating module 805.
Moreover, when the destination is provided with a plurality of data buffers, as shown in fig. 8, the destination is provided with a data buffer 1 and a data buffer 2, and the write command processing module 806 synchronously writes data into the data buffer 1 and the data buffer 2 and performs data interpolation in a pipeline manner.
The application also provides an NPU chip, wherein the NPU chip is provided with the DMA controller according to the embodiment. When the CPU chip needs to write data into the NPU chip, a data transmission instruction is sent to a DMA controller in the NPU chip, the DMA controller reads the data according to the instruction, the read data is written into a buffer of the NPU chip, and data interpolation is carried out by utilizing a bus and data reading delay.
Referring to fig. 9, a schematic structural diagram of a computer device according to an exemplary embodiment of the present application is shown. The computer device comprises a CPU chip 910, an NPU chip 920 and a memory 930, wherein the CPU chip 910, the NPU chip 920 and the memory 930 are connected through a bus 940, and the NPU chip 920 is provided with a DMA controller 921 provided by the above embodiments.
As shown in fig. 9, at least two buffers 922 are further disposed in the NPU chip 920, and the DMA controller 921 writes the read data and the interpolated data into the buffers 922, so that the NPU chip 920 processes (e.g., performs a convolution operation) the data in the buffers 922.
Those skilled in the art will recognize that, in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (14)
1. A method of data transfer for a direct memory access, DMA, controller, the method comprising:
acquiring a first data transmission instruction, wherein the first data transmission instruction comprises a first read address parameter, a first write address parameter and a first interpolation address parameter, the first read address parameter is used for indicating an address of first data in a source end, the first write address parameter is used for indicating an address of the first data in a destination end, and the first interpolation address parameter is used for indicating an address of first interpolation data in the destination end;
sending a first data read command to a bus according to the first read address parameter, where the bus is used to read the first data from the source end according to the first data read command;
in response to receiving the first data returned by the bus, writing the first data into the destination terminal according to the first write address parameter;
and in response to the first data returned by the bus is not received, writing the first interpolation data into the target end according to the first interpolation address parameter.
2. The method of claim 1, wherein sending a first data read command to a bus according to the first read address parameter comprises:
determining a read data address corresponding to at least one data line in the first data according to the first read address parameter;
and sending at least one first data read command to the bus according to the read data address and the data length of the data line.
3. The method of claim 2, wherein the first data is a three-dimensional data block;
determining a read data address corresponding to at least one data row in the first data according to the first read address parameter, where the read data address includes at least one of:
determining the read data address of the data line in a first dimension according to a data start address in the first read address parameter;
determining the data reading address of the data line in a second dimension according to a data start address and a two-dimensional address offset in the first reading address parameter, wherein the two-dimensional address offset is an address offset between adjacent data lines in the second dimension;
and determining the read data address of the data row in a third dimension according to a data start address and a three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is an address offset between adjacent data rows in the third dimension.
4. The method according to any one of claims 1 to 3, wherein n buffers are provided at the destination, and the DMA controller includes an instruction storage module having a depth of n, n being an integer greater than or equal to 2;
the acquiring of the first data transmission instruction includes:
acquiring the first data transmission instruction from the instruction storage module;
the writing the first data to the destination according to the first write address parameter in response to receiving the first data returned by the bus includes:
in response to receiving the first data returned by the bus, determining a write data address of the first data in a first buffer according to the first write address parameter;
writing the first data into the first buffer according to the write data address;
the writing the first interpolation data into the destination terminal according to the first interpolation address parameter in response to not receiving the first data returned by the bus comprises:
in response to the first data returned by the bus is not received, determining an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter;
and writing the first interpolation data into the first buffer according to the interpolation address.
5. The method of claim 4, wherein after sending the first data read command to the bus according to the first read address parameter, the method further comprises:
acquiring a second data transmission instruction from the instruction storage module, wherein the second data transmission instruction comprises a second reading address parameter, a second writing address parameter and a second interpolation address parameter;
sending a second data read command to the bus according to the second read address parameter, where the bus is used to read second data from the source end according to the second data read command;
in response to receiving the second data returned by the bus, writing the second data into a second buffer according to the second write address parameter;
in response to that the second data returned by the bus is not received, writing the second interpolation data into the second buffer according to the second interpolation address parameter;
wherein, when the writing operation of the first buffer is not completed, the writing operation of the first buffer and the second buffer is synchronously executed.
6. The method of claim 4, further comprising:
and responding to the first data completion writing and the first interpolation data completion writing, and releasing the first data transmission instruction in the instruction storage module.
7. A DMA controller, characterized in that the DMA controller comprises: the device comprises a command sending module and a data writing module;
the command sending module is configured to obtain a first data transmission instruction, where the first data transmission instruction includes a first read address parameter, a first write address parameter, and a first interpolation address parameter, the first read address parameter is used to indicate an address of first data in a source end, the first write address parameter is used to indicate an address of the first data in a destination end, and the first interpolation address parameter is used to indicate an address of first interpolation data in the destination end;
the command sending module is configured to send a first data read command to a bus according to the first read address parameter, where the bus is configured to read the first data from the source according to the first data read command;
the data writing module is used for writing the first data into the target end according to the first writing address parameter when the first data returned by the bus is received;
and the data writing module is further configured to write the first interpolation data into the destination according to the first interpolation address parameter when the first data returned by the bus is not received.
8. The DMA controller of claim 7,
the command sending module is configured to determine, according to the first read address parameter, a read data address corresponding to at least one data line in the first data; and sending at least one first data read command to the bus according to the read data address and the data length of the data line.
9. The DMA controller of claim 8, wherein the first data is a three-dimensional block of data;
the command sending module is further configured to:
determining the read data address of the data line in a first dimension according to a data start address in the first read address parameter;
determining the data reading address of the data line in a second dimension according to a data start address and a two-dimensional address offset in the first reading address parameter, wherein the two-dimensional address offset is an address offset between adjacent data lines in the second dimension;
and determining the read data address of the data row in a third dimension according to a data start address and a three-dimensional address offset in the first read address parameter, wherein the three-dimensional address offset is an address offset between adjacent data rows in the third dimension.
10. The DMA controller according to any of claims 7 to 9, wherein the destination is provided with n buffers, and the DMA controller includes an instruction storage module having a depth of n, n being an integer greater than or equal to 2;
the command sending module is used for acquiring the first data transmission command from the command storage module;
the data writing module is used for determining a write data address of the first data in a first buffer according to the first write address parameter when the first data returned by the bus is received; writing the first data into the first buffer according to the write data address;
the data writing module is further configured to determine, when the first data returned by the bus is not received, an interpolation address of the first interpolation data in the first buffer according to the first interpolation address parameter; and writing the first interpolation data into the first buffer according to the interpolation address.
11. The DMA controller of claim 10,
the command sending module is further configured to obtain a second data transmission command from the command storage module, where the second data transmission command includes a second read address parameter, a second write address parameter, and a second interpolation address parameter; sending a second data read command to the bus according to the second read address parameter, where the bus is used to read second data from the source end according to the second data read command;
the data writing module is further configured to write the second data into a second buffer according to the second write address parameter when receiving the second data returned by the bus;
the data writing module is further configured to write the second interpolation data into the second buffer according to the second interpolation address parameter when the second data returned by the bus is not received;
wherein, when the writing operation of the first buffer is not completed, the writing operation of the first buffer and the second buffer is synchronously executed.
12. The DMA controller of claim 10,
the instruction storage module is further configured to release the first data transmission instruction when the first data is completely written and the first interpolation data is completely written.
13. A neural network processor NPU chip having a DMA controller as claimed in any one of claims 7 to 12 disposed therein.
14. Computer equipment is characterized by comprising a Central Processing Unit (CPU) chip, an NPU chip and a memory, wherein the CPU chip, the NPU chip and the memory are connected through a bus;
the NPU chip includes a DMA controller as claimed in any one of claims 7 to 12.
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