CN111782438B - An Improved Radiation Hardened Matrix Code Decoding Circuit - Google Patents

Abstract

An improved decoding circuit of radiation-resistant reinforced matrix code is designed to correct the error of the reversed bit of 6-bit data width of memory. The decoding circuit completes decoding error correction of the data bits through two iterations. The core of the decoding circuit is to obtain new check bits and syndromes for the received information bits and redundant bits, and to correct errors in the data by comparing the updated syndromes with the initial syndromes.

Description

An Improved Radiation Hardened Matrix Code Decoding Circuit

technical field

The present invention relates to an improved matrix code decoding circuit for memory radiation hardening.

Background technique

In the environment of space irradiation, high-energy particles can cause multiple bit flips in the memory. The memory has a high probability of soft errors with a data width of 2-5 bits, and a very small probability of data bit flips with a larger width. Generally speaking, the memory can also perform error correction through BCH code, RS code and LDPC codeword with strong error correction capability. However, the high performance of such codewords complicates the circuit implementation. Not only does it need to store the parity check matrix, but the parity check matrix is prone to errors in a radiation environment, resulting in decoding failure. Moreover, the decoding process has a serious delay and the hardware overhead is unbearable.

A two-dimensional matrix code is constructed according to the error characteristics in the radiation environment. The two-dimensional matrix code logically divides a word into a matrix form, which can correct the memory flip of the specified data width. Except for adding redundant circuits, no changes are required. Memory circuit structure. The matrix code circuit is simple to implement, and can better harden the memory against radiation. However, with the reduction of the circuit process size, the memory needs an error correction code with stronger error correction capability.

After searching the DOI number is 10.16708/j.cnki.1000-758X.2018.0070, a matrix code construction method is proposed. The present invention designs an improved decoding circuit, which performs multiple divisions for the inversion of the 6-bit data width and then corrects error, it can correct the 6-bit data width inversion of a single codeword.

翻转时，公式3的状态应当表示为‘1110’。The matrix code logically divides the words of the memory into multiple 4th-order matrices. The matrix code check bit generation formula is as follows, where Equation 3 and Equation 4 perform joint checking on the checked information bits, such as information bits

When flipped, the state of Equation 3 should be represented as '1110'.

（1）

(1)

（2）

(2)

（3）

(3)

（4）

(4)

SUMMARY OF THE INVENTION

The problem to be solved by the present invention is to provide an improved decoding circuit to increase the error correction performance of the matrix code.

In order to achieve the above object, the present invention provides following realization scheme:

，以此得到校正子

:Step 1: Generate 14 new parity bits according to data reception information bits

, so as to get the corrector

:

（5）

(5)

Step 2: Correct some information bits in the information matrix. The error correction formula is as follows:

（6）

(6)

（7）

(7)

与校正子

，根据新的校正子对剩余的信息位中的部分信息位进行纠错：Step 3: Update the corrected information bit to get a new check bit

with syndrome

, and correct some of the remaining information bits according to the new syndrome:

（8）

(8)

（9）

(9)

（10）

(10)

，并以此得到新的校正子

。Step 4: Update the correction result of the information bit in Step 3, and generate a new check bit after the update

, and use this to get a new correction

.

（11）

(11)

可根据更新后的校正子

得到，通过校验状态即可对3区信息位进行纠错：Step 5: Check Status of Remaining Information Bits

According to the updated syndrome

It can be obtained that the error correction of the 3-zone information bits can be performed by checking the status:

（12）

(12)

表示信息位

在指定数据宽度内根据公式3和公式4可能得到校验状态的所有情况的或运算。剩余信息位纠错完成，纠错算法完成译码。in

Indicates information bits

According to Equation 3 and Equation 4, it is possible to obtain the OR operation of all cases of the check state within the specified data width. The error correction of the remaining information bits is completed, and the error correction algorithm completes the decoding.

The excellent effects of the present invention are as follows: the present invention proposes an improved matrix code decoding circuit, the circuit divides the flipped bits through multiple iterations for continuous errors occurring in the information bits; each iteration update will reduce check bit errors The number of bits; thereby increasing the decoding performance of the error correction code without increasing too much power consumption and delay overhead.

Description of drawings

In order to better illustrate the purpose, details and advantages of the present invention, the following accompanying drawings are provided for description:

Fig. 1 is a decoding flow chart;

Figure 2 is the logical matrix arrangement of a word with a bit width of 16 bits

Fig. 3 divides the matrix into 3 parts when the codeword is encoded to the logical matrix;

Figures 4 to 19 are error correction circuits for each information bit of a 16-bit wide word.

Detailed ways

With reference to the codeword logical arrangement structure in Fig. 2, the present invention takes the word of 16bit bit width as a preferred embodiment, and the concrete steps are as follows:

，以此得到校正子

:Step 1: Generate 14 new parity bits according to data reception information bits

, so as to get the corrector

:

（13）

(13)

Step 2: Referring to the position of each partition in Fig. 3, firstly correct some information bits in the 1st area and 2nd area in the information matrix, and the error correction formula is as follows:

（6）

(6)

（7）

(7)

与校正子

，根据新的校正子对图3中1区和2区剩余的信息位进行纠错：Step 3: Update the corrected sum to get the new check digit

with syndrome

, and correct the remaining information bits in areas 1 and 2 in Figure 3 according to the new syndrome:

（8）

(8)

（9）

(9)

（10）

(10)

，并以此得到新的校正子

。Step 4: Update the 3-area check digit for the correction result of the information bit in step 3, and generate a new check digit after the update

, and use this to get a new correction

.

（11）

(11)

可根据更新后的校正子

得到，通过校验状态即可对3区信息位进行纠错：Step 5: Check Status of Remaining Information Bits

According to the updated syndrome

It can be obtained that the error correction of the 3-zone information bits can be performed by checking the status:

（12）

(12)

表示信息位

在6位数据宽度内根据公式3和公式4可能得到校验状态的所有情况的或运算。剩余信息位纠错完成，纠错算法完成译码。in

Indicates information bits

According to formula 3 and formula 4, it is possible to obtain the OR operation of all cases of the check state within the data width of 6 bits. The error correction of the remaining information bits is completed, and the error correction algorithm completes the decoding.

The corresponding circuit of each information bit is shown in Figure 4~19.

The above-detailed embodiments are only used to illustrate the specific implementation of the present invention. It should be noted that the above-described content is only illustrative and not restrictive, but those skilled in the art should understand that different forms and details can be made. changes without departing from the scope defined by the claims of the invention.

Claims (2)

1. An improved radiation-resistant reinforced matrix code decoding circuit is designed to correct the error of the reversed bit of the data width of 6 bits in a memory, and the decoding circuit completes the decoding and error correction of the data bits through two iterations; the core of the decoding circuit is that new check bits and syndromes are obtained from received information bits and redundant bits, and data are corrected through comparison between the updated syndromes and the initial syndromes;

the coding mode of the designed decoding circuit is that a code word is logically divided into n 4-order matrixes, 16 information bits in the matrixes are sequentially arranged, and 14 check bits are obtained from the 16 information bits; the sign bit is defined as:

is an initial information bit;

is an initial check bit;

a check bit generated for receiving the information bit;

calculating a syndrome for the received information bits and the initial check bits;

the check bits are obtained after the first iteration of part of the information bits;

obtaining a new syndrome for the check bit and the initial information bit after the first iteration;

the check bits are obtained after the second iteration of the partial information bits;

obtaining a syndrome for the check bit after the second iteration and the initial information bit;

is the modified information bit;

step 1: data receiving information bits are based on generating 14 new parity bits

Thereby obtaining a syndrome

:

（13）

Step 2: and correcting errors of partial information in the information matrix, wherein the error correction formula is as follows:

（6）

（7）

step 3, updating the corrected information bits to obtain new check bits

And syndrome

And correcting error of part of the remaining information bits according to the new syndrome:

（8）

（9）

（10）

and 4, step 4: updating the correction result of the information bit in the step 3, and generating a new check bit after updating

And thus obtain a new syndrome

；

（11）

And 5: check state of remaining information bits

Can be based on the updated syndrome

And obtaining, the residual information bits can be corrected through the check state:

（12）

wherein

Representing information bits

An or operation of all cases of the check state may be obtained according to equations 3 and 4 within the 6-bit data width; and completing error correction of the residual information bits, and completing decoding by an error correction algorithm.

2. The improved radioresistant reinforced matrix code decoding circuit of claim 1 wherein: the circuit divides the reversed bit through multiple iterations for continuous errors of the information bit, and the error bit of the check bit is reduced through each iteration updating.

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