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CN111769831A - Charge pump for eliminating current mismatch and phase-locked loop circuit - Google Patents

Charge pump for eliminating current mismatch and phase-locked loop circuit Download PDF

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Publication number
CN111769831A
CN111769831A CN202010250017.8A CN202010250017A CN111769831A CN 111769831 A CN111769831 A CN 111769831A CN 202010250017 A CN202010250017 A CN 202010250017A CN 111769831 A CN111769831 A CN 111769831A
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China
Prior art keywords
switch
charge pump
mos tube
current
phase
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CN202010250017.8A
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Chinese (zh)
Inventor
刘钊
颜文
韩洪征
宋永华
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Bouffalo Lab Nanjing Co ltd
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Bouffalo Lab Nanjing Co ltd
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Priority to CN202010250017.8A priority Critical patent/CN111769831A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

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Abstract

The invention discloses a charge pump for eliminating current mismatch and a phase-locked loop circuit, wherein the charge pump comprises a first current source, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, an operational amplifier, a first switch, a second switch, a third switch and a fourth switch; the output end of the first current source is respectively connected with the grid electrode of the first MOS tube, the drain electrode of the first MOS tube and the grid electrode of the third MOS tube, the source electrode of the first MOS tube is grounded, and the source electrode of the third MOS tube is grounded; the drain electrode of the third MOS tube is respectively connected with the second end of the first switch and the second end of the second switch; the drain electrode of the second MOS tube is respectively connected with the first end of the third switch and the first end of the fourth switch, and the grid electrode of the second MOS tube is connected with the output end of the operational amplifier. The charge pump and the phase-locked loop circuit for eliminating the current mismatch can effectively reduce the mismatch of the channel length modulation effect on the current; meanwhile, the charge pump circuit avoids current mismatch caused by current source manufacturing deviation in principle.

Description

Charge pump for eliminating current mismatch and phase-locked loop circuit
Technical Field
The invention belongs to the technical field of electronic circuits, relates to a charge pump, and particularly relates to a charge pump for eliminating current mismatch and a phase-locked loop circuit.
Background
Phase-locked loop circuits are widely used in a variety of circuits, in analog circuits for generating radio frequency clock signals, and in digital circuits for generating reference clocks for digital circuits. The charge pump phase-locked loop becomes a classical phase-locked loop implementation mode due to the characteristics of high performance and low power consumption.
The charge pump is a core module in the charge pump phase-locked loop. The charge pump works together with the phase frequency detector to extract the error signal of the loop, and the error signal is further processed by the loop filter. The performance of the charge pump has a significant impact on the overall performance of the phase-locked loop:
(1) the current mismatch of the charge pump is one of the sources of phase-locked loop output spurs;
(2) the current mismatch of the charge pump can cause the nonlinearity of the phase frequency detector and the charge pump, and the nonlinearity can alias high-frequency noise in a circuit to low frequency, so that the noise characteristic of a phase-locked loop is influenced;
(3) the noise of the charge pump is an important component of the noise of the whole phase-locked loop;
(4) the output voltage range of the charge pump during normal operation determines the input regulation range of the voltage-controlled oscillator.
In a traditional method for solving the current mismatch of the charge pump, the current mismatch of the charge pump mainly has two sources, one is the channel length modulation effect of an MOS (metal oxide semiconductor) tube, and the other is the random mismatch of a current source.
The source of the current mismatch is illustrated below with the charge pump shown in fig. 1. In the PLL circuit, the vctrl voltage cannot be equal to the vbiasp voltage due to the process angle deviation of the VCO circuit, and the drain currents flowing through MN2 and MN3 may be different due to the channel length modulation effect. For the same reason, the drain currents flowing through MP1 and MP2 will be different. While the current through the drains of MN2 and MP1 is the same. If the vctrl voltage is lower than vbiasp voltage, then the drain current through MN3 is less than the drain current through MN2, the drain current through MP2 is greater than the drain current through MP1, and because the drain current through MN2 and the drain current through MP1 are equal, then the drain current through MP2 is greater than the drain current through MN 3.
In the ideal case, if the vctrl voltage and the vbiasp voltage are equal, the channel length modulation effect will not bring about current mismatch at this time. The non-ideal effects of MN2 and MN3 at the time of manufacture can cause current mismatch: manufacturing errors can exist in MN2 and MN3, and even if voltages at four ports of two MOS (metal oxide semiconductor) tubes of MN2 and MN3 are equal, drain currents flowing through MN2 and MN3 can also have mismatch; also, there is a mismatch in drain currents of MP1 and MP 2.
In order to reduce the current setup time of the charge pump, the current steering type charge pump is adopted as the mainstream structure at present, as shown in fig. 2. Where op is an operational amplifier that acts to equalize the vdummy voltage and the vctrl voltage. This configuration also has the two sources of current mismatch discussed above.
There are two general approaches that can be used to reduce the charge pump current mismatch, the principle and advantages of which are discussed separately below.
(1) Current mismatch is reduced with a cascode structure.
Fig. 3 is a charge pump for reducing current mismatch by using a cascode structure, in which MN2 and MN3 current source drains are connected to the sources of the cascode transistors MN4 and MN5, so that the mismatch of MN2 and MN3 drain currents due to a channel length modulation effect is reduced. The advantages of this configuration are mainly two, no extra loop is introduced causing stability problems, no extra noise source is introduced to affect the charge pump noise. The main disadvantages of the structure are three, and the voltage variation range of the vctrl is reduced by adding the common-gate tube; additional bias circuits are required to provide the vcasn voltage and the vcasp voltage; in a deep submicron process, the improvement of the common-source common-gate structure on output impedance is limited, and the improvement degree of current mismatch is limited.
(2) The current mismatch is reduced by means of an operational amplifier.
Fig. 4 is a circuit for reducing charge pump current mismatch using an operational amplifier. In the following circuit, the operational amplifier op1 makes the vdummy voltage and the vctrl voltage approximately equal, and the operational amplifier op2 makes the vbias voltage and the vdummy voltage approximately equal. For current sources MN2 and MN3, the drain voltages are approximately equal, so that for MN2 and MN3, the channel length modulation effect is also approximately the same, and the mismatch introduced by the drain currents of MN2 and MN3 due to the channel length modulation effect is reduced. For the same reason, the current mismatch of MP1 and MP2 is also reduced. And the drain current of MN2 is equal to the drain current of MP1, so that the mismatch of the drain current of MN3 and the drain current of MP2 is reduced. The advantages of this structure are mainly two, no extra voltage margin is consumed, and the current mismatch improvement introduced by the channel length modulation effect is better than that of the cascode structure. The disadvantages of this structure are mainly three, the op2 introduces extra noise, the op2 consumes extra current, and extra compensation capacitor is added to eliminate the instability risk.
In view of the above, there is a need to design a new charge pump to overcome at least some of the above-mentioned disadvantages of the existing charge pumps.
Disclosure of Invention
The invention provides a charge pump and a phase-locked loop circuit for eliminating current mismatch, which can effectively reduce the mismatch of a channel length modulation effect on current.
In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:
a charge pump that eliminates current mismatch, the charge pump comprising: the circuit comprises a first current source, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, an operational amplifier, a first switch, a second switch, a third switch and a fourth switch;
the output end of the first current source is respectively connected with the grid electrode of the first MOS tube, the drain electrode of the first MOS tube and the grid electrode of the third MOS tube, the source electrode of the first MOS tube is grounded, and the source electrode of the third MOS tube is grounded; the drain electrode of the third MOS tube is respectively connected with the second end of the first switch and the second end of the second switch;
the drain electrode of the second MOS tube is respectively connected with the first end of the third switch and the first end of the fourth switch, and the grid electrode of the second MOS tube is connected with the output end of the operational amplifier;
the positive phase input end of the operational amplifier is respectively connected with the second end of the third switch and the first end of the first switch, and the negative phase input end of the operational amplifier is connected with the second end of the fourth switch, the first end of the second switch and the reference voltage.
As an embodiment of the present invention, the charge pump further includes a second current source, and an output end of the second current source is connected to the drain of the second MOS transistor.
In an embodiment of the present invention, the first MOS transistor is an NMOS transistor.
In an embodiment of the invention, the third MOS transistor is an NMOS transistor.
In an embodiment of the invention, the second MOS transistor is a PMOS transistor.
As an embodiment of the present invention, the third MOS transistor is an N current source, and the second MOS transistor is a P current source; the operational amplifier is respectively connected with the third MOS tube and the second MOS tube;
the operational amplifier compares the currents of the P current source and the N current source, the output of the operational amplifier is connected with the second MOS tube, and grid bias voltage is fed back to the second MOS tube, so that the current of the P current source is equal to the current of the N current source.
According to another aspect of the invention, the following technical scheme is adopted:
a phase-locked loop circuit that cancels a current mismatch, the phase-locked loop circuit comprising: the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the feedback loop frequency divider; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the feedback loop frequency divider form a loop.
As an embodiment of the present invention, the phase frequency detector is configured to send a control signal to the charge pump to control operations of the first switch, the second switch, the third switch, and the fourth switch of the charge pump;
the phase frequency detector can control the first switch and the third switch to be opened and the second switch and the fourth switch to be closed, and can control the first switch and the third switch to be closed and the second switch and the fourth switch to be opened at the same time.
As an embodiment of the present invention, after the phase locked loop is locked, the charge pump injects the same charge into the loop filter as the charge pump extracts from the loop filter every reference clock cycle.
The invention has the beneficial effects that: the charge pump and the phase-locked loop circuit for eliminating the current mismatch can effectively reduce the mismatch of the channel length modulation effect on the current; meanwhile, the charge pump circuit avoids current mismatch caused by current source manufacturing deviation in principle. The charge pump does not consume extra voltage margin, and consumes less current than a traditional current steering charge pump.
Drawings
Fig. 1 is a circuit diagram of a conventional charge pump.
Fig. 2 is a circuit diagram of a conventional current-steering charge pump.
Fig. 3 is a circuit diagram of a conventional cascode current steering charge pump.
Fig. 4 is a circuit diagram of a conventional current-steering charge pump.
Fig. 5 is a circuit diagram of a charge pump according to an embodiment of the invention.
FIG. 6 is a circuit diagram of a phase-locked loop circuit according to an embodiment of the present invention.
Fig. 7 is a circuit diagram of a charge pump according to an embodiment of the invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.
The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.
Fig. 5 is a schematic circuit diagram of a charge pump according to an embodiment of the present invention; referring to fig. 5, the charge pump includes: the circuit comprises a first current source, a first MOS transistor MN1, a second MOS transistor MP2, a third MOS transistor MN3, an operational amplifier op3, a first switch sw1, a second switch sw2, a third switch sw3 and a fourth switch sw 4.
The output end of the first current source is respectively connected with the grid electrode of a first MOS tube MN1, the drain electrode of a first MOS tube MN1 and the grid electrode of a third MOS tube MN3, the source electrode of the first MOS tube MN1 is grounded, and the source electrode of the third MOS tube MN3 is grounded; the drain of the third MOS transistor MN3 is connected to the second terminal of the first switch sw1 and the second terminal of the second switch sw2, respectively.
The drain of the second MOS transistor MP2 is connected to the first end of the third switch sw3 and the first end of the fourth switch sw4, respectively, and the gate of the second MOS transistor MP2 is connected to the output end of the operational amplifier op 3;
the non-inverting input end of the operational amplifier op3 is connected to the second end of the third switch sw3 and the first end of the first switch sw1, and the inverting input end of the operational amplifier op3 is connected to the second end of the fourth switch sw4, the first end of the second switch sw2 and a reference voltage.
In an embodiment of the present invention, the first MOS transistor and the third MOS transistor are NMOS transistors, and the second MOS transistor is a PMOS transistor; of course, the types of the first MOS transistor MN1, the second MOS transistor MP2, and the third MOS transistor MN3 may be other types.
As shown in fig. 5, the third MOS transistor is an N current source, and the second MOS transistor is a P current source; the operational amplifier is respectively connected with the third MOS tube and the second MOS tube; the operational amplifier compares the currents of the P current source and the N current source, the output of the operational amplifier is connected with the second MOS tube, and grid bias voltage is fed back to the second MOS tube, so that the current of the P current source is equal to the current of the N current source.
The charge pump provided by the invention can eliminate the current mismatch of the charge pump, and has obvious advantages in voltage margin, current consumed by the charge pump and current matching degree compared with the traditional charge pump.
The core idea of the method is to directly compare the currents of the P current source and the N current source and to make the current of the P current source equal to the current of the N current source by using the negative feedback mechanism of the operational amplifier.
As shown in fig. 5, MN3 in this circuit is an N current source with a gate bias voltage derived from a diode-connected MN 1. The gate bias voltage of the P current source MP2 is provided by the operational amplifier op 3. The operational amplifier in the charge pump circuit can make the vdummy voltage and the vctrl voltage equal.
When the first switch sw1 and the third switch sw3 are closed and the second switch sw2 and the fourth switch sw4 are opened, the drain current idsN3_ a flowing through MN3 and the drain current idsP2_ a flowing through MP2 are equal. The drain voltages of MN3 and MP2 are vdummy.
When the first switch sw1 and the third switch sw3 are turned off and the second switch sw2 and the fourth switch sw4 are turned on, the drain current flowing through MN3 is IdsN3_ b. The difference between IdsN3_ b and IdsN3_ a is that the current mismatch due to channel length modulation effect is due to MN3 drain voltage changing from vdummy to vctrl in both cases. Since the vdummy voltage and the vctrl voltage are equal due to the operational amplifier op3, IdsN3_ b and IdsN3_ a are equal.
Using the same analysis, it can be seen that IdsP2_ b and IdsP2_ a are equal. Therefore, the currents IdsN3_ b and IdsP2_ b are equal when the charge pump works, and mismatch introduced by channel length modulation effect is restrained.
In the conventional charge pump in fig. 1, due to manufacturing variations, the drain currents of MN2 and MN3 have a mismatch, and the drain currents of the first MOS transistor MP1 and the second MOS transistor MP2 also have a mismatch, but in the structure proposed by the present invention, there is no mismatch due to manufacturing variations because there is no such current mirror.
FIG. 7 is a circuit diagram of a charge pump according to an embodiment of the present invention; referring to fig. 7, in an embodiment of the invention, the charge pump further includes a second current source, and an output terminal of the second current source is connected to a drain of the second MOS transistor.
The present invention is also not limited to the P current generation method shown in fig. 5, and the P current source may be provided by the second MOS transistor MP2 and the second current source I0 as shown in fig. 7. The main advantages of this circuit are two, the first can use the current source I0 with less noise to supply current for the charge pump, thus making the whole circuit less noise; after the MP2 current can be reduced second, the current consumed by the op3 can be smaller, which is more suitable for low power consumption applications.
The invention is not limited to the CMOS implementation of the charge pump presented but can also be applied to charge pumps implemented with BJTs. The charge pump provided by the invention is not limited to the NMOS tube connected with the diode for providing grid voltage for the N current source, and the operational amplifier provides grid voltage for the P current source; the grid voltage is provided for the P current source by a PMOS tube connected by a diode, and the grid voltage is provided for the N current source by an operational amplifier. The charge pump proposed by the present invention is not limited to the charge pump used in the phase locked loop.
Fig. 6 is a schematic circuit diagram of a phase-locked loop circuit according to an embodiment of the present invention; in an embodiment of the present invention, the phase-locked loop circuit includes: the phase frequency detector PFD, the charge pump CP, the loop filter LF, the voltage controlled oscillator VCO and the feedback loop frequency divider FBDV; the phase frequency detector PFD, the charge pump CP, the loop filter LF, the voltage controlled oscillator VCO and the feedback loop frequency divider FBDV form a loop.
In an embodiment of the present invention, the phase frequency detector PFD is configured to send a control signal to the charge pump to control operations of the first switch sw1, the second switch sw2, the third switch sw3 and the fourth switch sw4 of the charge pump; the phase frequency detector PFD can control the first switch sw1 and the third switch sw3 to be opened, the second switch sw2 and the fourth switch sw4 to be closed, and simultaneously can control the first switch sw1 and the third switch sw3 to be closed, and the second switch sw2 and the fourth switch sw4 to be opened.
As shown in fig. 6, where up and upb are complementary signals and dn and dnb are complementary signals. After the phase-locked loop is locked, the charge injected into the loop filter by the charge pump is equal to the charge extracted from the loop filter by the charge pump every reference clock period. Suppose the current flowing through the drain of the second MOS transistor MP2 is IdsP2The current flowing through the drain of the third MOS transistor MN3 is IdsN3(ii) a sw4 closure time tpSw2 closure time tnEquation (1) can be obtained:
IdsP2×tp＝IdsN3×tn(1)
the charges injected into and extracted from the vdummy point in each cycle (one cycle time is denoted as T) of the second MOS transistor MP2 and the third MOS transistor MN3 are also equal, so that the formula (2) can be obtained:
IdsP2×(T-tp)＝IdsN3×(T-tn) (2)
from equations (1) and (2), we can obtain: i isdsP2＝IdsN3. This formula shows that the drain current of the third MOS transistor MN3 is equal to the drain current of the second MOS transistor MP2, and according to the above analysis, when the current rudder current is switched, since the drain voltages of the third MOS transistor MN3 and the second MOS transistor MP2 are equal, the current mismatch caused by the channel length modulation effect is also eliminated.
In one embodiment of the invention, after the phase-locked loop is locked, the charge pump injects the charge into the loop filter in each reference clock period and the charge pump extracts the charge from the loop filter.
In the fractional phase-locked loop, in each period, the current source draws and injects unequal amounts of charge to vctrl through the second switch sw2 and the fourth switch sw4 due to the presence of the differential-integral modulator. However, since the vctrl point dc voltage does not change after the loop is locked, the current source draws and injects an equal amount of charge through switches sw2 and sw4 over a plurality of cycles. Since the vdummy point dc voltage also remains constant, the current sources draw and inject equal amounts of charge through sw1 and sw 3. The same conclusions can be drawn as for the integer phase locked loop using the same analytical methods.
In summary, the charge pump and the phase-locked loop circuit for eliminating current mismatch provided by the invention can effectively reduce the mismatch of the channel length modulation effect on the current; meanwhile, the charge pump circuit avoids current mismatch caused by current source manufacturing deviation in principle. The charge pump does not consume extra voltage margin, and consumes less current than a traditional current steering charge pump.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims (9)

1. A charge pump for eliminating current mismatch, the charge pump comprising: the circuit comprises a first current source, a first MOS (metal oxide semiconductor) tube, a second MOS tube, a third MOS tube, an operational amplifier, a first switch, a second switch, a third switch and a fourth switch;
the output end of the first current source is respectively connected with the grid electrode of the first MOS tube, the drain electrode of the first MOS tube and the grid electrode of the third MOS tube, the source electrode of the first MOS tube is grounded, and the source electrode of the third MOS tube is grounded; the drain electrode of the third MOS tube is respectively connected with the second end of the first switch and the second end of the second switch;
the drain electrode of the second MOS tube is respectively connected with the first end of the third switch and the first end of the fourth switch, and the grid electrode of the second MOS tube is connected with the output end of the operational amplifier;
the positive phase input end of the operational amplifier is respectively connected with the second end of the third switch and the first end of the first switch, and the negative phase input end of the operational amplifier is connected with the second end of the fourth switch, the first end of the second switch and the reference voltage.
2. The charge pump of claim 1, wherein:
the charge pump further comprises a second current source, and the output end of the second current source is connected with the drain electrode of the second MOS tube.
3. The charge pump of claim 1, wherein:
the first MOS tube is an NMOS tube.
4. The charge pump of claim 1, wherein:
the second MOS tube is a PMOS tube.
5. The charge pump of claim 1, wherein:
the third MOS tube is an NMOS tube.
6. The charge pump of claim 1, wherein:
the third MOS tube is an N current source, and the second MOS tube is a P current source; the operational amplifier is respectively connected with the third MOS tube and the second MOS tube;
the operational amplifier compares the currents of the P current source and the N current source, the output of the operational amplifier is connected with the second MOS tube, and grid bias voltage is fed back to the second MOS tube, so that the current of the P current source is equal to the current of the N current source.
7. A phase-locked loop circuit for eliminating current mismatch, the phase-locked loop circuit comprising: a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback loop divider as claimed in any one of claims 1 to 5; the phase frequency detector, the charge pump, the loop filter, the voltage-controlled oscillator and the feedback loop frequency divider form a loop.
8. The phase-locked loop circuit of claim 7, wherein:
the phase frequency detector is used for sending control signals for controlling the first switch, the second switch, the third switch and the fourth switch of the charge pump to work to the charge pump;
the phase frequency detector can control the first switch and the third switch to be opened and the second switch and the fourth switch to be closed, and can control the first switch and the third switch to be closed and the second switch and the fourth switch to be opened at the same time.
9. The phase-locked loop circuit of claim 7, wherein:
after the phase-locked loop is locked, the charge injected into the loop filter by the charge pump is equal to the charge extracted from the loop filter by the charge pump every reference clock period.
CN202010250017.8A 2020-04-01 2020-04-01 Charge pump for eliminating current mismatch and phase-locked loop circuit Pending CN111769831A (en)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1481076A (en) * 2002-07-17 2004-03-10 威盛电子股份有限公司 Circuit of phase locked loop of charge pump
US20040257162A1 (en) * 2003-06-23 2004-12-23 Mokeddem Hadj L. Charge pump for eliminating dc mismatches at common drian nodes
CN101414784A (en) * 2007-10-16 2009-04-22 瑞昱半导体股份有限公司 Charge pump
CN101515709A (en) * 2009-03-27 2009-08-26 东南大学 Charge pump of ultralow mismatching phase-locked loop circuit
US20150200588A1 (en) * 2014-01-16 2015-07-16 Qualcomm Incorporated Low-power, self-biasing-capable charge pump with current matching capabilities
US20190165795A1 (en) * 2017-11-29 2019-05-30 International Business Machines Corporation Efficient differential charge pump with sense and common mode control
CN212231424U (en) * 2020-04-01 2020-12-25 博流智能科技（南京）有限公司 Charge pump for eliminating current mismatch and phase-locked loop circuit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1481076A (en) * 2002-07-17 2004-03-10 威盛电子股份有限公司 Circuit of phase locked loop of charge pump
US20040257162A1 (en) * 2003-06-23 2004-12-23 Mokeddem Hadj L. Charge pump for eliminating dc mismatches at common drian nodes
CN101414784A (en) * 2007-10-16 2009-04-22 瑞昱半导体股份有限公司 Charge pump
CN101515709A (en) * 2009-03-27 2009-08-26 东南大学 Charge pump of ultralow mismatching phase-locked loop circuit
US20150200588A1 (en) * 2014-01-16 2015-07-16 Qualcomm Incorporated Low-power, self-biasing-capable charge pump with current matching capabilities
US20190165795A1 (en) * 2017-11-29 2019-05-30 International Business Machines Corporation Efficient differential charge pump with sense and common mode control
CN212231424U (en) * 2020-04-01 2020-12-25 博流智能科技（南京）有限公司 Charge pump for eliminating current mismatch and phase-locked loop circuit

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