CN111769138B - Array substrate and manufacturing method thereof - Google Patents

Abstract

An array substrate includes a stacked flexible substrate, a barrier layer and a buffer layer. The array substrate also includes: a semiconductor layer located on the buffer layer, including two source/drain electrodes and a channel region between the two source/drain electrodes; a first gate insulating layer located on the semiconductor layer and on the buffer layer; a first gate, located on the first gate insulating layer; an interlayer dielectric layer, located on the first gate and the first gate insulating layer, including A groove provided for a gate; two contact holes, formed in the interlayer dielectric layer and the first gate insulating layer, respectively exposing one of the two source/drain electrodes; and a plurality of metal layer, disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layer disposed corresponding to the two contact holes has a first top surface, and corresponds to The metal layer disposed on the groove has a second top surface lower than the first top surface.

Description

Array substrate and manufacturing method thereof

technical field

The present application relates to the field of display devices, in particular to an array substrate and a manufacturing method thereof.

Background technique

In the field of display technology, flat panel display technologies such as Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED) have become the main fields of research and development. Among them, OLED has many advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, nearly 180-degree viewing angle, wide temperature range, and can realize flexible display and large-area full-color display. It is recognized by the industry as the display device with the most development potential.

According to the driving type, OLED can be divided into passive OLED (PMOLED) and active OLED (AMOLED). Among them, AMOLED usually consists of a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) driven backplane and an electroluminescent layer to form a self-luminous component. For AMOLED, low-temperature polysilicon has high electron mobility, so the use of low-temperature polysilicon materials has the advantages of high resolution, fast response speed, high brightness, high aperture ratio, and low energy consumption.

AMOLED generally uses an array substrate including thin film transistors (TFTs), and the manufacture of TFTs involves the use of multiple photo masks. If more photomasks are used, the overall TFT process flow will be longer, more difficult, and more expensive. Therefore, how to reduce the number of photomasks used to manufacture TFTs while keeping the performance of the array unchanged is one of the important directions for cost reduction in subsequent AMOLED manufacturing.

Contents of the invention

The purpose of the present invention is to simplify the process flow of the existing array substrate, reduce manufacturing difficulty, and save cost.

To achieve the above object, the present invention provides an array substrate, including a flexible substrate, a barrier layer and a buffer layer arranged in layers. The array substrate includes:

a semiconductor layer located on the buffer layer, including two source/drain electrodes and a channel region between the two source/drain electrodes;

a first gate insulating layer located on the semiconductor layer and the buffer layer;

The first gate is located on the first gate insulating layer, and the vertical projection of the first gate on the flexible substrate completely falls into the vertical projection of the channel region of the semiconductor layer on the flexible substrate. inside the projection;

an interlayer dielectric layer located on the first gate and the first gate insulating layer, including a groove corresponding to the first gate;

two contact holes, formed in the interlayer dielectric layer and the first gate insulating layer, respectively exposing one of the two source/drain electrodes; and

a plurality of metal layers, disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layers disposed corresponding to the two contact holes fill the contacts The hole has a first top surface, and the metal layer corresponding to the groove has a second top surface lower than the first top surface.

In some embodiments, the plurality of metal layers are formed from the same metal material at the same time.

In some embodiments, a top surface of the interlayer dielectric layer exposed by the groove is lower than a top surface of the interlayer dielectric layer outside the groove.

In some embodiments, the metal layer disposed corresponding to the groove is disposed corresponding to the first gate, and forms a parasitic capacitance with the first gate insulating layer and the first gate.

In some embodiments, the first gate, the first gate insulating layer, the semiconductor layer and the two source/drain constitute a thin film transistor.

In some embodiments, the array base layer also includes:

an organic dielectric layer formed on the plurality of metal layers and the interlayer dielectric layer;

an anode formed on the organic dielectric layer electrically connected to one of the plurality of metal layers; and

The pixel defining layer is formed on the anode and the organic dielectric layer, exposing a part of the anode.

The embodiment of the present application also provides a method for manufacturing an array substrate, the array substrate includes a stacked flexible substrate, a barrier layer, and a buffer layer, which is characterized in that it includes the following steps:

forming a semiconductor layer on the buffer layer;

forming a first gate insulating layer on the semiconductor layer and the buffer layer;

forming a first gate on a portion of the first gate insulating layer;

Forming two source/drain electrodes in the semiconductor layer and a channel region between the two source/drain electrodes, wherein the vertical projection of the first gate on the flexible substrate completely falls into the semiconductor layer said channel region of a layer is in vertical projection on said flexible substrate;

forming an interlayer dielectric layer on the first gate and the first gate insulating layer,

forming two contact holes in the interlayer dielectric layer and the first gate insulating layer, respectively exposing one of the two source/drain electrodes;

forming a groove in the interlayer dielectric layer, the groove being disposed corresponding to the first gate; and

forming a plurality of metal layers on the interlayer dielectric layer, the plurality of metal layers are respectively arranged corresponding to the two contact holes and the grooves, wherein the plurality of metal layers arranged corresponding to the two contact holes The metal layer fills the contact hole and has a first top surface, and the metal layer disposed corresponding to the groove has a second top surface lower than the first top surface.

In some embodiments, the plurality of metal layers are simultaneously formed from the same metal material by patterning through the same photomask and etching process (both not shown).

In some embodiments, the metal layer disposed corresponding to the groove is disposed corresponding to the first gate, and forms a parasitic capacitance with the first gate insulating layer and the first gate.

In some embodiments, the first gate, the first gate insulating layer, the semiconductor layer and the two source/drain constitute a thin film transistor.

In the array substrate and its manufacturing method provided in the embodiment of the present application, by using five photomasks and etching processes, the parasitic capacitance (Cst) in the thin film transistor (TFT) and AMOLED driving circuit is completed, thereby reducing the adjacent Crosstalk between pixels. In the array substrate of the embodiment of the present application, the metal layer of the upper electrode plate serving as a parasitic capacitance and the metal layer electrically connected to the source/drain are deposited simultaneously, and the pattern is completed by the same photomask and etching process (both not shown). Compared with the traditional manufacturing method, it can save at least one layer of insulating layer deposition and an additional photomask and etching process (not shown) and other related processes for separately patterning the upper electrode plate of the parasitic capacitance. implementation. In this way, the array substrate and its manufacturing method provided by the embodiments of the present application have the technical effects of simplifying the process flow, reducing manufacturing difficulty, and saving cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

1-8 are schematic cross-sectional views of each step of the manufacturing method of the array substrate of the present invention.

FIG. 9 is a schematic structural diagram of a display panel of the present invention.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

The following description of the embodiments refers to the accompanying drawings to illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "top", "bottom", etc., are only for reference to the attached drawings. direction. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

This embodiment provides a method for fabricating an array substrate, and the steps are illustrated below with reference to the schematic cross-sectional views of FIGS. 1-8 .

First, referring to FIG. 1 , a flexible substrate 100 is provided, and the material used for the flexible substrate 100 can be polyimide (PI). Specifically, a display area A and an adjacent non-display area B are defined on the flexible substrate 100 . The display area A is, for example, an area where an AMOLED array component is formed, and the non-display area B is, for example, an area where a bending component is formed. Next, a barrier layer 102 and a buffer layer 104 are sequentially deposited on the flexible substrate 110 . Next, a semiconductor layer 106 is formed on the buffer layer 104 in the display area A. Referring to FIG. The semiconductor layer 106 may be a polysilicon layer processed by excimer laser crystallization technology, and patterned through a first photomask and etching process (both not shown).

Next, as shown in FIG. 2, a first gate insulating layer 108 is deposited on the semiconductor layer 106 and the buffer layer 104, a first gate layer is deposited on the first gate insulating layer 108 and penetrates the second A photomask and etching process (both not shown) pattern the first gate layer to form the first gate 110 . Then use the first grid 110 as a hard mask (hard mask), perform a self-alignment process to perform an ion implantation process (ion implantation), and form two sources/ drain 106A, and the semiconductor layer between the two source/drain 106A is used as a channel region. Therefore, the vertical projection of the first gate 110 on the flexible substrate 100 completely falls within the vertical projection of the channel region of the semiconductor layer 106 on the flexible substrate 100.

Next, as shown in FIG. 3, an interlayer dielectric layer 112 is deposited on the first gate insulating layer 108 and the first gate 110, and patterned by a third photomask and etching process (not shown), To form two contact holes (contacthole) 114 and the first opening 116. The two contact holes 114 are formed in the display area A, penetrate through the interlayer dielectric layer 112 and the first gate insulating layer 108 , and respectively expose one of the two source/drain electrodes 106A. The first opening 116 is formed in the non-display area B, penetrates the interlayer dielectric layer 112 and the first gate insulating layer 108, and exposes a part of the buffer layer 104.

Next, as shown in FIG. 4 , a part of the interlayer dielectric layer 112 and the non-display area located on the first gate 110 in the display area A are patterned through a fourth photomask and etching process (not shown). B is a part of the buffer layer 104 and barrier layer 102 exposed by the first deep hole 116, forming a groove 118 in the interlayer dielectric layer 112 in the display area A, and the barrier layer in the non-display area B. A second opening 120 is formed in the layer 102 and the buffer layer 104 . As shown in FIG. 4 , the top surface of the interlayer dielectric layer 112 exposed by the groove 118 is lower than the top surfaces of other interlayer dielectric layers 112 in the display area A. As shown in FIG. In the display area A, the groove 118 is disposed corresponding to the first gate 110 . In the non-display area B, the vertical projection of the second opening 120 on the flexible substrate 100 completely falls within the vertical projection of the first opening 116 on the flexible substrate 100, and the first The opening 116 and the second opening 120 form a stepped structure.

Next, please refer to FIG. 5, deposit a layer of metal material on the interlayer dielectric layer 112, the buffer layer 104 and the barrier layer 102, and fill the plurality of contact holes 114, the The first opening 116 and the second opening 120 are patterned through a fifth photomask and etching process (both not shown), and three metal layers 122 and 124 are formed simultaneously. The metal layer 122 in the display area A further includes a metal contact portion filling the contact hole 114 , and is electrically connected to the source/drain 106A through the metal contact portion. The metal layer 122 is also formed on a part of the barrier layer 102 exposed by the second opening 120 in the non-display area B, and the metal layer 124 is formed on the first grid 110 in the display area A. In the groove 118 of the interlayer dielectric layer 112. In addition, the metal layer 122 disposed corresponding to the two contact holes 114 fills the contact hole 114 and has a first top surface, while the metal layer 124 disposed corresponding to the groove 118 has a surface lower than the second top surface of the first top surface.

Here, as shown in FIG. 5 , the first gate 110 , the first gate insulating layer 108 , the semiconductor layer 106 and the two source/drain 106A in the display area A constitute a thin film transistor. . The metal layer 124 disposed corresponding to the groove 118 is disposed corresponding to the first gate 110, and forms a parasitic capacitance with the first gate insulating layer 108 and the first gate 110.

Next, please refer to FIG. 6, the organic photoresist material is filled in the first opening 116 and the second opening 120 in the non-display area B, and in the metal layer 122, the metal layer 124 and the layers The organic photoresist material is continuously coated on the inter-dielectric layer 112 to form the organic dielectric layer 126. Next, the organic material layer 126 corresponding to one of the metal layers 122 in the display area A is patterned by a sixth photomask and etching process (both not shown), to form a contact hole 128 exposing a part of the metal layer 122.

Next, please refer to FIG. 7, deposit metal on the organic dielectric layer 126 and fill in the contact hole 128, and pass the seventh photomask and etching process (not shown) to form a pattern metal layer 130. The metal layer 130 is formed in the display area A and penetrates through the contact hole 128 to electrically connect the metal layer 122 below it. The metal layer 130 is the anode of the light emitting unit.

Next, please refer to FIG. 8, a pixel defining layer 132 and a supporting layer 136 are formed on the organic material layer 126 and the metal layer 130, and are formed through an eighth photomask and etching process (not shown). The pixel defining layer 132 and the supporting layer 136 are patterned to form a third opening 134 in the pixel defining layer 132 and the supporting layer 136 . The third opening 134 passes through the supporting layer and the pixel defining layer 132 and corresponds to the metal layer 130 . Subsequently, a light-emitting layer and a cathode layer (both not shown) can be further formed in the third opening 134 to complete the fabrication of light-emitting components such as organic light-emitting diodes (OLEDs).

As shown in FIG. 8 , an embodiment of the present invention provides an array substrate 10, which includes a stacked flexible substrate 10, a barrier layer 102, and a buffer layer 104, and a display area A and a non-contact area adjacent to the display area A are defined thereon. Display area B, and in said display area A include:

a semiconductor layer 106, located on the buffer layer 104, including two source/drain electrodes 106A and a channel region between the two source/drain electrodes;

a first gate insulating layer 108 located on the semiconductor layer 106 and the buffer layer 104;

The first gate 110 is located on the first gate insulating layer 108, and the vertical projection of the first gate 110 on the flexible substrate 100 completely falls into the channel region of the semiconductor layer 106 in the In the vertical projection on the flexible substrate 100;

an interlayer dielectric layer 112, located on the first gate 110 and the first gate insulating layer 108, including a groove 118 corresponding to the first gate 110 (see FIG. 5);

two contact holes 114 (please refer to FIG. 5 ), formed in the interlayer dielectric layer 112 and the first gate insulating layer 108, respectively exposing one of the two source/drain electrodes 106A; and

A plurality of metal layers 122 and 124 are disposed on the interlayer dielectric layer 112, corresponding to the two contact holes 114 and the groove 118, wherein the corresponding to the two contact holes 114 are disposed The metal layer 122 fills the contact hole 114 and has a first top surface, and the metal layer 124 disposed corresponding to the groove 118 has a second top surface lower than the first top surface.

In addition, in the display area A, the array substrate 10 further includes:

an organic dielectric layer 126 formed on the plurality of metal layers 122 and 124 and the interlayer dielectric layer 112;

an anode (metal layer 130), formed on the organic dielectric layer 126, electrically connected to one of the plurality of metal layers 122; and

The pixel defining layer 132 is formed on the anode 130 and the organic dielectric layer 126 , exposing a part of the anode (the metal layer 130 ).

In addition, the array substrate 10 provided by the present invention includes a non-display component composed of a metal layer 22, an organic dielectric layer 126, and a pixel definition layer 132 in the non-display area B, so as to be used as For bending components.

In the array substrate and its manufacturing method provided in the embodiments of the present application, by using the five photomasks and etching processes (not shown) shown in FIGS. 1-5 , the thin film transistor (TFT) and AMOLED The parasitic capacitance (Cst) in the driving circuit reduces the problem of crosstalk between adjacent pixels. In the array substrate 10 of the embodiment of the present application, the metal layer 124 serving as the upper electrode plate of the parasitic capacitance can be deposited simultaneously with the metal layer 122 electrically connected to the source/drain 106A and through the same photomask and etching process (neither shown) to complete the patterning, compared with the traditional manufacturing method, at least one layer of insulating layer deposition and an additional photomask and etching process (not shown ) and other related technological processes. In this way, the array substrate and its manufacturing method provided by the embodiments of the present application have the technical effects of simplifying the process flow, reducing manufacturing difficulty, and saving cost.

Please refer to FIG. 9 , the present invention also provides a display device 1, including an array substrate 10, an IC 20, and a printed circuit board 30. in. The array substrate 10 has a non-display area B and a display area A. The main design point of the display device 1 in this embodiment lies in the array substrate 10 , so other components of the display device 1 (such as a base, a frame, or other films for improving optical quality) will not be described in detail here. The above display device 1 can be used in any display device or component with a display function such as wearable devices, mobile phones, tablet computers, televisions, monitors, notebook computers, e-books, e-newspapers, digital photo frames, and navigators. Among them, wearable devices include smart bracelets, smart watches, VR (Virtual Reality, that is, virtual reality) and other devices.

The display panel provided by the present invention and the preparation method thereof have been introduced in detail above. It should be understood that the exemplary embodiments described herein should only be considered as descriptive, and are used to help understand the method and core idea of the present invention, and are not used to limit the present invention. Descriptions of features or aspects within each example embodiment should typically be considered as available for similar features or aspects in other example embodiments. Although the invention has been described with reference to exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present invention intends to cover these changes and modifications within the scope of the appended claims, and any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention .

Claims (8)

1. The array substrate comprises a flexible substrate, a barrier layer and a buffer layer which are arranged in a stacked mode, and is characterized in that the barrier layer is arranged on the flexible substrate;

the semiconductor layer is positioned on the buffer layer and comprises two source/drain electrodes and a channel region positioned between the two source/drain electrodes;

the first gate insulating layer is positioned on the semiconductor layer and the buffer layer;

the first grid electrode is positioned on the first grid insulating layer, and the vertical projection of the first grid electrode on the flexible substrate completely falls into the vertical projection of the channel region of the semiconductor layer on the flexible substrate;

an interlayer dielectric layer on the first gate and the first gate insulating layer, including a groove corresponding to the first gate;

two contact holes formed in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes; and

a plurality of metal layers disposed on the interlayer dielectric layer, corresponding to the two contact holes and the groove, wherein the metal layers disposed corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers disposed corresponding to the groove have second top surfaces lower than the first top surfaces;

wherein the plurality of metal layers are simultaneously formed of the same metal material.

2. The array substrate of claim 1, wherein the top surface of the interlayer dielectric layer exposed by the groove is lower than the top surface of the interlayer dielectric layer outside the groove.

3. The array substrate of claim 1, wherein the metal layer disposed corresponding to the recess is disposed corresponding to the first gate and forms a parasitic capacitance with the first gate insulating layer and the first gate.

4. The array substrate of claim 1, wherein the first gate electrode, the first gate insulating layer, the semiconductor layer, and the two source/drain electrodes constitute a thin film transistor.

5. The array substrate of claim 1, further comprising:

an organic dielectric layer formed on the plurality of metal layers and the interlayer dielectric layer;

an anode formed on the organic dielectric layer and electrically connected to one of the metal layers; and

and the pixel limiting layer is formed on the anode and the organic dielectric layer and exposes a part of the anode.

6. The manufacturing method of the array substrate comprises a flexible substrate, a barrier layer and a buffer layer which are arranged in a stacked mode, and is characterized by comprising the following steps:

forming a semiconductor layer on the buffer layer;

forming a first gate insulating layer on the semiconductor layer and the buffer layer;

forming a first gate electrode on a portion of the first gate insulating layer;

forming two source/drain electrodes in the semiconductor layer and a channel region between the two source/drain electrodes, wherein a vertical projection of the first gate electrode on the flexible substrate completely falls within a vertical projection of the channel region of the semiconductor layer on the flexible substrate;

forming an interlayer dielectric layer on the first gate electrode and the first gate insulating layer,

forming two contact holes in the interlayer dielectric layer and the first gate insulating layer to expose one of the two source/drain electrodes respectively;

forming a groove in the interlayer dielectric layer, wherein the groove is arranged corresponding to the first grid electrode; and

forming a plurality of metal layers on the interlayer dielectric layer, the plurality of metal layers being disposed corresponding to the two contact holes and the groove, respectively, wherein the metal layers disposed corresponding to the two contact holes fill the contact holes and have first top surfaces, and the metal layers disposed corresponding to the groove have second top surfaces lower than the first top surfaces;

the metal layers are formed simultaneously by patterning the same metal material through the same photomask and etching process.

7. The method as claimed in claim 6, wherein the metal layer disposed corresponding to the recess is disposed corresponding to the first gate, and forms a parasitic capacitance with the first gate insulating layer and the first gate.

8. The method of claim 6, wherein the first gate electrode, the first gate insulating layer, the semiconductor layer and the two source/drain electrodes form a thin film transistor.

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