CN111766489B - Reliability test method and system for power semiconductor device - Google Patents
Reliability test method and system for power semiconductor device Download PDFInfo
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Abstract
A reliability test method and a system for a power semiconductor device are provided, wherein the method comprises the following steps: adjusting the temperature of the environment where the power semiconductor device to be tested is located to be a preset test temperature, adjusting the relative humidity setting to be a preset relative humidity, and applying a first preset bias voltage to the power semiconductor device to be tested for a first preset time; and restoring the power semiconductor device to be tested to a normal-temperature static test environment, applying a second preset bias voltage to the power semiconductor device to be tested after the restoration is completed and lasting for a second preset time, measuring the leakage current of the power semiconductor device to be tested to obtain a first leakage current, and determining the fault state of the power semiconductor device to be tested according to the first leakage current. The method can effectively evaluate and test the reliability of the semiconductor device in a high-humidity environment after long-term working, thereby providing a reference for a designer to select a proper device, enabling the product to better meet the field application requirement and ensuring high-reliability application.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a reliability testing method and system for a power semiconductor device.
Background
As a core device of a novel converter, a power semiconductor device (such as an IGBT module) has been widely used in the fields of locomotive traction, heavy-duty driving, power transmission/distribution, and renewable energy power generation (wind power generation and conversion).
Most of these applications are subject to harsh environmental conditions, particularly humidity. The quality and reliability of power semiconductor devices are critical, since these devices are often used in applications where they are exposed or critical. Furthermore, power semiconductor devices play a critical role in applications. At present, the reliability of the power semiconductor device under a humidity environment is generally tested by adopting a classical THB test method. However, practical applications have proven that the existing THB standard test is not suitable under more severe application environment conditions (e.g. tropical regions).
Disclosure of Invention
In order to solve the above problem, the present invention provides a method for testing reliability of a power semiconductor device, the method comprising:
adjusting the temperature of an environment where a power semiconductor device to be tested is located to be a preset test temperature, adjusting the relative humidity setting to be a preset relative humidity, and applying a first preset bias voltage to the power semiconductor device to be tested for a first preset time, wherein the value range of the preset relative humidity is [90%,97% ], and the value range of the first preset bias voltage comprises 40% to 70% of blocking voltage;
and step two, restoring the power semiconductor device to be tested to a normal-temperature static test environment, applying a second preset bias voltage to the power semiconductor device to be tested after the restoration is finished and lasting for a second preset duration, measuring the leakage current of the power semiconductor device to be tested to obtain a first leakage current, and determining the fault state of the power semiconductor device to be tested according to the first leakage current.
According to an embodiment of the invention, before the step one, the method further performs the steps of:
applying a second preset bias voltage to the power semiconductor device to be tested in a normal-temperature static test environment for a second preset duration, and measuring the leakage current of the power semiconductor device to be tested to obtain a second leakage current;
and judging the fault state of the power semiconductor device to be tested according to the second leakage current, and executing the step one when the power semiconductor device to be tested has no fault.
According to an embodiment of the present invention, a value interval of the second preset time period is [2.5min,4min ].
According to an embodiment of the present invention, in the second step, the second preset bias voltage is applied to the collector and the emitter of the power semiconductor device to be tested, and the second preset bias voltage is 75% to 85% of the blocking voltage.
According to one embodiment of the invention, whether the waveform of the first leakage current exceeds the waveform range of the reference leakage current is judged, and if yes, the power semiconductor device to be tested is judged to have a fault.
The invention also provides a test system of the power semiconductor device, which is characterized in that the test system adopts the method as described in any one of the above items to carry out reliability test.
According to one embodiment of the invention, the test system comprises:
the power-on device is connected with the power semiconductor device to be tested and is used for applying bias voltage to the power semiconductor device to be tested;
the power semiconductor device to be tested is arranged in the test box, and the test box is used for adjusting the temperature and the relative humidity of the environment where the power semiconductor device to be tested is located;
the control device is connected with the power-on device and the test box and is used for controlling the running states of the power-on device and the test box;
and the data detection and analysis device is connected with the power semiconductor device to be tested and is used for detecting the leakage current of the power semiconductor device and determining the reliability state of the power semiconductor device to be tested according to the detected leakage current.
According to one embodiment of the invention, the control device is configured to control the test box not to operate in the first test stage and the third test stage, and adjust the temperature of the environment where the power semiconductor device to be tested is located to a preset test temperature and the relative humidity setting to a preset relative humidity in the second test stage, wherein the preset relative humidity is in a value range of [90%,97% ].
According to an embodiment of the present invention, the control device is configured to control the power-on device to apply a second preset bias voltage to the power semiconductor device to be tested for a second preset duration in the first test phase and the third test phase, and apply a first preset bias voltage to the power semiconductor device to be tested for the first preset duration in the second test phase, wherein a voltage value of the first preset bias voltage is smaller than a voltage value of the second preset voltage.
According to an embodiment of the present invention, the data detection and analysis device is configured to determine whether the waveform of the first leakage current detected in the third test stage exceeds the waveform range of the reference leakage current, and if so, determine that the power semiconductor device to be tested has a fault.
The invention provides a brand-new reliability testing method and a brand-new reliability testing system for a power semiconductor device, so as to fully quantify the reliability of the device in long-term operation under a high-humidity environment. The invention is based on the fact that in addition to humidity and temperature, which accelerate the aging of the power semiconductor, voltage is also an important acceleration factor, and more importantly, voltage reflects the actual application conditions. Therefore, the method provided by the invention is used for testing the most critical stress of the IGBT module under high humidity application reliability by increasing the collector-emitter voltage, simultaneously needs to improve the relative humidity during testing to meet the actual conditions, and improves the accuracy of the test result by regulating the duration of initial detection and final detection, so that the product can better meet the field application requirement and ensure high reliable application.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required in the description of the embodiments or the prior art:
FIG. 1 is a schematic block diagram of a test system for power semiconductor devices according to one embodiment of the present invention;
fig. 2 is a schematic flow chart of an implementation of a testing method of a power semiconductor device according to an embodiment of the invention.
Detailed Description
The following detailed description will be given with reference to the accompanying drawings and examples to explain how to apply the technical means to solve the technical problems and to achieve the technical effects. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details or with other methods described herein.
Additionally, the steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions and, although a logical order is illustrated in the flow charts, in some cases, the steps illustrated or described may be performed in an order different than here.
Generally, for high-reliability equipment, the failure rate of the semiconductor device must be ensured to be 100FIT (1FIT = 1x10) 9 Per hour) below. To achieve such reliability, in addition to improving the reliability of the semiconductor device itself, the use conditions are also important in device design. In practice, differences in use can result in failure rates that differ by a factor of 10 or more in actual operation even for modules produced by the same manufacturing process.
The inventor discovers that the power semiconductor devices such as the IGBT module are easily influenced by severe environment (particularly humidity) in the practical application process by analyzing the working principle and the working process of the power semiconductor devices such as the IGBT module.
In particular, in most cases, the converter cabinet cannot ensure that the power semiconductor devices including the IGBT modules are protected from the environmental factors, and the IGBT modules in the converter cabinet are still affected by humidity, especially in the application field of high humidity environment.
At the same time, the converter does not always run under full load conditions, but may also be idle or run under partial load, which means that the temperature rises or falls relatively quickly. Because of this, moisture in the air can penetrate into the IGBT module when the inverter is out of operation for a long time and there is no high temperature to evaporate the moisture in the module. On the other hand, condensation may occur during operation when the temperature drops.
These undesirable operating conditions and humidity variations can adversely affect the semiconductor device, resulting in increased local stress in the termination area of the chip and reduced device blocking capability.
At present, the moisture resistance of the IGBT module is generally verified by adopting a classic THB test method. Wherein, the THB test conditions are as follows: the test temperature is 85 ℃, the relative humidity is 85%, the bias voltage is 80V, and the test time is 1000 hours. The test standard is to measure the leakage current, and the leakage current measured before the test is taken as a reference. If the variation generated by the leakage current exceeds the set range during or after the test, the test is not passed.
In the THB test, a mode of combining humidity, temperature and voltage is adopted, so that the movement of charges or ions in the whole test process is promoted, and the problem of unstable performance caused by the process change or insufficient design space of the IGBT module can be detected.
For this standard test, the engineering community has accumulated several years of experience. However, the inventor has found through research that the bias voltage of 80V applied in the test is much lower than that in the practical application of the current transformer for the high-power semiconductor device. And practical application proves that the existing THB standard test is not suitable for evaluating the reliability of the device working in a high-humidity environment for a long time.
Therefore, the invention provides a novel reliability test method for the power semiconductor device, which can effectively evaluate the reliability of the high-voltage IGBT module which can work in a high-temperature and high-humidity environment for a long time. The premise for improvement of the reliability test method is to fully quantify the application conditions of the device in a severe environment. The inventor finds out through research that besides humidity and temperature, the voltage is an important acceleration factor, and more importantly, the voltage is closely related to practical application conditions. The most critical stress test for the chip termination and its passivation material is to increase the bias voltage to 40-70% of the blocking voltage, and to quantify the application environment of high humidity, to make the chip surface present high humidity, compared with the THB test, it needs enough humidity, when the high humidity condition and high voltage coexist, it will accelerate the electrochemical mechanism of the test process, thus achieving the test purpose.
The reliability test method of the power semiconductor device and the test system for testing the reliability of the power semiconductor device by applying the method provided by the invention evaluate and test the reliability of the semiconductor device (such as an IGBT module) under a high humidity environment for a long time based on the analysis conclusion, thereby providing a reference for a designer to select a proper device, being beneficial to reducing the maintenance cost of the power semiconductor device in the whole life cycle and simultaneously improving the operation reliability of electrical equipment such as a converter and the like.
Fig. 1 shows a schematic structural diagram of a test system of a power semiconductor device provided in this embodiment, fig. 2 shows a schematic implementation flow diagram of a reliability test method of a power semiconductor device provided in this embodiment, and the principles, implementation procedures, and advantages of the test system and the test method of the power semiconductor device provided in this embodiment are further described below with reference to fig. 1 and fig. 2.
As shown in fig. 1, the test system for a power semiconductor device provided in the present embodiment preferably includes: the device comprises a power-on device 101, a test box 102, a control device 103 and a data detection and analysis device 104. The power-on device 101 is connected to the power semiconductor device 100 to be tested, and is used for applying a bias voltage to the power semiconductor device 100 to be tested under the control of the control device 103.
During testing, the power semiconductor device 100 to be tested is placed in a test chamber 102. The test chamber 102 can adjust the temperature and humidity in the cavity under the control of the control device 103, so as to realize the temperature and relative humidity of the environment where the power semiconductor device to be tested is located.
It should be noted that in different embodiments of the present invention, the power semiconductor device 100 to be tested may be a power semiconductor device such as an IGBT module, but may also be other reasonable power semiconductor devices, and the present invention does not limit the specific type of the power semiconductor device 100 to be tested.
The data detection and analysis device 104 is electrically connected to the power semiconductor device 100 to be tested, and is capable of detecting a leakage current of the power semiconductor device 100 and determining a fault state of the power semiconductor device 100 to be tested according to the detected leakage current.
Specifically, as shown in fig. 2, in order to avoid the influence on the final test result due to the existence of the failure of the semiconductor device 100 to be tested before the test, in the present embodiment, optionally, in the first test stage, the control device 103 preferably controls the test chamber 102 to be in a non-operating state, so that the environment where the power semiconductor device 100 to be tested is located is the normal temperature static test environment. In the normal-temperature static test environment, the ambient temperature is room temperature, and the ambient relative humidity is the relative humidity under the standard atmospheric pressure condition.
In the normal temperature static test environment, the control device 103 controls the power-on device 101 to apply a second preset bias voltage to the power semiconductor device 100 to be tested for a second preset duration in step S201. In this process, the data detection and analysis device 104 measures the leakage current of the power semiconductor device 100 to be tested, so as to obtain a second leakage current.
In this embodiment, after obtaining the second leakage current, the data detection and analysis device 104 determines in step S202 whether a waveform of the second leakage current exceeds a waveform range of a preset reference leakage current. If the waveform of the second leakage current exceeds the waveform range of the preset reference leakage current, the data detection and analysis device 104 may determine that the power semiconductor device 100 to be tested has a fault at this time, that is, the power semiconductor device 100 to be tested has a fault before the reliability test is performed, and obviously, the reliability test on the power semiconductor device 100 to be tested is not required.
If the waveform of the second leakage current does not exceed the waveform range of the preset reference leakage current, the data detection and analysis device 104 may determine that the power semiconductor device 100 to be tested has no fault, and may normally perform the reliability test on the power semiconductor device 100 to be tested.
In this embodiment, the predetermined reference leakage current has a waveform range of ± 100% of the nominal value. Of course, in other embodiments of the present invention, the waveform range of the preset reference leakage current may also be configured to be other reasonable ranges, and the present invention is not limited thereto.
In this embodiment, the control device 103 controls the power-on device 101 to apply the second preset bias voltage to the collector and the emitter of the power semiconductor device 100 to be tested. Wherein the second preset bias voltage is preferably 80% of the blocking voltage, and the second preset time period is preferably configured to be 3 minutes.
Of course, in other embodiments of the present invention, the second preset bias voltage and/or the second preset time period may also be configured to be other reasonable values according to actual needs, and the present invention is not limited thereto. For example, in an embodiment of the present invention, the second preset bias voltage may be reasonably set to 75% to 85% of the blocking voltage, and the value of the second preset duration may be reasonably set to a value within a range of [2.5min,4min ].
When it is determined that the power semiconductor device 100 to be tested has no fault in the first test stage, in the second test stage, as shown in fig. 2, the control device 103 controls the test chamber 102 to adjust the temperature in the cavity of the test chamber to the preset test temperature and the relative humidity to the preset relative humidity in step S203, so that the temperature of the environment where the power semiconductor device 100 to be tested is located is the preset test temperature and the relative humidity is set to the preset relative humidity.
In this embodiment, the preset relative humidity is preferably 95%, and the preset temperature is preferably 85 ℃. Of course, in other embodiments of the present invention, the preset relative humidity and/or the preset temperature may be configured to be other reasonable values according to actual needs, and the present invention is not limited thereto. For example, in other embodiments of the present invention, the preset relative humidity may also be [90%,97% ] and the preset temperature may also be a reasonable value configured according to the THB test standard.
After the adjustment of the temperature and the relative humidity of the environment where the power conductor device 100 to be tested is located is completed, as shown in fig. 2, in the present embodiment, the control device 103 controls the power-on device 101 to apply the first preset bias voltage to the power semiconductor device 100 to be tested in step S204 for the first preset time.
Specifically, in the present embodiment, the first preset bias voltage is preferably configured to be 50% of the blocking voltage, and the first preset time period is preferably configured to be 1000 hours. Of course, in other embodiments of the present invention, according to actual needs, the first preset bias voltage and/or the first preset time period may also be configured to be other reasonable values according to actual needs, and the present invention is not limited thereto. For example, in an embodiment of the present invention, the first preset bias voltage may be a reasonable value (e.g., 65%) in a range from 40% to 70% of the blocking voltage, and the first preset time period may be configured as a reasonable value configured according to the THB test standard.
And when the test duration reaches the first preset duration, ending the second test stage. At this time, in the third testing stage, the control device 103 controls the test chamber 102 to stop working in step S205, so that the environment of the power semiconductor device 100 to be tested can be restored to the normal temperature static testing environment.
Subsequently, under the normal temperature static test environment, the control device 103 controls the power-on device 101 to apply a second preset bias voltage to the power semiconductor device 100 to be tested for a second preset duration in step S206. In this process, the data detection and analysis device 104 measures the leakage current of the power semiconductor device 100 to be tested, so as to obtain a first leakage current. In step S207, the data detection and analysis device 104 determines the fault state of the power semiconductor device 100 to be tested according to the first leakage current, so as to implement the reliability test on the power semiconductor device 100 to be tested.
If it is determined that the power semiconductor device 100 to be tested does not have a fault according to the first leakage current, the power semiconductor device 100 to be tested passes the reliability test item; if it is determined that the power semiconductor device 100 to be tested has a failure based on the first leakage current, the power semiconductor device 100 to be tested does not pass the reliability test item.
In this embodiment, the implementation principle and the implementation process of the steps S206 and S207 are the same as those disclosed in the steps S201 and S202, and therefore, detailed descriptions of the steps S206 and S207 are omitted here.
It should be noted that, in other embodiments of the present invention, the control device 103 and the data detection and analysis device 104 may be integrated into the same device according to actual needs, and the present invention is not limited thereto.
As can be seen from the above description, the present invention provides a novel method and system for testing the reliability of a power semiconductor device, so as to fully quantify the reliability of the device in a high humidity environment for a long time. The invention is based on the fact that in addition to humidity and temperature, which accelerate the aging of the power semiconductor, voltage is also an important accelerating factor, and more importantly, voltage reflects the actual application conditions. Therefore, the method provided by the invention is used for testing the most critical stress of the IGBT module under high humidity application reliability by increasing the collector-emitter voltage, simultaneously needs to improve the relative humidity during testing to meet actual conditions, and improves the accuracy of a test result by regulating the duration of initial detection and final detection, so that a product can better meet the field application requirement and ensure high-reliability application.
It is to be understood that the disclosed embodiments of the invention are not limited to the particular structures or process steps disclosed herein, but extend to equivalents thereof as would be understood by those skilled in the relevant art. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
While the foregoing examples have been provided to illustrate the principles of the invention in one or more applications, it will be apparent to those skilled in the art that various changes in form, usage and details of implementation can be made without departing from the principles and concepts of the invention. Accordingly, the invention is defined by the appended claims.
Claims (9)
1. A method for testing the reliability of a power semiconductor device, the method comprising:
adjusting the temperature of an environment where a power semiconductor device to be tested is located to be a preset test temperature, adjusting the relative humidity setting to be a preset relative humidity, and applying a first preset bias voltage to the power semiconductor device to be tested for a first preset time, wherein the value range of the preset relative humidity is [90%,97% ], and the value range of the first preset bias voltage comprises 40% to 70% of blocking voltage;
and step two, restoring the power semiconductor device to be tested to a normal-temperature static test environment, applying a second preset bias voltage to the power semiconductor device to be tested after the restoration is completed and lasting for a second preset duration, measuring the leakage current of the power semiconductor device to be tested to obtain a first leakage current, determining the fault state of the power semiconductor device to be tested according to the first leakage current, judging whether the waveform of the first leakage current exceeds the waveform range of a reference leakage current, and if so, judging that the power semiconductor device to be tested has a fault.
2. The method of claim 1, wherein prior to said step one, the method further performs the steps of:
applying a second preset bias voltage to the power semiconductor device to be tested in a normal-temperature static test environment for a second preset time, and measuring the leakage current of the power semiconductor device to be tested to obtain a second leakage current;
and judging the fault state of the power semiconductor device to be tested according to the second leakage current, and executing the step one when the power semiconductor device to be tested has no fault.
3. The method of claim 1, wherein the second predetermined period of time is [2.5min,4min ].
4. The method according to any of claims 1 to 3, wherein in the second step, the second preset bias voltage is applied to the collector and emitter of the power semiconductor device to be tested, and the second preset bias voltage is 75% to 85% of a blocking voltage.
5. A test system for power semiconductor devices, characterized in that the test system employs the method of any one of claims 1-4 for reliability testing.
6. The test system of claim 5, wherein the test system comprises:
the power-on device is connected with the power semiconductor device to be tested and is used for applying bias voltage to the power semiconductor device to be tested;
the test box is used for adjusting the temperature and the relative humidity of the environment where the power semiconductor device to be tested is positioned;
the control device is connected with the power-on device and the test box and is used for controlling the running states of the power-on device and the test box;
and the data detection and analysis device is connected with the power semiconductor device to be tested and is used for detecting the leakage current of the power semiconductor device and determining the reliability state of the power semiconductor device to be tested according to the detected leakage current.
7. The test system according to claim 6, wherein the control device is configured to control the test chamber not to operate in the first test stage and the third test stage, and to adjust the temperature of the environment in which the power semiconductor device to be tested is located to a preset test temperature and the relative humidity setting to a preset relative humidity in the second test stage, wherein the preset relative humidity is in a range of [90%,97% ].
8. The test system of claim 7, wherein the control device is configured to control the power-on device to apply a second preset bias voltage to the power semiconductor device to be tested for a second preset duration in the first test phase and a third test phase, and to apply a first preset bias voltage to the power semiconductor device to be tested for a first preset duration in the second test phase, wherein a voltage value of the first preset bias voltage is smaller than a voltage value of the second preset voltage.
9. The test system according to any one of claims 7 to 8, wherein the data detection and analysis device is configured to determine whether the waveform of the first leakage current detected in the third test stage exceeds the waveform range of the reference leakage current, and if so, determine that the power semiconductor device to be tested has a fault.
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| CN114893972B (en) * | 2022-04-27 | 2023-12-15 | 上海临港电力电子研究有限公司 | Dehumidification system of power module and control method |
| CN114675119A (en) * | 2022-05-31 | 2022-06-28 | 陕西半导体先导技术中心有限公司 | Semiconductor power device reliability detection box and detection method |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090218684A1 (en) * | 2008-01-25 | 2009-09-03 | Mark Pavier | Autoclave capable chip-scale package |
| CN102393501A (en) * | 2011-10-14 | 2012-03-28 | 哈尔滨工业大学 | MOSFET reliability test analysis system and method thereof |
| CN105158670A (en) * | 2015-10-13 | 2015-12-16 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on leakage current of collector electrode |
| CN106324466A (en) * | 2016-08-08 | 2017-01-11 | 同济大学 | Current transformer IGBT module field fault pre-diagnosis method |
| CN107024649A (en) * | 2017-05-15 | 2017-08-08 | 扬州乔恒电子有限公司 | A kind of IGBT module characteristic aging equipment |
| CN107621599A (en) * | 2017-08-28 | 2018-01-23 | 北京工业大学 | A method for measuring junction temperature change of IGBT in high temperature reverse bias test |
| US20180188197A1 (en) * | 2017-01-05 | 2018-07-05 | Kevin R. Williams | Moisture detecting system and method for use in an igbt or a mosfet |
| CN108344936A (en) * | 2018-01-22 | 2018-07-31 | 无锡昌德微电子股份有限公司 | A kind of test method of power semiconductor |
| CN108562841A (en) * | 2018-06-14 | 2018-09-21 | 山东阅芯电子科技有限公司 | leakage current detection method and device in electronic component environmental aging test |
| CN108594101A (en) * | 2018-04-02 | 2018-09-28 | 重庆大学 | A kind of SiC Mosfet reliabilities and high temperature aging test device |
-
2019
- 2019-03-27 CN CN201910238052.5A patent/CN111766489B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090218684A1 (en) * | 2008-01-25 | 2009-09-03 | Mark Pavier | Autoclave capable chip-scale package |
| CN102393501A (en) * | 2011-10-14 | 2012-03-28 | 哈尔滨工业大学 | MOSFET reliability test analysis system and method thereof |
| CN105158670A (en) * | 2015-10-13 | 2015-12-16 | 中国人民解放军海军工程大学 | IGBT health state monitoring method based on leakage current of collector electrode |
| CN106324466A (en) * | 2016-08-08 | 2017-01-11 | 同济大学 | Current transformer IGBT module field fault pre-diagnosis method |
| US20180188197A1 (en) * | 2017-01-05 | 2018-07-05 | Kevin R. Williams | Moisture detecting system and method for use in an igbt or a mosfet |
| CN107024649A (en) * | 2017-05-15 | 2017-08-08 | 扬州乔恒电子有限公司 | A kind of IGBT module characteristic aging equipment |
| CN107621599A (en) * | 2017-08-28 | 2018-01-23 | 北京工业大学 | A method for measuring junction temperature change of IGBT in high temperature reverse bias test |
| CN108344936A (en) * | 2018-01-22 | 2018-07-31 | 无锡昌德微电子股份有限公司 | A kind of test method of power semiconductor |
| CN108594101A (en) * | 2018-04-02 | 2018-09-28 | 重庆大学 | A kind of SiC Mosfet reliabilities and high temperature aging test device |
| CN108562841A (en) * | 2018-06-14 | 2018-09-21 | 山东阅芯电子科技有限公司 | leakage current detection method and device in electronic component environmental aging test |
Non-Patent Citations (2)
| Title |
|---|
| IGBT基于物理故障的失效分析及电子器件加速寿命模型研究;郭来小;《中国优秀硕士学位论文全文数据库 信息科技辑》;20180915;第2018卷(第09期);全文 * |
| The influence of humidity on the high voltage blocking reliability of power IGBT modules and means of protection;Charalampos Papadopoulos 等;《Microelectronics Reliability》;20180930;全文 * |
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