CN111756381B - A signal amplitude adjustment system implemented by hardware - Google Patents
A signal amplitude adjustment system implemented by hardware Download PDFInfo
- Publication number
- CN111756381B CN111756381B CN202010666909.6A CN202010666909A CN111756381B CN 111756381 B CN111756381 B CN 111756381B CN 202010666909 A CN202010666909 A CN 202010666909A CN 111756381 B CN111756381 B CN 111756381B
- Authority
- CN
- China
- Prior art keywords
- module
- signed
- factor
- amplitude modulation
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/70—Automatic control for modifying converter range
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/661—Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention provides a hardware-implemented signal amplitude regulating system, which belongs to the technical field of electronics, and comprises an upper computer, a parameter communication module, an amplitude modulation factor analysis module, a factor symbolizing module, a signed signal shifting module, a signed bit multiplication module, a signed bit addition module and a DAC module.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a hardware-implemented signal amplitude adjusting system.
Background
The signal amplitude adjustment plays an important role in signal transmission and processing, and a signal receiving end has certain requirements on the signal amplitude or the receiving end needs the signal amplitude adjustment to excite a subsequent circuit. A method with adjustable signal amplitude, wide adjusting range and high adjusting precision is generated.
The DAC is a module for converting digital signals into analog signals by a digital-to-analog converter.
Independent DAC chips, there are typically two chips, serial and parallel control. Such as DAC0832, belongs to the parallel control port; DAC7612 belongs to the serial input port. The serial port includes serial port, I2C, SPI, etc. The parallel port is typically 8 bits or 16 bits. For example DAC0832 belongs to 8-bit parallel control and DAC7612 belongs to SPI port control. The singlechip controls DAC0832,8 control pins are needed, DAC7612 is controlled, 4 SPI pins are needed, direct DAC7612 can be called if an SPI module is arranged in the singlechip, and IO port software can be used for simulation if SPI is not arranged.
And the DAC module controlled by the parallel port occupies more IO ports of the singlechip, and the more the accuracy is, the more the IO ports are needed. For example DAC0832,8 bit control, 8 pins to 0000 0000 output 0V,8 pins to 1111 1111 output 5V, 256 total from 0000 0000 to 1111 1111, so DAC0832 belongs to 8 bit precision, i.e. 5V/256 is approximately equal to 0.02V,0000 0001 outputs 0.02V,0000 0002 outputs 0.04V, steps 0.02V, 8 bit precision is not sufficient if a voltage step of 0.01V is desired to be output.
The current DAC chip generally adopts serial port control, and the most used SPI port is 4-line control no matter 8-bit precision, 10-bit precision, 12-bit precision and 16-bit precision.
But the amplitude modulation precision of the traditional DAC module is not high and the amplitude modulation range is not large.
Disclosure of Invention
In order to solve the technical problems, the invention provides a hardware-implemented signal amplitude adjusting system, which enables the signal amplitude to be adjustable and an amplitude modulation factor communication interface to be configured.
The technical scheme of the invention is as follows:
A hardware-implemented signal amplitude regulation system comprises an upper computer, a parameter communication module, an amplitude modulation factor analysis module, a factor symbolization module, a signed signal shift module, a signed bit multiplication module, a signed bit addition module and a DAC module.
The parameter communication module is respectively connected with the upper computer and the amplitude modulation factor analysis module;
the signed bit multiplication module is respectively connected with a signed signal shift module, a factor symbolization module and a signed bit addition module;
The factor symbolizing module is connected with the amplitude modulation factor analyzing module; the DAC module is connected with the signed bit addition module;
The amplitude modulation factor is set in a digital mode to change the numerical value of the signed digital signal, so that the analog signal output amplitude of the DAC module is regulated.
Further, the method comprises the steps of,
The upper computer can issue parameters through the parameter communication module, and the serial port, the PCIe interface and the USB interface can be realized only by humanized issuing of parameters used by the system.
Further, the method comprises the steps of,
And the parameter communication module analyzes the data transmitted by the communication interface protocol in the amplitude modulation factor analysis module to obtain an amplitude modulation factor. The amplitude modulation factor consists of an amplification factor and a scaling factor.
The more the number of bits of the amplification factor, the wider the amplitude modulation range; the greater the number of bits of the scaling factor, the greater the amplitude modulation accuracy. The amplitude modulation factor acts on the signed signal and it needs to be converted into a signed bit factor at the factor symbolizing module. The signed signal is amplified and scaled by shifting, so that a divider is avoided, and resources are saved.
The symbolizing factor performs a signed bit multiplication operation with the signed signal. And carrying out signed bit addition operation on the effective multiplication module result to obtain an amplitude-modulated digital signal output. The amplitude-modulated digital signal output passes through the DAC module, the amplitude-modulated analog signal is output, and the amplitude modulation precision is determined by the digital input of the DAC, so that the amplitude modulation limit of the DAC module is made up.
The invention has the beneficial effects that
The amplitude modulation factor is set in a digital mode to change the numerical value of the signed digital signal, so that the function of adjusting the output amplitude of the analog signal of the DAC module is achieved. The signal amplitude is regulated from the source of the digital signal, and the defects of low amplitude modulation precision and small amplitude modulation range of the DAC module are overcome. The invention has the characteristics of adjustable signal amplitude, configurable amplitude modulation factor communication interface, high amplitude modulation precision, wide amplitude modulation range, simple and convenient implementation, humanized control and the like, and has wide application prospect.
Drawings
Fig. 1 is a block diagram of the operation of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making any inventive effort based on the embodiments of the present invention are within the scope of protection of the present invention.
The invention relates to a hardware-implemented signal amplitude regulating system, the block diagram of which is shown in figure 1, and which consists of an upper computer, a parameter communication module, an amplitude modulation factor analysis module, a factor symbolizing module, a signed signal shifting module, a signed bit multiplication module, a signed bit addition module and a DAC module.
The upper computer can issue parameters through the parameter communication module, and the serial port, the PCIe interface and the USB interface can be realized only by humanized issuing of parameters used by the system.
And the parameter communication module analyzes the data transmitted by the communication interface protocol in the amplitude modulation factor analysis module to obtain an amplitude modulation factor. The amplitude modulation factor consists of an amplification factor and a scaling factor. The more the number of bits of the amplification factor, the wider the amplitude modulation range; the greater the number of bits of the scaling factor, the greater the amplitude modulation accuracy.
The amplitude modulation factor acts on the signed signal and it needs to be converted into a signed bit factor at the factor symbolizing module. The signed signal is amplified and scaled by shifting, so that a divider is avoided, and resources are saved. The symbolizing factor performs a signed bit multiplication operation with the signed signal. And carrying out signed bit addition operation on the effective multiplication module result to obtain an amplitude-modulated digital signal output.
The amplitude-modulated digital signal output passes through the DAC module, the amplitude-modulated analog signal is output, and the amplitude modulation precision is determined by the digital input of the DAC, so that the amplitude modulation limit of the DAC module is made up.
Illustrating the amplitude modulation scheme:
① The upper computer issues 32bit amplitude modulation factors (hexadecimal C000A 001), wherein the upper computer is 16 bits high (hexadecimal C000) representing the amplification factors, and the lower computer is 16 bits low (hexadecimal A001) representing the scaling factors, and the scaling factors are issued to the parameter communication module through the communication interface.
② The amplitude modulation factor analysis module analyzes the 32bit amplitude modulation factor, which comprises an amplification factor (hexadecimal C000) and a scaling factor (hexadecimal A001).
③ The factor symbolizing module converts each bit in the factor into a signed bit factor for operation with a signed bit signal. The conversion rule is to convert the original unsigned bit factor bit by bit into a 2bit signed bit factor, i.e. bit 0 into bit 00 and bit 1 into bit 01. The amplification factor (hexadecimal C000) is converted into 16 2-bit signed bit factors, here we denote a 1,A2,…,A16, i.e. a 1＝A2＝…＝A14＝2'b00,A15＝A16 =2' b01; the scaling factor (hexadecimal a 001) is converted to 16 2-bit signed bit factors, here denoted by B 1,B2,…,B16, i.e. B 1＝B3＝B16＝2'b01,B2＝B4＝B5＝…＝B15 = 2' B00.
④ Carrying out signed bit shift operation on a signed bit signal X, wherein the signed bit signal X is respectively shifted to the left by 0 bit, 1 bit, 2 bit, … bit and 15 bit, and the shifted signals are respectively represented by X L0,XL1,XL2,…,XL15; the signed bit signals X are respectively right signed shifted by 1 bit, 2 bits, … bits, 16 bits, and the shifted signals are respectively denoted by X R1,XR2,…,XR16.
⑤ In the signed bit multiplication module, the shifted 32 signals are respectively subjected to signed bit multiplication with 32 signed bit factors, namely TL15＝A16*XL15,TL14＝A15*XL14,…,TL1＝A2*XL1,TL0＝A1*XL0;TR1＝B1*XR1,TR2＝B2*XR2,…,TR15＝B15*XR15,TR16＝B16*XR16.
⑥ In the signed bit addition operation module, the product results are summed and accumulated, and a multi-stage summation method of pairwise addition is adopted, so that the time sequence risk of hardware for summing 32 numerical values in one clock period is avoided. The signal output by this example
XDO＝TL15+TL14+TR1+TR3+TR16＝A16*XL15+A15*XL14+B1*XR1+B3*XR3+B16*XR16＝215*X+214*X+X/21+X/23+X/216＝(215+214+2-1+2-3+2-16)X.
⑦ The amplitude-modulated digital signal output X DO is used as the input of a DAC module, digital-to-analog conversion is carried out, and amplitude-modulated analog signal output X AO is output.
⑧ The amplitude modulation range of the method is 0 to (2 15+214+…+20+2-1+2-2+…+2-16) times of that of the original signal, and the amplitude modulation precision is 2 -16 times of that of the original signal. By adopting the method, the amplitude modulation range is wide, and the amplitude modulation precision is high. The above is illustrated with only 16-bit magnification factors, 16-bit magnification factors.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010666909.6A CN111756381B (en) | 2020-07-13 | 2020-07-13 | A signal amplitude adjustment system implemented by hardware |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010666909.6A CN111756381B (en) | 2020-07-13 | 2020-07-13 | A signal amplitude adjustment system implemented by hardware |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111756381A CN111756381A (en) | 2020-10-09 |
| CN111756381B true CN111756381B (en) | 2024-11-12 |
Family
ID=72710895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010666909.6A Active CN111756381B (en) | 2020-07-13 | 2020-07-13 | A signal amplitude adjustment system implemented by hardware |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111756381B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2289529A1 (en) * | 1997-05-17 | 1998-11-26 | Aware, Inc. | Improved method for partially modulating and demodulating data in a multi-carrier transmission system |
| CN103441825A (en) * | 2013-09-02 | 2013-12-11 | 西安电子科技大学 | Self-adaptive interference alignment method for lowering peak value average power ratio |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2003273979A1 (en) * | 2002-11-22 | 2004-06-18 | Telefonaktiebolaget Lm Ericsson (Publ) | Calculation of soft decision values using reliability information of the amplitude |
| US9397689B2 (en) * | 2014-11-24 | 2016-07-19 | Intel Corporation | Interpolator systems and methods |
| CN109359267B (en) * | 2018-10-18 | 2022-11-01 | 哈尔滨工程大学 | Low-complexity multiplier-free fixed-point FFT (fast Fourier transform) optimization method based on dynamic truncation |
| US11146280B2 (en) * | 2018-12-31 | 2021-10-12 | Tektronix, Inc. | Digital signal processing waveform synthesis for fixed sample rate signal sources |
-
2020
- 2020-07-13 CN CN202010666909.6A patent/CN111756381B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2289529A1 (en) * | 1997-05-17 | 1998-11-26 | Aware, Inc. | Improved method for partially modulating and demodulating data in a multi-carrier transmission system |
| CN103441825A (en) * | 2013-09-02 | 2013-12-11 | 西安电子科技大学 | Self-adaptive interference alignment method for lowering peak value average power ratio |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111756381A (en) | 2020-10-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110057477B (en) | Multi-channel alternating/direct current excited signal measuring system for strain type force sensor | |
| CN103607209A (en) | DC imbalance calibration system and DC imbalance calibration method | |
| JP6054732B2 (en) | Semiconductor device and offset voltage correction method | |
| CN108241079B (en) | Electronic load system and parallel operation method | |
| KR100332178B1 (en) | Digital to analog converter and digital to analog converting method | |
| CN107222268B (en) | Power amplifier module intermodulation automatic debugging and testing system and method | |
| CN111756381B (en) | A signal amplitude adjustment system implemented by hardware | |
| CN107066013B (en) | A kind of logging instrument amplifier power supply self-adapting adjusting apparatus | |
| US5072358A (en) | Process controller | |
| CN106547299A (en) | A kind of high precision closed loop reference power source | |
| CN102955486B (en) | High-voltage large-power frequency conversion adjustable constant voltage source | |
| CN102007687A (en) | Amplitude control circuit, polar modulation transmission circuit and polar modulation method | |
| CN218866381U (en) | Voltage regulating circuit and voltage measuring circuit | |
| CN103795415A (en) | High-precision analog to digital conversion method and device based on double-path combination analog to digital converter | |
| CN213751958U (en) | Device for realizing PDM decoding based on FGPA | |
| CN112366999B (en) | Voice coil motor driving circuit and method thereof | |
| CN214310718U (en) | Automatic calibrating device for signal amplifier | |
| CN215768707U (en) | A VHF high precision signal generator | |
| CN111221371A (en) | Analog voltage output method, system, device, and computer-readable storage medium | |
| CN1514660A (en) | Device for modulating radio communication signal | |
| CN113390448B (en) | Method and system for decoding Heidenhain absolute grating ruler | |
| CN206962790U (en) | Intelligent adjustable voltage comparator | |
| CN215813884U (en) | Constant current source device and system | |
| CN215005738U (en) | ADC test circuit of data conversion device verification system | |
| CN112350730A (en) | Digital-to-analog converter and digital-to-analog conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20241015 Address after: 250100 building S02, No. 1036, Langchao Road, high tech Zone, Jinan City, Shandong Province Applicant after: Shandong Inspur Scientific Research Institute Co.,Ltd. Country or region after: China Address before: 250100 First Floor of R&D Building 2877 Kehang Road, Sun Village Town, Jinan High-tech Zone, Shandong Province Applicant before: JINAN INSPUR HIGH-TECH TECHNOLOGY DEVELOPMENT Co.,Ltd. Country or region before: China |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |