CN111755035A - A power chip management system and method - Google Patents

Abstract

The invention relates to the technical field of power supply chips, and discloses a power supply chip management system, comprising a power supply startup/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit and a random access memory protection circuit; the power supply startup The input end of the low voltage detection circuit is connected to the output end of the logic control circuit, the output end of the power start/low voltage detection circuit is connected to the external digital logic circuit/MCU; the output end of the digital logic circuit/MCU is connected to The input terminal of the logic control circuit is connected. The invention achieves the purpose of stable operation of the system by providing a stable voltage for the power supply chip, can also perform low-voltage detection and protect the content in the memory, and also realizes the dynamic control of the voltage conversion by the MCU module in the SOC, which is beneficial to Reduce the power consumption of the system, which is critical for SOC applications in battery-powered embedded systems.

Description

A power chip management system and method

technical field

The invention relates to the technical field of power chips, in particular to a power chip management system and method.

Background technique

With the rapid development of integrated circuit design technology and ultra-deep submicron technology, integrated circuit design has entered the era of system-on-chip (SOC: System-On-Chip), and SOC can integrate embedded microprocessors and memories on a single silicon chip. , interface circuit, clock circuit and other functional modules of digital circuits and analog circuits, which can realize a complete electronic system function. It has the characteristics of high integration and fast clock frequency. Therefore, the emergence of SOC puts forward higher requirements on the power supply that provides energy.

The current power supply chips have many disadvantages. For example, the change of the power supply voltage can cause the digital circuit to fail to meet the timing requirements, so that the system cannot work normally; in addition, when the voltage is too low, the content in the random access memory (RAM) will be damaged. , causing the chip to work abnormally, the power management system is introduced to solve the above problems, especially in the more and more widely used mobile embedded application systems that use batteries as power sources, power management is particularly important, for this reason, we A power chip management system and method are presented.

SUMMARY OF THE INVENTION

In view of the above problems existing in the prior art, the present invention provides a power chip management system and method.

In order to achieve the above purpose, a power chip management system provided by the present invention includes a power start/low voltage detection circuit, a voltage conversion circuit, three drive circuits, a logic control circuit and a random access memory protection circuit; The input end of the voltage detection circuit is connected with the output end of the logic control circuit, the output end of the power start/low voltage detection circuit is connected with the external digital logic circuit/MCU; the output end of the digital logic circuit/MCU is connected with the logic control circuit The input end of the circuit is connected; the logic control circuit and the voltage conversion circuit are bidirectionally connected; the output ends of the voltage conversion circuit are respectively connected with the input ends of the three drive circuits; the drive circuit includes a drive circuit 1 and a drive circuit 2 and drive circuit three, the output end of the drive circuit one is connected to the digital logic circuit/MCU, the output end of the drive circuit two is connected to an external phase-locked loop circuit, and the output end of the drive circuit three is connected to an external memory The input end and output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the driving circuit.

Preferably, the power start/low voltage detection circuit includes a power start circuit and a low voltage detection circuit; the power start circuit includes a power start signal latch circuit, when the external voltage (Vddpll) rises from zero to a certain When the voltage is low, the current reference signal (Iref) and the voltage reference signal (Vstopbias) have initial values. At this time, the signal Por_set is set to a high level, and the power supply start signal latch circuit latches the signal Por_set and generates a The power start signal (Por:PowerOnReset) starts the system, and the external voltage continues to rise. After reaching a certain value, Por_set is set to a low level, but because the power start signal latch circuit latches the initial high level, Therefore, the power start signal remains valid. When the system completes start-up, the logic control circuit generates a power start release signal (Por_relcasc), thereby releasing Por to end the system start-up process; the low-voltage detection circuit consists of a voltage reference circuit, a comparator and a voltage divider Circuit structure, the internal voltage Vregd is the voltage that supplies power to the MCU and RAM in the SOC. When its value drops to a certain value, causing Vx to be less than Vref, a low-voltage event signal is generated to the system to achieve low-voltage restart or interruption of the system. .

Preferably, the driving circuit adjusts the voltage Vnominal provided by the voltage conversion circuit to increase the driving capability to achieve the purpose of driving.

Preferably, the random access memory protection circuit includes a comparator, a control circuit and a switch circuit. When the applied voltage Vstby is normal, Vstby is output from the Vregr terminal through the NMOS transistor and the switch circuit. When the Vstby voltage is lower than Vregd, Vstbyref is Low level, Vregd is output from the Vregr terminal through the switch circuit to achieve the purpose of protecting the memory, and a high-level flag signal Stby_b is generated, indicating that the memory is powered by Vregd.

Preferably, the logic control circuit includes a rewrite circuit, a state control circuit, an analog control circuit, a low voltage logic circuit and a restart control circuit, and the restart control circuit receives a power start signal and a low voltage restart generated by the low voltage logic control circuit signal, generate a control signal to the rewriting circuit, and the rewriting circuit completes the initial value setting of each state control bit when the system starts. If the power is started, after the rewriting is completed, the rewriting circuit receives the system's power start completion signal. Generate the power start release signal to the power start circuit, release the power start signal, the low voltage logic control circuit receives the low voltage event signal, and according to the state control signal provided by the MCU, decides whether the system is to perform a low voltage restart or a low voltage interruption, The state control circuit generates control signals to the analog control circuit and the voltage conversion circuit for state control. The analog control circuit receives the control signals, performs logic conversion, and generates an enable signal for the analog part in the power management chip.

Preferably, the voltage conversion circuit includes auxiliary modules, three oscillators, three feedback circuits and three pump circuits, and under the control of the logic control circuit, dynamically converts the external power supply voltage to provide a stable voltage Vnominal To the drive circuit; the oscillator generates a square wave according to the external voltage signal and the reference voltage generated by the power management chip, and provides it to the pump circuit. The pump circuit receives the square wave from the oscillator and outputs a relatively stable voltage Vnonnina1. To obtain a stable Vominal, Therefore, the oscillator circuit and the pump circuit are required to complement each other so as to finally output a stable voltage. The three feedback circuits monitor the output voltages of the three drive circuits respectively, and transmit the control signal to the oscillator to adjust the working state of the oscillator. In order to achieve the purpose of adjusting the voltage.

A method for a power chip management system, the specific steps are as follows:

(1) The power start circuit is responsible for starting and restarting the power supply, and generating a power start signal;

(2) The low voltage detection circuit monitors the internal power supply (Vregd) and generates a low voltage event signal;

(3) The voltage conversion circuit converts the external power supply under the control of the logic control circuit, and provides the voltage (Vnominal) to the driving circuit. ) provides supply voltage;

(4) The logic control circuit is interrelated with the MCU, the power start-up circuit and the low voltage detection circuit, and controls the voltage conversion circuit to achieve the purpose of determining the working state of the power management module and realize the dynamic management of the power supply;

(5) The random access memory protection circuit chooses between the voltages Vregd and Vstby according to the actual external voltage to provide an uninterruptible power supply for the memory to protect its contents from being damaged.

Compared with the prior art, the power chip management system and method provided by the present invention have the following beneficial effects:

The present invention manages the external power supply through a dynamic method to achieve stable system power supply, can provide stable voltage for the power supply chip, achieve the purpose of stable operation of the system, and can also perform low-voltage detection and protect the content in the memory, in addition, The dynamic control of the voltage conversion by the MCU module in the SOC is also realized, which is beneficial to reduce the power consumption of the system, which is very important for the application of the SOC in the embedded system powered by the battery.

Description of drawings

Fig. 1 is the system schematic diagram of the present invention;

2 is a schematic diagram of a power supply startup circuit of the present invention;

3 is a schematic diagram of a low voltage detection circuit of the present invention;

4 is a schematic diagram of the I-V characteristic curve of the drive circuit of the present invention and its output;

5 is a schematic diagram of a random access memory protection circuit of the present invention;

6 is a schematic diagram of a logic control circuit of the present invention;

FIG. 7 is a schematic diagram of a voltage conversion circuit of the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure.

Please refer to Figure 1-7, a power chip management system, including a power start/low voltage detection circuit, a voltage conversion circuit, three drive circuits, a logic control circuit and a random access memory protection circuit; the power start/low voltage detection circuit; The input end of the circuit is connected with the output end of the logic control circuit, the output end of the power start/low voltage detection circuit is connected with the external digital logic circuit/MCU; the output end of the digital logic circuit/MCU is connected with the output end of the logic control circuit. the input terminal is connected; the logic control circuit is bidirectionally connected with the voltage conversion circuit; the output terminals of the voltage conversion circuit are respectively connected with the input terminals of the three driving circuits; the driving circuit includes a driving circuit 1, a driving circuit 2 and a driving circuit In circuit 3, the output end of the driving circuit 1 is connected to the digital logic circuit/MCU, the output end of the driving circuit 2 is connected to an external phase-locked loop circuit, and the output end of the driving circuit 3 is connected to an external memory; The input end and the output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the driving circuit 1.

The power start/low voltage detection circuit includes a power start circuit and a low voltage detection circuit; the power start circuit includes a power start signal latch circuit, when the external voltage (Vddpll) rises from zero to a certain low voltage , the current reference signal (Iref) and the voltage reference signal (Vstopbias) have initial values. At this time, the signal Por_set is set to a high level, and the power start signal latch circuit is excited to latch the signal Por_set and generate a power start signal. (Por:PowerOnReset), start the system, the external voltage continues to rise, after reaching a certain value, Por_set is set to low level, but since the power start signal latch circuit latches the initial high level, the power supply starts The signal remains valid. After the system is started, the logic control circuit generates a power start release signal (Por_relcasc), thereby releasing the Por to end the system start-up process; the low-voltage detection circuit is composed of a voltage reference circuit, a comparator and a voltage divider circuit. The internal voltage Vregd is the voltage that supplies power to the MCU and RAM in the SOC. When its value decreases to a certain value, causing Vx to be less than Vref, a low-voltage event signal is generated to the system to achieve low-voltage restart or interruption of the system.

The driving circuit adjusts the voltage Vnominal provided by the voltage conversion circuit to increase the driving capability to achieve the purpose of driving. The driving circuit is composed of an NMOS with a source follower connection and a bypass capacitor. Pay attention to the size of the NMOS, so that it always works in the weak inversion region. The biggest advantage of this circuit structure is that a large output current can be obtained without a large input current. For example, to obtain an output current of 50mA, If a bipolar transistor with a gain of 100 is used, an input current of 500uA is required, while if an NMOS transistor operating in the weak inversion region is used, such a large input current is not required. The A-B curve in Figure 4 is close to a straight line, which is The weak inversion region of the NMOS transistor.

The random access memory protection circuit includes a comparator, a control circuit and a switch circuit. When the applied voltage Vstby is normal, Vstby is output from the Vregr terminal through the NMOS tube and the switch circuit. When the Vstby voltage is lower than Vregd, Vstbyref is a low level. , Vregd is output from the Vregr terminal through the switch circuit, to achieve the purpose of protecting the memory, and generate a high-level flag signal Stby_b, indicating that the memory is powered by Vregd.

The logic control circuit includes a rewrite circuit, a state control circuit, an analog control circuit, a low-voltage logic circuit and a restart control circuit, and the restart control circuit receives the power start signal and the low-voltage restart signal generated by the low-voltage logic control circuit, and generates a The control signal is given to the rewriting circuit, and the rewriting circuit completes the initial value setting of each state control bit when the system is started. If it is power-on, after the rewriting is completed, the rewriting circuit receives the power-on completion signal of the system and generates power-on Release the signal to the power start-up circuit, release the power start-up signal, the low-voltage logic control circuit receives the low-voltage event signal, and according to the state control signal provided by the MCU, decides whether the system is to perform a low-voltage restart or a low-voltage interruption. The state control circuit The control signal is generated to the analog control circuit and the voltage conversion circuit for state control, the analog control circuit receives the control signal, performs logic conversion, and generates an enable signal of the analog part in the power management chip.

The voltage conversion circuit includes auxiliary modules, three oscillators, three feedback circuits and three pump circuits. Under the control of the logic control circuit, the external power supply voltage is dynamically converted to provide a stable voltage Vnominal to the drive circuit. ;The oscillator generates a square wave according to the external voltage signal and the reference voltage generated by the power management chip, and supplies it to the pump circuit. The pump circuit receives the square wave from the oscillator and outputs a relatively stable voltage Vnonnina1. To obtain a stable Vominal, oscillation is required. The three feedback circuits monitor the output voltages of the three driving circuits respectively, and transmit the control signal to the oscillator to adjust the working state of the oscillator, and then achieve the adjustment voltage purpose.

A method for a power chip management system, the specific steps are as follows:

(1) The power start circuit is responsible for starting and restarting the power supply, and generating a power start signal;

(2) The low voltage detection circuit monitors the internal power supply (Vregd) and generates a low voltage event signal;

(3) The voltage conversion circuit converts the external power supply under the control of the logic control circuit, and provides the voltage (Vnominal) to the driving circuit. ) provides supply voltage;

(4) The logic control circuit is interrelated with the MCU, the power start-up circuit and the low voltage detection circuit, and controls the voltage conversion circuit to achieve the purpose of determining the working state of the power management module and realize the dynamic management of the power supply;

(5) The random access memory protection circuit chooses between the voltages Vregd and Vstby according to the actual external voltage to provide an uninterruptible power supply for the memory to protect its contents from being damaged.

It should be noted that Vdd in the figure is the external voltage that supplies power to digital logic circuits such as MCU, Vddpll is the external voltage that powers analog circuits such as phase-locked loops, Vddf is the external voltage that powers memory, Vstby is the external voltage that powers memory, and Vregd The internal voltage that powers digital circuits such as MCU after conversion, the internal voltage that Vregpll converts to power analog circuits such as phase-locked loops, the internal voltage that powers memory after Vreg conversion, the internal voltage that powers memory after Vregr conversion, and Stby_b is the memory Flag signal when power is supplied.

The present invention manages the external power supply through a dynamic method to achieve stable system power supply, can provide stable voltage for the power supply chip, achieve the purpose of stable operation of the system, and can also perform low-voltage detection and protect the content in the memory, in addition, The dynamic control of the voltage conversion by the MCU module in the SOC is also realized, which is beneficial to reduce the power consumption of the system, which is very important for the application of the SOC in the embedded system powered by the battery.

The above descriptions are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and the protection scope of the present invention is defined by the claims. Those skilled in the art can make various modifications or equivalent replacements to the present invention within the spirit and protection scope of the present invention, and such modifications or equivalent replacements should also be regarded as falling within the protection scope of the present invention.

Claims (7)

1. A power chip management system is characterized by comprising a power starting/low voltage detection circuit, a voltage conversion circuit, three driving circuits, a logic control circuit and a random access memory protection circuit;

the input end of the power supply starting/low voltage detection circuit is connected with the output end of the logic control circuit, and the output end of the power supply starting/low voltage detection circuit is connected with an external digital logic circuit/MCU;

the output end of the digital logic circuit/MCU is connected with the input end of the logic control circuit;

the logic control circuit is connected with the voltage conversion circuit in a bidirectional way;

the output end of the voltage conversion circuit is respectively connected with the input ends of the three driving circuits;

the driving circuit comprises a first driving circuit, a second driving circuit and a third driving circuit, wherein the output end of the first driving circuit is connected with the digital logic circuit/MCU, the output end of the second driving circuit is connected with an external phase-locked loop circuit, and the output end of the third driving circuit is connected with an external memory;

the input end and the output end of the random access memory protection circuit are respectively connected with the logic control circuit and the external random access memory, and the input end of the random access memory protection circuit is connected with the first driving circuit.

2. The power chip management system according to claim 1, wherein the power on/low voltage detection circuit comprises a power on circuit and a low voltage detection circuit;

the Power supply starting circuit comprises a Power supply starting signal latch circuit, when an external voltage (Vddpall) rises from zero to a certain low voltage, a current reference signal (Iref) and a voltage reference signal (Vstopbias) have initial values, at the moment, a signal Por _ set is placed at a high level, the Power supply starting signal latch circuit is stimulated to latch the signal Por _ set and generate a Power supply starting signal (Por: Power On Reset), the system is started, the external voltage continues rising, after a certain value, the Por _ set is placed at a low level, but the Power supply starting signal latch circuit latches the initial high level, so that the Power supply starting signal is kept effective, and after the system is started, a logic control circuit generates a Power supply starting release signal (Por _ realasc), so that the system starting process is finished by releasing Por;

the low-voltage detection circuit is composed of a voltage reference circuit, a comparator and a voltage division circuit, wherein the internal voltage Vregd is a voltage for supplying power to an MCU and an RAM in the SOC, and when the value of the internal voltage Vregd is reduced to a certain value, Vx is smaller than Vref, a low-voltage event signal is generated and is sent to a system, and low-voltage restart or interruption of the system is realized.

3. The power management system of claim 1, wherein the driving circuit adjusts a voltage Vnominal provided by the voltage converting circuit to increase a driving capability, so as to achieve a driving purpose.

4. The power chip management system of claim 1, wherein the ram protection circuit comprises a comparator, a control circuit and a switch circuit, when the applied voltage Vstby is normal, the Vstby is outputted from the Vregr terminal through the NMOS transistor and the switch circuit, when the voltage of Vstby is lower than Vregd, the Vstbyref is low, the Vregd is outputted from the Vregr terminal through the switch circuit, thereby achieving the purpose of protecting the memory, and a high flag signal Stby _ b is generated to indicate that the memory is supplied with Vregd.

5. The power management chip system of claim 1, wherein the logic control circuit comprises a rewrite circuit, a status control circuit, an analog control circuit, a low voltage logic circuit, and a restart control circuit, the restart control circuit receives a power enable signal and a low voltage restart signal generated by the low voltage logic control circuit, generates a control signal to the rewrite circuit, the rewrite circuit sets the initial values of the status control bits during system start, if the power is on, the rewrite circuit receives the power enable complete signal of the system after the completion of the rewrite, generates a power enable release signal to the power enable circuit, releases the power enable signal, the low voltage logic control circuit receives the low voltage event signal, and determines whether the system is performing low voltage restart or low voltage interrupt according to the status control signal provided by the MCU, the state control circuit generates control signals to the analog control circuit and the voltage conversion circuit to carry out state control, and the analog control circuit receives the control signals to carry out logic conversion and generate enable signals of an analog part in the power management chip.

6. The power chip management system according to claim 1, wherein the voltage conversion circuit comprises an auxiliary module, three oscillators, three feedback circuits and three pump circuits, and dynamically converts the external power voltage under the control of the logic control circuit to provide a stable voltage Vnominal to the driving circuit;

the oscillator generates square waves according to an external voltage signal and reference voltage generated by a power management chip and provides the square waves to the pump circuit, the pump circuit receives the square waves from the oscillator and outputs relatively stable voltage Vnnina 1, and in order to obtain stable Vominal, the oscillator circuit and the pump circuit are required to complement each other so as to finally output stable voltage, the three feedback circuits respectively monitor the output voltages of the three driving circuits, and transmit control signals to the oscillator to adjust the working state of the oscillator, so that the purpose of adjusting the voltage is achieved.

7. The method of claim 1, wherein the method comprises the following steps:

(1) the power supply starting circuit is responsible for starting and restarting a power supply and generating a power supply starting signal;

(2) the low voltage detection circuit monitors an internal power supply (Vregd) and generates a low voltage event signal;

(3) the voltage conversion circuit converts an external power supply under the control of the logic control circuit, provides voltage (Vnominal) to the driving circuits, and the three driving circuits respectively provide power supply voltage for an internal memory, a phase-locked loop and a Microcontroller (MCU) in the power supply chip;

(4) the logic control circuit is mutually associated with the MCU, the power supply starting circuit and the low voltage detection circuit to control the voltage conversion circuit, so that the aim of determining the working state of the power supply management module is fulfilled, and the dynamic management of the power supply is realized;

(5) the random memory protection circuit selects between the voltage Vregd and Vstby according to the condition of the external actual voltage, and provides an uninterrupted power supply for the memory to protect the content from being damaged.

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