CN111740598B - A low-power load current detection circuit for PWM DC-DC converters - Google Patents
A low-power load current detection circuit for PWM DC-DC converters Download PDFInfo
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- CN111740598B CN111740598B CN202010627127.1A CN202010627127A CN111740598B CN 111740598 B CN111740598 B CN 111740598B CN 202010627127 A CN202010627127 A CN 202010627127A CN 111740598 B CN111740598 B CN 111740598B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of AC or of pulses
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc-Dc Converters (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
The invention requests to protect a low-power-consumption load current detection circuit applied to a PWM DC-DC converter, and belongs to the technical field of microelectronics. The device comprises a peak current sensing module, a sampling and holding circuit, an analog-to-digital conversion module and the like. The invention adopts a peak current detection module, a sampling holding circuit and an analog-to-digital conversion module, wherein the input end of the peak current detection module is connected to the drain of a follow current tube to be detected through a switch tube, the output end of the peak current detection module is connected with the input end of the sampling holding circuit, and the output end of the sampling holding circuit is connected with the input end of the analog-to-digital conversion circuit. The sampling hold circuit obtains a stable peak current signal through a switch capacitor, converts the stable peak current signal into a digital signal VS [0:3] through an analog-to-digital conversion module, and shows the change of load current through the change of the VS [0:3] signal.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and relates to a design of a load current detection circuit applied to PWM DC-DC.
Background
A Load Current Detection (Load Current Detection) circuit in a DC-DC converter is often used to monitor Load Current changes, and the Load Current Detection circuit is a basic circuit module in a Current control mode or a voltage control mode of a multi-modulation mode. For the convenience and stability of the control module processing, it is also desirable that the load current variation sampled by the load current detection circuit can be converted into a digital signal.
Common Current Detection methods of the switching power converter include Peak Current Detection (Peak Current Detection) and Average Current Detection (Average Current Detection). Peak current detection is a detection means for reflecting the magnitude of the load current by detecting the peak or the valley of the current flowing through the power transistor, and is also the most common method. The average current detection is a method for reflecting the magnitude of the load current by detecting the voltage change at two ends of the inductor and using the average value of the voltage change, and has the functions of smoothing and relaxing a sampling signal. In contrast, peak current detection reflects the change of load current by detecting the peak value of the current of the power follow current tube, and can realize on-chip sampling of Buck (Buck), Boost (Boost) and Buck-Boost (Buck-Boost) DC-DC load current.
The peak current detection is to directly detect the current change of the power current tube, so the vibration amplitude of the sampling signal is large, the subsequent control circuit is inconvenient to process, and no matter the power current tube is in an open or closed state, the detection circuit is used for detecting, and unnecessary power consumption is generated. Therefore, it becomes a hot point to study how to make the sampled peak current signal become a stable processable signal and reduce the power consumption of the detection circuit.
As shown in fig. 1, the conventional peak current detection circuit is also from VSWThe difference is that the traditional peak current detection circuit is used for a current mode control loop and needs an additional compensation circuit, the traditional peak current detection circuit is applied to a voltage mode control loop, and the problem to be solved is how to obtain a stable current sampling signal and facilitate subsequent processing while the stable signal is obtained by sampling.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A low power consumption load current detection circuit applied to a PWM DC-DC converter is provided. The technical scheme of the invention is as follows:
a low-power-consumption load current detection circuit applied to a PWM DC-DC converter is connected with a voltage conversion core circuit, and comprises: the constant current detection circuit comprises a peak current detection module (1), a sampling and holding circuit (2) and an analog-to-digital conversion module (3), wherein the input end of the peak current detection module (1) is connected to a drain stage of a follow current tube to be detected through a switch tube, then the output end of the peak current detection module (1) is connected with the input end of the sampling and holding circuit (2), the output end of the sampling and holding circuit (2) is connected with the input end of the analog-to-digital conversion circuit (3), and the sampling and holding circuit obtains a stable peak current signal through a switch capacitor. The peak current detection module (1) is used for detecting the current peak value on the power follow current PMOS pipe M1 in real time, converting the current peak value into a voltage signal and outputting the voltage signal to the sampling hold circuit (2); the sampling hold circuit (2) is used for sampling and holding the peak current signal detected by the peak current detection module to obtain a flat voltage signal so as to facilitate comparison by a comparator; the analog-to-digital conversion module (3) is used for converting the voltage signal output by the sampling and holding circuit into a digital electric signal and providing the digital electric signal to a subsequent logic circuit for processing.
Further, the peak current detection module (1) comprises: PMOS tube M3, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M7, NMOS tube M4, NMOS tube M9, NMOS tube M10, NMOS tube M11, resistor RsenseThe source of PMOS tube M3 is connected with the drain of power follow current PMOS tube M1 and the drain of power follow current NMOS tube M2, the source of PMOS tube M5 is connected with power input VDD, the grid of M5 is connected with the grid of power follow current PMOS tube M1 and the grid of PMOS tube M6, the drain of M5 is connected with the drain of PMOS tube M3 and the source of M7, the source of PMOS tube M6 is connected with power VDD, the drain of M6 is connected with the source of PMOS tube M7 and the drain of NMOS tube M11, the grid of PMOS tube M7 is connected with the drain of M7 and the grid of PMOS tube M8, the drain of PMOS tube M8 is connected with the drain of NMOS tube M10 and the grid of NMOS tube M11, the grid and drain of NMOS tube M4 are connected with the current source output, the grid and drain of NMOS tube M9 are connected with the grid of NMOS tube M10, the grid of M4 and M9 and the source of M10 are connected with the source of NMOS tube M11, and the resistor of NMOS tube GND are connected with the NMOS tube GNDsenseIs connected to the input of the sample-and-hold circuit, RsenseThe other end of the power freewheeling PMOS transistor M1 stops detecting when it is turned off.
Further, the sample hold circuit (2) comprises a transmission gate PASS and a capacitor CsenseWherein the input of the transmission gate PASS is connected with the output of the peak current detection, and the output of the transmission gate PASS is connected with the capacitor VsenseThe clock control end of the PASS gate is connected with the grid electrode of the power follow current PMOS tube M1, the peak value is kept unchanged at the peak value of the sampling current signal until the next power follow current PMOS tube is opened again, and a stable peak current sampling signal is output in the clock period of the power follow current PMOS tube being turned off.
Further, the analog-to-digital conversion module (2) includes dynamic comparators CMOP1, COMP2, COMP3, COMP4, and voltage dividing resistors R1, R2, R3, R4, and R5, wherein four positive electrode inputs of the dynamic comparators CMOP1, COMP2, COMP3, and COMP4 are connected to an output of the sample-and-hold circuit, the R1 to R5 are connected to negative electrode inputs of the dynamic comparators COMP1 to COMP4 after voltage division by series connection, the four dynamic comparisons perform comparison operation when the power freewheeling PMOS transistor is turned off, and four inputs of the dynamic comparators COMP1 to COMP4 constitute a four-bit signal VS [0:3 ].
Further, a switching signal VCP controls the opening and closing of a power follow current PMOS tube M1, a PMOS tube M5, a PMOS tube M6 and a transmission gate PASS, when the power follow current PMOS tube M1 is opened, the PMOS tubes M5 and M6 and the transmission gate PASS are synchronously opened to detect and sample load current, when the power follow current PMOS tube is closed, the PMOS tubes M5 and M6 are also closed at the same time to avoid extra power consumption, the transmission gate PASS is closed at the same time, and a capacitor C is closedsenseObtaining and holding the sampled peak current signal, and comparing the output VS [0 ] of the dynamic comparators COMP 1-COMP 4 when the power freewheeling PMOS transistor M1 is closed]～VS[3]Digital signal VS [0:3] forming a four-bit]When VS (VS [0 ]],VS[1],VS[2],VS[3]) When the signal of (a) goes through the step-wise change of VS (0000) → VS (0001) → VS (0011) → VS (0111) → VS (1111), it indicates that the load current is gradually increasing, and this realizes the process of digitizing the detected load current.
Furthermore, the PMOS tubes M5 and M6 are in a deep linear region during the sampling detection, and the resistance values thereof are
In the formula upFor hole mobility, CoxIs the gate oxide capacitance per unit area,
is the width-length ratio of PMOS transistor M5 or PMOS transistor M6, VDD is the power supply input voltage, VTH,PThreshold voltages of M5, M6; the current of the circuit branch in which M5 and M6 are located during the sampling detection period can be expressed as
Due to RONIs a constant value during sample detection, so IDWill follow VSWIs linearly varied, finally by RsenseReflected as a linear change in the voltage signal.
The invention has the following advantages and beneficial effects:
the invention provides a load current detection circuit applied to a PWM DC-DC converter, and aims to solve the problems that the amplitude of vibration of a sampling signal detected by a peak current is too large, the subsequent control circuit is inconvenient to process, and the detection circuit detects whether a power follow-up tube is in an open or closed state, unnecessary power consumption is generated, and the like.
The innovation point of the invention is that the transmission gate PASS and the capacitor C are passedsenseThe combination of (1) realizes a switch sampling circuit and converts the sampled current signal into a more manageable and stable digital signal through four dynamic comparators to reflect the change of the load current. The switching signal VCP is used to control the current detection circuit to be turned on and off to reduce unnecessary loss. The switching signal VCP controls the opening and closing of the power freewheeling PMOS transistor M1, the PMOS transistor M5, the PMOS transistor M6, and the PASS gate PASS. When the power follow current PMOS tube M1 is opened, the PMOS tubes M5 and M6 and the transmission gate PASS are synchronously opened to detect and sample load current, when the power follow current PMOS tube is closed, the PMOS tubes M5 and M6 are also closed simultaneously to avoid extra power consumption, the transmission gate PASS is closed simultaneously, and the capacitor C is closedsenseObtaining and holding the sampled peak current signal, and comparing the output VS [0 ] of the dynamic comparators COMP 1-COMP 4 when the power freewheeling PMOS transistor M1 is closed]～VS[3]Digital signal VS [0:3] forming a four-bit]When VS (VS [0 ]],VS[1],VS[2],VS[3]) When the signal of (b) goes through a stepwise change of VS (0000) → VS (0001) → VS (0011) → VS (0111) → VS (1111), it indicates that the load current is gradually increasing.
Drawings
FIG. 1 is a block diagram of a conventional PWM DC-DC system;
FIG. 2 is a schematic diagram of a load current detection circuit applied to a PWM DC-DC converter according to a preferred embodiment of the present invention;
FIG. 3 is a simulation diagram of the output of the sample-and-hold circuit of the load current detection circuit applied to the PWM DC-DC converter according to the preferred embodiment of the present invention;
fig. 4 is a simulation diagram of the overall output function of the load current detection circuit applied to the PWM DC-DC converter according to the preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail and clearly with reference to the accompanying drawings. The described embodiments are only some of the embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
as shown in FIG. 1, which is a block diagram of a PWM Buck DC-DC system, a power follow current PMOS transistor M1 and a power follow current NMOS transistor M2 are used as follow current transistors of the Buck DC-DC, VSWThe sampling signal as the peak current is connected to the input of the current detection circuit (dashed box). The specific structure of the load current detection circuit is shown in fig. 2, and the load current detection circuit comprises a peak current detection module (i), a sample-and-hold circuit (ii) and an analog-to-digital conversion module (iii), wherein the input end of the peak current detection module is connected to the drain of the follow current tube to be detected through a switch tube, the output end of the peak current detection module is connected with the input end of the sample-and-hold circuit, and the output end of the sample-and-hold circuit is connected with the input end of the analog-to-digital conversion circuit. The sample-and-hold circuit obtains a stable peak current signal by switching a capacitor. The switching signal VCP controls the opening and closing of the power freewheeling PMOS transistor M1, the PMOS transistor M5, the PMOS transistor M6, and the PASS gate PASS. When the power follow current PMOS tube M1 is opened, the PMOS tubes M5 and M6 and the transmission gate PASS are synchronously opened to detect and sample load current, when the power follow current PMOS tube is closed, the PMOS tubes M5 and M6 are also closed simultaneously to avoid extra power consumption, the transmission gate PASS is closed simultaneously, and the capacitor C is closedsenseObtaining and holding the sampled peak current signal, and comparing the output VS [0 ] of the dynamic comparators COMP 1-COMP 4 when the power freewheeling PMOS transistor M1 is closed]～VS[3]Digital signal VS [0:3] forming a four-bit]When VS (VS [0 ]],VS[1],VS[2],VS[3]) Is subjected to VS (0)000) When the load current changes in stages → VS (0001) → VS (0011) → VS (0111) → VS (1111), it indicates that the load current is gradually increasing.
FIG. 3 is a simulated waveform diagram of the output of the sample-and-hold circuit II in the load current detection circuit, which is shown as the load current IOUTIt can be seen that as the load current is gradually increased from 10 μ a to 800mA, the output of the sample-and-hold circuit is also gradually increased. The peak current detection circuit can well convert the change of the load current into the change of the voltage and output the voltage through the sampling holding current. The change of the load current can be known through the output change of the sample hold circuit.
Fig. 4 is a simulation diagram of the overall output waveform of the load current detection circuit applied to the PWM DC-DC converter according to the preferred embodiment of the present invention, where the uppermost signal is the load current IOUTThe same gradually increases from 10 μ a to 800 mA. The remaining waveforms represent VS 0 from top to bottom]、VS[1]、VS[2]、VS[3]It can be seen that the signal VS (VS [0 ] when the load current increases from 10 μ A to 100mA],VS[1],VS[2],VS[3]) Change from VS (0000) to VS (0001); when the load current increases from 100mA to 200mA, the signal VS (VS [0 ]],VS[1],VS[2],VS[3]) Change from VS (0001) to VS (0011); when the load current increases from 200mA to 400mA, the signal VS (VS [0 ]],VS[1],VS[2],VS[3]) Change from VS (0011) to VS (0111); when the load current increases from 400mA to 800mA, the signal VS (VS [0 ]],VS[1],VS[2],VS[3]) Change from VS (0111) to VS (1111); fig. 3 and 4 collectively illustrate the load current detection circuit applied to the PWM DC-DC converter, which can correctly detect the variation trend of the current of the load and convert the variation trend into a stable digital signal for output.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. One typical implementation device is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above examples are to be construed as merely illustrative and not limitative of the remainder of the disclosure. After reading the description of the invention, the skilled person can make various changes or modifications to the invention, and these equivalent changes and modifications also fall into the scope of the invention defined by the claims.
Claims (2)
1. A low power consumption load current detection circuit applied to a PWM DC-DC converter is connected with a voltage conversion core circuit, and is characterized by comprising: the peak current detection circuit comprises a peak current detection module (1), a sampling and holding circuit (2) and an analog-to-digital conversion module (3), wherein the input end of the peak current detection module (1) is connected to a drain of a power follow current PMOS (P-channel metal oxide semiconductor) transistor M1, then the output end of the peak current detection module (1) is connected with the input end of the sampling and holding circuit (2), the output end of the sampling and holding circuit (2) is connected with the input end of the analog-to-digital conversion circuit (3), the sampling and holding circuit obtains a stable peak current signal through a switch capacitor, and the peak current detection module (1) is used for detecting a current peak value on the power follow current PMOS transistor M1 in real time, converting the current peak value into a voltage signal and outputting the voltage signal to the sampling and holding circuit (2); the sampling hold circuit (2) is used for sampling and holding the peak current signal detected by the peak current detection module to obtain a flat voltage signal so as to facilitate comparison by a comparator; the analog-to-digital conversion module (3) is used for converting the voltage signal output by the sampling and holding circuit into a digital electric signal and providing the digital electric signal to a subsequent logic circuit for processing;
the analog-digital conversion module (3) comprises dynamic comparators CMOP1, COMP2, COMP3 and COMP4, voltage dividing resistors R1, R2, R3, R4 and R5, wherein four positive pole inputs of the dynamic comparators CMOP1, COMP2, COMP3 and COMP4 are connected with the output of the sample hold circuit, the connection points between the two dynamic comparators R1-R5 after voltage division are connected in series are respectively connected with the negative pole inputs of the dynamic comparators COMP 1-COMP 4, the four dynamic comparators carry out comparison operation when the power freewheeling PMOS tube M1 is closed, and four outputs of the dynamic comparators COMP 1-COMP 4 form a four-bit signal VS [0:3 ];
the switching signal VCP controls the opening and closing of the power follow current PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M6 and the transmission gate PASS, when the power follow current PMOS tube M1 is opened, the PMOS tubes M3, M5, M6 and the transmission gate PASS are synchronously opened to detect and sample load current, when the power follow current PMOS tube M1 is closed, the PMOS tubes M3, M5 and M6 are simultaneously closed, extra power consumption is avoided, the transmission gate PASS is closed, and the capacitor C is closedsenseThe sampled peak current signals are obtained and held, and the dynamic comparators COMP 1-COMP 4 are workingWhen the PMOS transistor M1 is turned off, the dynamic comparator outputs VS 0]～VS[3]Digital signal VS [0:3] forming a four-bit]When VS (VS [0 ]],VS[1],VS[2],VS[3]) When the signal of (a) goes through the stage-by-stage change of VS (0000) → VS (0001) → VS (0011) → VS (0111) → VS (1111), it indicates that the load current is gradually increasing, and this realizes the process of digitizing the detected load current;
the peak current detection module (1) comprises: PMOS tube M, NMOS tube M, and resistor Rsense, wherein the source of PMOS tube M is connected to the drain of power freewheeling PMOS tube M and the drain of power freewheeling NMOS tube M, the source of PMOS tube M is connected to power VDD, the source of NMOS tube M is connected to GND, the source of PMOS tube M is connected to power input VDD, the grid of PMOS tube M is connected to the grid of power freewheeling PMOS tube M, the grid of PMOS tube M, the drain of PMOS tube M is connected to the drain of PMOS tube M and the source of M, the source of PMOS tube M is connected to power VDD, the drain of M is connected to the source of PMOS tube M and the drain of NMOS tube M, the grid of PMOS tube M is connected to the drain of M, the drain of PMOS tube M is connected to the grid of NMOS tube M, the drain of PMOS tube M is connected to the drain of NMOS tube M and the grid of NMOS tube M, the grid of NMOS tube M and the drain of NMOS tube M are connected to the current source output, the output of NMOS tube M, the drain of NMOS tube M, The grid of the NMOS tube M10 is connected, the sources of M4, M9 and M10 are connected with GND, the source of the NMOS tube M11 is connected with one end of the sensing resistor Rsense and the input of the sampling hold circuit, and R is connected with the output of the sampling hold circuitsenseThe other end of the power freewheeling PMOS tube M1 stops detecting when the power freewheeling PMOS tube M1 is closed;
the sampling and holding circuit (2) comprises a transmission gate PASS and a capacitor Csense, wherein the input of the transmission gate PASS is connected with the output of the peak current detection module, the output of the transmission gate PASS is connected with the four input ends of the capacitor Csense and the analog-to-digital conversion module, the clock control end of the transmission gate PASS is connected with the grid electrode of the power follow current PMOS tube M1, the peak value is kept unchanged at the peak value of the sampling current signal until the next power follow current PMOS tube M1 is opened again, and a stable peak current sampling signal is output in the clock period of the power follow current PMOS tube M1 being turned off.
2. The load current detection circuit with low power consumption for PWM DC-DC converter according to claim 1, wherein the PMOS transistors M5 and M6 are in deep linear region during sampling detection, and have resistance value of
In the formula upFor hole mobility, CoxIs the gate oxide capacitance per unit area,
is the width-length ratio of PMOS transistor M5 or PMOS transistor M6, VDD is the power supply input voltage, VTH,PThreshold voltages of M5, M6; the current of the circuit branch in which M5 and M6 are located during the sampling detection period can be expressed as
Due to RONIs a constant value during sample detection, so IDWill follow VSWChange of (a) and linear change of (b), VSWThe voltage at the drain electrode of the PMOS transistor M1 is a power follow current and finally passes through RsenseReflected as a linear change in the voltage signal.
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| CN114705919B (en) * | 2022-03-04 | 2024-09-10 | 重庆邮电大学 | Inductance current detection circuit for power management chip |
| CN114935960B (en) * | 2022-04-11 | 2024-10-22 | 西安电子科技大学重庆集成电路创新研究院 | MPPT method suitable for rapid sampling of open-circuit voltage of alternating current energy |
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