CN111739944A - A fully surrounded gate synapse transistor, preparation method and circuit connection method - Google Patents

Abstract

The invention relates to a fully surrounding gate synapse transistor, a preparation method and a circuit connection method. The fully surrounding gate synapse transistor comprises an active layer, an insulating layer, a gate electrode, a source electrode and a drain electrode; the active layer is A cylinder, the outer side of the active layer wraps the insulating layer and the gate electrode in turn, one end of the active layer is provided with a source electrode, and the other end is provided with a drain electrode, the source electrode and the drain electrode are both cylindrical The diameter of the bottom surface of the source electrode and the drain electrode is smaller than the diameter of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are arranged coaxially. The invention enables the gate voltage to control the channel current from all directions, improves the control ability of the gate electrode, and reduces the power consumption of the device.

Description

A fully surrounded gate synapse transistor, preparation method and circuit connection method

technical field

The present invention relates to the technical field of synaptic transistors, in particular to a fully surrounding gate synaptic transistor, a preparation method and a circuit connection method.

Background technique

With the rapid development of information technology, the amount of data has grown explosively, and the processing capacity of the huge amount of data has also begun to encounter bottlenecks. The traditional computer based on the von Neumann system shows strong computing power when dealing with problems with clear logic and clear data structure, but for some problems with ambiguous logical structure and huge amount of data, such as image and video processing, It is very inefficient and consumes a lot of energy. Inspired by the human brain, research on brain-like computer systems has received extensive attention. To create a brain-like computer, it is particularly important to develop high-performance synaptic transistors. The current traditional synaptic transistors are based on the thin film transistor technology (Thin Film Transistor TFT) stack structure, the gate has a weak ability to control the channel current, resulting in large channel leakage current, small switching current ratio, and device power. A series of problems, such as high power consumption, make the performance of synaptic transistors low. At the same time, the proton mobility of the insulating layer in traditional synaptic transistors is insufficient, and the synaptic characteristics need to be improved.

SUMMARY OF THE INVENTION

Based on this, the purpose of the present invention is to provide a fully surrounded gate synapse transistor, a preparation method and a circuit connection method. In the fully surrounded gate synapse transistor, the gate surrounds the insulating layer and the active layer, so that the The gate voltage can control the channel current from all directions, improving the controllability of the gate electrode, thereby reducing the power consumption of the device.

For achieving the above object, the present invention provides the following scheme:

A fully surrounded gate synapse transistor, comprising an active layer, an insulating layer, a gate electrode, a source electrode and a drain electrode; the active layer is a cylinder, and the outer side of the active layer wraps the insulating layer and the For the gate electrode, one end of the active layer is provided with a source electrode, and the other end is provided with a drain electrode. The diameter of the bottom surface of the active layer is small, and the active layer, the source electrode and the drain electrode are arranged coaxially.

Optionally, the insulating layer material includes polyethylene oxide (PEO), polyacrylonitrile (PAN), polyvinylidene fluoride (PVDF), polymethyl methacrylate (PMMA), polypropylene oxide (PPO) ), polyvinylidene chloride (PVDC), perovskite type, NASICON type, LISICON type and garnet type or one or any of them.

Optionally, the height of the active layer is 10-100 nm.

Optionally, the gate electrode has a height of 30-500 nm and a thickness of 5-50 nm.

Optionally, the heights of the source electrode and the drain electrode are both 10-50 nm.

The present invention also provides a method for preparing a fully surrounded gate synapse transistor, the method comprising:

depositing a source electrode on the substrate, the source electrode is a cylinder;

depositing a first intermetallic insulator layer on the source electrode, the height of the first intermetallic insulator layer being greater than or equal to the height of the source electrode;

A cylindrical gate electrode is arranged on the first intermetal insulator layer, and the gate electrode is arranged coaxially with the source electrode;

An insulating layer is arranged inside the cylindrical gate electrode, and the insulating layer is cylindrical;

Filling the inside of the insulating layer with the active layer material to form an active layer, the active layer is a cylinder;

A drain electrode is arranged on the active layer, the drain electrode is a cylinder, the diameter of the bottom surface of the source electrode and the drain electrode is smaller than the diameter of the bottom surface of the active layer, the drain electrode and the gate electrode Coaxial setup.

Optionally, the arranging the cylindrical gate electrode on the first intermetallic insulator layer specifically includes: depositing a gate electrode material on the first intermetallic insulator layer to form a cylinder, The cylinder is etched into a cylindrical gate electrode.

Optionally, the disposing an insulating layer inside the cylindrical gate electrode specifically includes: using an electrospinning process to dispose an insulating layer inside the gate electrode.

Optionally, the first intermetal insulator layer includes any one of borophosphosilicate glass, silicon dioxide and silicon nitride.

The present invention also provides a circuit connection method for a fully surrounding gate synapse transistor, relying on the above-mentioned preparation method of a fully surrounding gate synapse transistor, the method comprising:

The source electrode and the connection line of the source electrode are deposited on the substrate according to the preset patterned source electrode and the connection line of the source electrode; the number of the source electrode is greater than 1;

depositing a first intermetal insulator layer on the connection line between the source electrode and the source electrode;

Disposing a cylindrical gate electrode on the first intermetal insulator layer;

depositing the gate electrode connection line on the first intermetal insulator layer according to the preset patterned gate electrode connection line;

depositing a second intermetal insulator layer on the first intermetal insulator layer, the height of the second intermetal insulator layer being equal to the height of the gate electrode;

An insulating layer and an active layer are sequentially arranged inside the cylindrical gate electrode;

a drain electrode is provided on the active layer;

depositing a third inter-metal insulator layer on the second inter-metal insulator layer, the height of the third inter-metal insulator layer is smaller than the height of the drain electrode;

The drain electrode connection line is deposited on the third intermetal insulator layer according to a preset patterned drain electrode connection line.

According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

The purpose of the present invention is to provide a fully surrounding gate synapse transistor, a preparation method and a circuit connection method. In the fully surrounding gate synapse transistor, the gate wraps the insulating layer and the active layer in a surrounding shape, so that the gate voltage The channel current can be controlled from all directions, the control ability of the gate electrode is improved, the channel leakage current is reduced, and the switching current ratio is increased, thereby reducing the power consumption of the device.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some of the present invention. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative labor.

1 is a perspective view of a fully surrounding gate synapse transistor according to an embodiment of the present invention;

2 is a front view of a fully surrounded gate synapse transistor according to an embodiment of the present invention;

3 is a cross-sectional view of a fully surrounding gate synapse transistor according to an embodiment of the present invention;

4 is a schematic structural diagram of a conventional bottom-gate TFT-based stacked synapse transistor according to an embodiment of the present invention;

5 is a schematic flowchart of a method for fabricating a fully surrounded gate synapse transistor according to an embodiment of the present invention;

6 is a schematic flowchart of a circuit connection method for fully surrounding gate synapse transistors according to an embodiment of the present invention;

FIG. 7 is a process flow diagram of a connection process in which a fully surrounding synaptic transistor is connected as a NAND gate circuit according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a fully surrounded synapse transistor fabricated in an embodiment of the present invention connected as a NAND gate circuit.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The purpose of the present invention is to provide a fully surrounding gate synapse transistor, a preparation method and a circuit connection method. In the fully surrounding gate synapse transistor, the gate wraps the insulating layer and the active layer in a surrounding shape, so that the gate voltage The channel current can be controlled from all directions, and the control ability of the gate electrode can be improved, thereby reducing the power consumption of the device.

In order to make the above objects, features and advantages of the present invention more clearly understood, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

1-3 is a structure of a fully surrounding gate synapse transistor. As shown in FIG. 1-3, the fully surrounding gate synapse transistor includes an active layer, an insulating layer, a gate electrode, a source electrode and a drain electrode; The active layer is a cylinder, and the outer side of the active layer wraps the insulating layer and the gate electrode in turn. One end of the active layer is provided with a source electrode, and the other end is provided with a drain electrode. The drain electrodes are all cylinders, the diameters of the bottom surfaces of the source electrodes and the drain electrodes are both smaller than the diameters of the bottom surfaces of the active layer, and the active layer, the source electrodes and the drain electrodes are coaxially arranged .

The gate electrode material includes one or any composite metals of Al, Au, Ag, Mo, W, Cu and Fe. The gate electrode has a height of 30-500 nm and a thickness of 5-50 nm.

Insulation layer materials include polyethylene oxide (PEO), polyacrylonitrile (PAN), polyvinylidene fluoride (PVDF), polymethyl methacrylate (PMMA), polypropylene oxide (PPO), polyvinylidene chloride (PVDC), perovskite type, NASICON type, LISICON type and garnet type, one or any of them, with a thickness of 10-100 nm.

The active layer material includes one or any of SnSiO, SnZrO, InSnBaO, InZnO, and InGaN, and the thickness is 10-100 nm.

The material of the source electrode and the drain electrode includes one of Al, Au, Ag, Mo, W, Cu, and Fe, or a composite metal of any of them.

The heights of the source electrode and the drain electrode are both 10 to 50 nm.

The present invention also provides a method for preparing a fully surrounded gate synapse transistor. As shown in 5, the method includes:

Step 101 : depositing a source electrode on the substrate, where the source electrode is a cylinder.

Wherein, step 101 specifically includes: depositing patterned source electrodes and interconnecting lines on the substrate.

Step 102 : depositing a first inter-metal insulator layer on the source electrode, where the height of the first inter-metal insulator layer is greater than or equal to the height of the source electrode. The insulating property of the first intermetal insulator layer should be good.

Step 103: Disposing a cylindrical gate electrode on the first inter-metal insulator layer, the gate electrode and the source electrode are disposed coaxially.

Wherein, step 103 specifically includes: depositing a patterned metal cylinder on the first intermetal insulator layer to make a gate electrode, the metal cylinder must be deposited just above the source electrode, and the metal cylinder must be deposited directly above the source electrode by reactive ion etching. The inside of the metal cylinder for making the gate electrode is etched cleanly to form a cylindrical gate electrode, and at the same time, the first intermetallic insulator layer on the bottom surface of the cylinder is etched away, so that the source electrode is exposed.

Step 104: disposing an insulating layer inside the cylindrical gate electrode, and the insulating layer is cylindrical;

Wherein, step 104 specifically includes: using an electrospinning process to fabricate an insulating layer formed of solid electrolyte nanowires inside the gate electrode.

Step 105 : filling the inside of the insulating layer with an active layer material to form an active layer, the active layer being a cylinder.

Wherein, step 105 specifically includes: sputtering the active layer material to fill the interior of the gate electrode by sputtering.

Step 106: Disposing a drain electrode on the active layer, the drain electrode is a cylinder, the diameter of the bottom surface of the source electrode and the drain electrode is smaller than the diameter of the bottom surface of the active layer, and the drain electrode is the same as the diameter of the bottom surface of the active layer. The gate electrodes are arranged coaxially. The drain electrode is made by evaporation.

The present invention also provides a circuit connection method for fully surrounding gate synapse transistors, as shown in FIG. 6 , the method includes:

Step 201 : deposit the source electrode and the connection line of the source electrode on the substrate according to the preset patterned source electrode and the connection line of the source electrode; the number of the source electrode is greater than one.

Before step 201 , the method further includes: selecting a substrate of a suitable size according to the size of the full-surrounding gate synapse transistor, and cleaning and drying the substrate.

Wherein, step 201 specifically includes: preparing patterned source electrodes on the substrate by thermal evaporation or sputtering, connecting the source electrodes according to the needs of circuit functions, and preparing the connecting lines by sputtering or thermal evaporation .

Step 202 : depositing a first intermetal insulator layer on the source electrode and the connection line of the source electrode.

Wherein, step 202 specifically includes: preparing the first intermetal insulator layer by chemical vapor deposition or sputtering, the purpose is to separate the source electrode and the source electrode connecting line prepared in step 201 from the gate electrode to be prepared in the following steps, which is worthwhile. It should be noted that the dielectric constant of the material of the first intermetal insulator layer should be small and should reach a certain thickness.

Step 203: Disposing a cylindrical gate electrode on the first intermetal insulator layer.

Wherein, step 203 specifically includes: preparing a metal cylinder with a diameter of 50-500 nm and a height of 30-500 nm on the first metal insulator layer by thermal evaporation or sputtering, and the metal cylinder should be coaxial with the source electrode. By the method of reactive ion etching, the inside of the metal cylinder is first etched to make a metal cylinder with a thickness of 5-50 nm, and then the first intermetallic insulator layer in the cylinder is etched away to make the source electrode appear. , the gate electrode is completed.

Step 204 : deposit the gate electrode connection line on the first intermetal insulator layer according to the preset patterned gate electrode connection line.

Wherein, step 204 specifically includes: using a method of thermal evaporation or sputtering to fabricate connecting lines of the gate electrodes, and connecting the gate electrodes according to circuit function requirements.

Step 205 : depositing a second inter-metal insulator layer on the first inter-metal insulator layer, where the height of the second inter-metal insulator layer is equal to the height of the gate electrode.

Wherein, step 205 specifically includes: using chemical vapor deposition or sputtering to prepare the second intermetal insulator layer, the purpose is to bury the gate electrode and the metal connection line of the gate electrode to facilitate the fabrication of subsequent steps.

Step 206: Disposing an insulating layer and an active layer in sequence on the inner side of the cylindrical gate electrode.

Wherein, step 206 specifically includes: next, using an electrospinning process to fabricate a thin layer of solid electrolyte nanowires on the inner side of the cylindrical gate as an insulating layer.

After the insulating layer is fabricated, the active layer material is sputtered to fill the cylinder of the gate electrode, so that the fabrication of the active layer is completed.

Step 207: Disposing a drain electrode on the active layer.

Wherein, step 207 specifically includes: fabricating the drain electrode by sputtering or thermally evaporating metal.

Step 208 : depositing a third inter-metal insulator layer on the second inter-metal insulator layer, where the height of the third inter-metal insulator layer is smaller than the height of the drain electrode.

Wherein, step 208 specifically includes: preparing a third intermetal insulator layer by chemical vapor deposition or sputtering, burying the upper surfaces of the gate electrode, the insulating layer and the active layer, but exposing the upper half of the drain electrode out to facilitate the connection of the circuit.

Step 209 : deposit the connection line of the drain electrode on the third intermetal insulator layer according to the preset patterned connection line of the drain electrode.

Wherein, step 209 specifically includes: using thermal evaporation or sputtering to prepare a metal connection wire of the drain electrode, and connecting the exposed drain electrode in step 208 according to circuit functional requirements.

At this step, the fully surrounding synaptic transistor device is completed, and at the same time, the circuit with certain specific functions suitable for the device structure of the present invention is also completed.

The material of the connection line of the source electrode, the connection line of the gate electrode and the connection line of the drain electrode includes: one or any kind of composite metal in Al, Au, Ag, Mo, W, Cu, Fe, and the thickness is 10~ 30nm, the width is 10～30nm.

Materials of the first intermetallic insulator layer, the second intermetallic insulator layer and the third intermetallic insulator layer include any one of borophosphosilicate glass, silicon dioxide, and silicon nitride.

Among them, the methods of sputtering and etching are all carried out under the conditions of corresponding masks.

In the fully surrounding gate structure synaptic transistor of the present invention, the gate (gate electrode) wraps the insulating layer and the edge layer in a fully surrounding shape, which overcomes the traditional synaptic transistor based on "bottom gate" or "top gate" TFT structure. There are many drawbacks of the traditional bottom-gate TFT-based stacked synapse transistor structure as shown in Figure 4. In the traditional "stacked" structure synaptic transistor, the gate voltage can only control the channel current from one direction, and the gate voltage has a weak ability to control the channel current, which directly leads to the synaptic transistor device. The channel leakage current will be large, the power consumption of the device will be high, and the stability and efficiency of the device will be greatly reduced. The gate electrode, insulating layer, active The layers are prepared in the shape of concentric circles in turn. The gate electrode voltage can control the channel current from all directions, and the control ability of the gate electrode voltage is greatly improved, which means that the overall performance of the device will be greatly optimized. . At the same time, the insulating layer of the fully enclosed gate synapse transistor of the present invention adopts the electrospinning process to prepare solid electrolyte nanowires. Compared with the traditional synapse transistor device, the proton mobility in the nanowire structure is higher, and the electric double layer effect is The more obvious, the more prominent the synaptic properties.

For the device structure and preparation method of the fully enclosed gate synapse transistor of the present invention, the present invention also proposes a corresponding circuit interconnection process, so that individual devices that are independent of each other can be connected to achieve specific functions. Whether it is the fully surrounding gate synapse transistor structure and its preparation method of the present invention, or the corresponding circuit interconnection process proposed, it is compatible with the existing integrated circuit planarization process, and the solution proposed by the present invention is simple and easy to understand. The operability is strong, and the production cost is low.

7 is a process flow diagram of connecting a NAND circuit according to the above-mentioned circuit connection method for a fully surrounding gate synapse transistor, and FIG.

The manufacturing process of the NAND gate circuit formed by the connection of the fully surrounded synaptic transistors includes:

Choose a glass substrate of suitable size, wash it with acetone, alcohol, and deionized water in sequence, and then dry it for later use.

Two cylindrical copper source electrodes with a height of 30nm and a diameter of 60nm are prepared by the method of sputtering on the cleaned glass substrate (Note: all sputtering, lithography, and etching steps in this scheme will use To the corresponding reticle, for the convenience of description, the reticle is omitted below).

Using the method of sputtering, copper wires with a height of 10 nm and a width of 20 nm were prepared to connect the two source electrodes.

The first intermetallic insulator layer is prepared by chemical vapor deposition, and the material of the first intermetallic insulator layer is borophosphosilicate glass (BPSG) with a thickness of 50 nm. The purpose is to connect the source electrode and metal prepared in the above steps with the following steps. The prepared gate electrodes are spaced apart.

On the first intermetallic insulator layer, a small metal copper cylinder with a diameter of 200 nm and a height of 300 nm is prepared by sputtering to make a gate electrode, and the small metal copper cylinder should be aligned with the center of the source electrode.

By the method of reactive ion etching, the inside of the small metal copper cylinder is first etched to make a small metal cylinder with a thickness of 20nm, and then the first intermetallic insulator layer under the small cylinder is etched away to make the source electrode It is exposed to facilitate subsequent connection with the active layer, so that the gate electrode is completed.

A copper wire with a height of 10 nm and a width of 20 nm is fabricated by sputtering, and the two gates are respectively drawn out as input ports input1 and input2.

The chemical vapor deposition method is used to prepare the second intermetal insulator layer with a height of 300 nm. The material is also borophosphosilicate glass. The purpose is to bury the gate electrode and the metal connection line of the gate electrode to facilitate the fabrication of subsequent steps.

Next, an electrospinning process was used to fabricate a thin layer of solid electrolyte nanowires on the inside of the cylindrical gate electrode as an insulating layer. The solid electrolyte material was a garnet-type solid electrolyte, and the thickness of the insulating layer was 30 nm.

The small gate cylinder is filled by sputtering InZnO, so that the active layer is completed.

Two cylindrical copper drain electrodes with a height of 30 nm and a diameter of 60 nm were fabricated by sputtering.

The third intermetal insulator layer is still prepared by chemical vapor deposition of borophosphosilicate glass, and the gate, insulating layer, and the upper surface of the active layer are buried, but the upper half of the drain electrode is exposed to facilitate the circuit. connection, and the thickness of the third intermetal insulator layer is controlled to be 15 nm. So far, the independent all-encompassing synaptic transistor device has been prepared.

Finally, a copper wire with a height of 10 nm and a width of 20 nm is prepared by sputtering, and the two exposed drain electrodes are led out to two interfaces, wherein the first interface is used as the connection port of V _DD and the ground wire, and the second interface is used as the output port. , as shown in Figure 8. Finally, a circuit suitable for the device structure of the present invention, taking the NAND gate as an example, is connected.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other.

In this paper, specific examples are used to illustrate the principles and implementations of the present invention. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present invention; meanwhile, for those skilled in the art, according to the present invention There will be changes in the specific implementation and application scope. In conclusion, the contents of this specification should not be construed as limiting the present invention.

Claims (10)

1. A fully-wrapped-gate synaptic transistor comprising an active layer, an insulating layer, a gate electrode, a source electrode, and a drain electrode; the active layer is a cylinder, the outer side of the active layer is sequentially wrapped by the insulating layer and the gate electrode, one end of the active layer is provided with a source electrode, the other end of the active layer is provided with a drain electrode, the source electrode and the drain electrode are cylinders, the diameter of the bottom surface of the source electrode and the diameter of the bottom surface of the drain electrode are smaller than that of the bottom surface of the active layer, and the active layer, the source electrode and the drain electrode are coaxially arranged.

2. The fully-wrapped-gate synaptic transistor of claim 1, wherein the insulating layer material comprises one or any of polyethylene oxide, polyacrylonitrile, polyvinylidene fluoride, polymethyl methacrylate, polypropylene oxide, polyvinylidene chloride, perovskite type, NASICON type, LISICON type, and garnet type.

3. The fully-wrapped-gate synaptic transistor of claim 1, wherein the height of the active layer is between 10nm and 100 nm.

4. The fully-wrapped-gate synaptic transistor according to claim 1, wherein the gate electrode has a height of 30-500 nm and a thickness of 5-50 nm.

5. The fully-wrapped-gate synaptic transistor according to claim 1, wherein the height of each of the source electrode and the drain electrode is 10-50 nm.

6. A method for preparing a fully-wrapped-gate synaptic transistor, the method comprising:

depositing a source electrode on a substrate, wherein the source electrode is a cylinder;

depositing a first intermetallic insulator layer on the source electrode, the first intermetallic insulator layer having a height greater than or equal to a height of the source electrode;

providing a cylindrical gate electrode on the first intermetallic insulator layer, the gate electrode being provided coaxially with the source electrode;

an insulating layer is arranged on the inner side of the cylindrical gate electrode, and the insulating layer is cylindrical;

filling an active layer material into the insulating layer to form an active layer, wherein the active layer is a cylinder;

and a drain electrode is arranged on the active layer, the drain electrode is a cylinder, the diameters of the bottom surfaces of the source electrode and the drain electrode are smaller than that of the bottom surface of the active layer, and the drain electrode and the gate electrode are coaxially arranged.

7. The method according to claim 6, wherein the step of providing a cylindrical gate electrode on the first intermetallic insulator layer comprises: and depositing a gate electrode material on the first intermetallic insulator layer to form a cylinder, and etching the cylinder to form the cylindrical gate electrode.

8. The method according to claim 6, wherein the step of providing an insulating layer inside the cylindrical gate electrode comprises: and arranging an insulating layer on the inner side of the gate electrode by adopting an electrostatic spinning process.

9. The method of claim 6, wherein the first inter-metal insulator layer comprises any one of borophosphosilicate glass, silicon dioxide, and silicon nitride.

10. A circuit connection method for a fully-wrapped-gate synaptic transistor, in accordance with a method of manufacturing a fully-wrapped-gate synaptic transistor according to any one of claims 6-9, the method comprising:

depositing a connecting line of the source electrode and the source electrode on a substrate according to a preset patterned connecting line of the source electrode and the source electrode; the number of the source electrodes is more than 1;

depositing a first intermetallic insulator layer on the source electrode and the connection line of the source electrode;

providing a cylindrical gate electrode on the first intermetallic insulator layer;

depositing a connection line of the gate electrode on the first intermetallic insulator layer according to a preset patterned connection line of the gate electrode;

depositing a second intermetallic insulator layer on the first intermetallic insulator layer, the second intermetallic insulator layer having a height equal to a height of the gate electrode;

sequentially arranging an insulating layer and an active layer on the inner side of the cylindrical gate electrode;

providing a drain electrode on the active layer;

depositing a third intermetallic insulator layer on the second intermetallic insulator layer, the third intermetallic insulator layer having a height less than the height of the drain electrode;

and depositing a connecting line of the drain electrode on the third intermetallic insulator layer according to a preset patterned connecting line of the drain electrode.

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