CN111724851B - Data protection method, memory storage device and memory control circuit unit - Google Patents

Abstract

The present invention provides a data protection method, a memory storage device and a memory control circuit unit. The method includes: setting a plurality of disk array labels corresponding to a plurality of word lines and a plurality of memory planes, wherein one word line is connected to the disk array label corresponding to one of the memory planes and another word line is connected to another memory The disk array labels corresponding to the planes are at least partially the same; receiving a write command and data corresponding to the write command from the host system; and sequentially writing the data into a plurality of word lines and a plurality of memory planes corresponding to the plurality of disk array labels .

Description

Data protection method, memory storage device and memory control circuit unit

technical field

The present invention relates to a memory management technology, in particular to a data protection method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones and MP3 players have grown rapidly over the past few years, resulting in a rapid increase in consumer demand for storage media. Because rewritable non-volatile memory modules (eg, flash memory) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for built-in Among the various portable multimedia devices exemplified above.

In the field of flash memory, 3D NAND flash memory in which more memory cells are packaged through 3D stacking technology has been developed. However, the 3D NAND flash memory may cause physical failures such as short-circuiting of word lines due to various factors (eg, leakage of memory cells, program failure, damage, etc.). Generally speaking, in order to ensure the correctness of the data, in some encoding/decoding technologies, the data stored in multiple physical pages may be encoded as the same tag. Data belonging to the same label can protect each other. When a certain data cannot be corrected by its own error correction code, the data corresponding to the same tag and stored in other physical pages can be used to assist the correction of the uncorrectable data. For example, the data is corrected using the parity information (Parity) stored in the rewritable non-volatile memory corresponding to the data to be corrected.

However, the storage space of the rewritable non-volatile memory module is limited, and as the capacity of the memory increases, the amount of data corresponding to the temporary tag may occupy too much capacity of the buffer memory. In particular, in 3D NAND flash memory, the above situation is more pronounced. Therefore, how to maintain the reliability of the stored data while reducing the data amount of the stored tags is a topic of concern to those skilled in the art.

SUMMARY OF THE INVENTION

The present invention provides a data protection method, a memory storage device and a memory control circuit unit, which can achieve good data protection capability under the condition that the capacity of the buffer memory is limited.

Embodiments of the present invention provide a data protection method for a memory storage device. The memory storage device includes a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of physical programming units, and each of the physical programming units corresponds to one of a plurality of word lines and One of multiple memory planes. The data protection method includes: setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, and wherein one of the plurality of word lines is connected to one of the plurality of memory planes. The corresponding plurality of disk array labels are at least partially identical to the plurality of disk array labels corresponding to another of the plurality of word lines connected to another of the plurality of memory planes. The plurality of disk array labels are used to indicate that one of the plurality of word lines is connected to the physical programming unit corresponding to one of the plurality of memory planes and the other of the plurality of word lines is connected to another the protection relationship between the physical programming unit data corresponding to the plurality of memory planes.

In an exemplary embodiment of the present invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects the first word line and the second word line among the plurality of word lines, The second plane connects the first word line and the second word line. The first word line is connected to the first plane and corresponds to a plurality of first disk array labels, and the second word line is connected to the second plane and corresponds to a plurality of second disk array labels. The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels.

In an exemplary embodiment of the present invention, the plurality of disk array labels corresponding to the plurality of word lines connected to the same plurality of memory planes are different.

In an exemplary embodiment of the present invention, the plurality of disk array labels corresponding to the plurality of memory planes that are connected to the same plurality of word lines differently are different.

In an exemplary embodiment of the present invention, the step of setting the plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes includes: setting the plurality of disk array labels corresponding to the plurality of disk array labels to the plurality of memory planes and the plurality of physical programming units.

In an exemplary embodiment of the present invention, the above method further includes: generating parity information according to the data, and setting the disk array label corresponding to the parity information.

In an exemplary embodiment of the present invention, the step of setting the disk array label corresponding to the parity information includes: setting the disk array label corresponding to the parity information to correspond to a label used for calculating the parity information The plurality of memory planes and the plurality of physical programming units to which the data is written.

An exemplary embodiment of the present invention provides a memory storage device. The memory storage device includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The rewritable non-volatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of physical programming units, and each of the physical programming units corresponds to one of a plurality of word lines and One of multiple memory planes. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used for setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, and one of the plurality of word lines is connected to one of the plurality of memory planes The corresponding plurality of disk array labels are at least partially identical to the plurality of disk array labels corresponding to another of the plurality of word lines connected to another of the plurality of memory planes. The memory control circuit unit is further configured to receive a write command and data corresponding to the write command from the host system. And the memory control circuit unit is further used for sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

In an exemplary embodiment of the present invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects the first word line and the second word line among the plurality of word lines, The second plane connects the first word line and the second word line. The memory control circuit unit is further configured to set the first word line to connect to the first plane and correspond to a plurality of first disk array labels, and to set the second word line to connect to the second plane and correspond to to multiple second disk array labels. The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels.

In an exemplary embodiment of the present invention, the multiple disk array labels corresponding to the same multiple memory planes connected to the different multiple word lines are different.

In an exemplary embodiment of the present invention, the plurality of disk array labels corresponding to the plurality of different memory planes connected to the same plurality of word lines are different.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit for setting the plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes includes: the memory control The circuit unit is further configured to set the plurality of disk array labels to correspond to the plurality of memory planes and the plurality of physical programming units.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to generate parity information according to the data, and set the disk array label corresponding to the parity information.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to set the disk array label corresponding to the parity information to correspond to the data written for calculating the parity information a plurality of memory planes and the plurality of physical programming units.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device including a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of physical programming units, and each of the physical programming units corresponds to one of a plurality of word lines and One of multiple memory planes. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used for coupling to the host system. The memory interface is used for coupling to the rewritable non-volatile memory module. A memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used for setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, and one of the plurality of word lines is connected to one of the plurality of memory planes. The corresponding plurality of disk array labels are at least partially identical to the plurality of disk array labels corresponding to another of the plurality of word lines connected to another of the plurality of memory planes. The memory management circuit is further configured to receive a write command and data corresponding to the write command from the host system. And the memory management circuit is further used for sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

In an exemplary embodiment of the present invention, the plurality of memory planes include a first plane and a second plane, and the first plane connects the first word line and the second word line among the plurality of word lines, The second plane connects the first word line and the second word line. The memory management circuit is further configured to set the first word line to connect to the first plane and to correspond to a plurality of first disk array labels, and to set the second word line to connect to the second plane and correspond to at most a second disk array label. The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels.

In an exemplary embodiment of the present invention, the multiple disk array labels corresponding to the same multiple memory planes connected to the different multiple word lines are different.

In an exemplary embodiment of the present invention, the plurality of disk array labels corresponding to the plurality of different memory planes connected to the same plurality of word lines are different.

In an exemplary embodiment of the present invention, the operation of the memory management circuit for setting the plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes includes: the memory management circuit It is also used for setting the plurality of disk array labels to correspond to the plurality of memory planes and the plurality of physical programming units.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to generate parity information according to the data, and set the disk array label corresponding to the parity information.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to set the disk array label corresponding to the parity information to correspond to the multiplicity of data written in the data for calculating the parity information a memory plane and the plurality of physical programming units.

Based on the above, the data protection method, memory storage device, and memory control circuit unit provided by the embodiments of the present invention can set multiple disks corresponding to multiple word lines and multiple memory planes through the staggered arrangement of disk array labels Array label. In this way, under the condition that the capacity of the buffer memory is limited, fewer disk array labels can be used to protect the data in the memory, thereby maximizing the protection effect.

Description of drawings

1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment;

2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment;

3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment;

4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

7 is a schematic block diagram of a parity information buffer according to an exemplary embodiment of the present invention;

FIG. 8 is a flowchart of a data protection method according to an exemplary embodiment of the present invention.

Detailed ways

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

In general, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit unit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another exemplary embodiment.

Referring to FIGS. 1 and 2 , the host system 11 generally includes a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , the random access memory 112 , the ROM 113 and the data transmission interface 114 are all coupled to a system bus 110 .

In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114 . For example, host system 11 may write data to or read data from memory storage device 10 via data transfer interface 114 . In addition, the host system 11 is coupled to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O device 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read only memory 113 and the data transmission interface 114 can be disposed on the mainboard 20 of the host system 11 . The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be coupled to the memory storage device 10 via wired or wireless means. The memory storage device 10 may be, for example, a USB flash drive 201 , a memory card 202 , a Solid State Drive (SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a Near Field Communication Storage (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (eg, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be coupled to various I/O modules such as a Global Positioning System (GPS) module 205 , a network interface card 206 , a wireless transmission device 207 , a keyboard 208 , a screen 209 , a speaker 210 and the like through the system bus 110 . O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to FIG. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, etc., and the memory storage device 30 may be used therefor Various non-volatile memory storage devices such as SD card 32 , CF card 33 or embedded storage device 34 . The embedded storage device 34 includes various types such as an embedded multimedia card (embedded MMC, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 to directly couple the memory module to the substrate of the host system embedded storage device.

4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used for coupling the memory storage device 10 to the host system 11 . The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash memory (Universal Flash) Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 may be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware and to write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 operations such as fetching and erasing.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and used to store data written by the host system 11 . The rewritable non-volatile memory module 406 may be a single level cell (Single Level Cell, SLC) NAND type flash memory module (ie, a flash memory module that can store 1 bit in one memory cell), a multi-level memory module. Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in one memory cell), triple level cell (Triple Level Cell, TLC) NAND flash memory Module (that is, a flash memory module that can store 3 bits in one memory cell), Quad Level Cell (QLC) NAND-type flash memory module (that is, a memory cell that can store 4 bits of flash memory module) flash memory modules), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (also referred to as a threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". Each memory cell in the rewritable non-volatile memory module 406 has multiple storage states as the threshold voltage changes. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming unit on the same word line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit Programmable unit reliability.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit in which data is written. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, the physical programming unit may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit region may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory units that are erased. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 operates, these control commands are executed to perform operations such as data writing, reading, and erasing. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control commands are programmed into the read-only memory. When the memory storage device 10 operates, the control commands are executed by the microprocessor unit to perform operations such as data writing, reading and erasing.

In another exemplary embodiment, the control instructions of the memory management circuit 502 may also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of codes (eg, a system area dedicated to storing system data in the memory module). . In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store the boot code in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of memory management circuit 502 . Afterwards, the microprocessor unit will run these control commands to perform operations such as data writing, reading and erasing.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells or memory cell groups of the rewritable non-volatile memory module 406 . The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 406 and the data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence, and the erase command sequence may include one or more codes or command codes, respectively, and are used to instruct the rewritable non-volatile memory module 406 to perform the corresponding write, read, and erase operations such as removal. In an exemplary embodiment, the memory management circuit 502 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is coupled to the memory management circuit 502 . Memory management circuitry 502 may communicate with host system 11 through host interface 504 . The host interface 504 can be used to receive and identify commands and data transmitted by the host system 11 . For example, instructions and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504 . Additionally, the memory management circuit 502 may communicate data to the host system 11 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compliant with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 506 is coupled to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406 . That is, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding command sequence. For example, these instruction sequences may include a write instruction sequence to instruct to write data, a read instruction sequence to instruct to read data, an erase instruction sequence to instruct to erase data, and to instruct various memory operations (eg, change read fetch a voltage level or perform a garbage collection operation, etc.) These sequences of instructions are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or codes. For example, in the read command sequence, information such as the read identification code, memory address, etc. will be included.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508 , a buffer memory 510 and a power management circuit 512 .

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and and/or an error detecting code (EDC), and the memory management circuit 502 writes the data corresponding to the write instruction and the corresponding error correcting code and/or error checking code to the rewritable non-volatile memory in module 406. Then, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 will This error correction code and/or error checking code performs error checking and correction operations on the read data.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . In this embodiment, the buffer memory 510 includes a parity information buffer, and the parity information buffer is used to temporarily store the parity information. The power management circuit 512 is coupled to the memory management circuit 502 and used to control the power of the memory storage device 10 .

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash for controlling the flash memory module. memory controller. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

In this exemplary embodiment, the error checking and correction circuit 508 is implemented with low density parity code (LDPC). However, in another exemplary embodiment, the error checking and correction circuit 508 may also be implemented with encoding/decoding algorithms such as BCH code, convolutional code, turbo code, bit flipping, and the like.

Specifically, the memory management circuit 502 generates an error correction code frame (ECC Frame) according to the received data and the corresponding error check and correction code (hereinafter also referred to as an error correction code) and writes the error correction code frame to the Rewritable non-volatile memory module 406. After that, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the error checking and correction circuit 508 verifies the correctness of the read data according to the error correction code in the error correction code box .

It should be noted that the operations performed by the memory management circuit 502 , the host interface 504 and the memory interface 506 , the error checking and correction circuit 508 , the buffer memory 510 and the power management circuit 512 will also be referred to as the memory control circuit unit. 404 is executed.

In an exemplary embodiment, the memory storage device 10 includes a plurality of rewritable non-volatile memory modules 406, and the rewritable non-volatile memory modules 406 include a plurality of word lines (WL) and a plurality of memories. plane. Also, word lines connect a plurality of memory planes.

The devices of the rewritable non-volatile memory module 406 described above are divided according to the memory planes in the memory die of the rewritable non-volatile memory module 406 . Specifically, the rewritable non-volatile memory module 406 can have one or more memory dies, each memory die has one or more memory planes, and each memory plane has multiple physical programs chemical unit. At the factory, manufacturers divide one or more memory planes into one device according to their needs. Thereby, the manufacturer can manage the entire rewritable non-volatile memory module 406 on a device-by-device basis. The invention does not limit the number of memory planes included in each device.

In the present exemplary embodiment, the rewritable non-volatile memory module 406 is a three-dimensional (3D) complex level cell (Trinary Level Cell, TLC) NAND flash memory module (ie, a memory cell that can Flash memory modules that store 3 data bits) or other memory modules with the same characteristics. However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a 3D Multi Level Cell (MLC) NAND flash memory module (ie, one memory cell can store 2 bits of data) flash memory modules) or other memory modules with the same characteristics.

In this exemplary embodiment, the rewritable non-volatile memory module 406 includes a plurality of physical units and each physical unit includes a plurality of physical programming units, and each physical programming unit corresponds to a word line and a memory plane .

In an exemplary embodiment, when the memory management circuit 502 receives a write command and corresponding data from the host system 11, the memory management circuit 502 temporarily stores the data in the buffer memory 510, and organizes the data according to the size of the physical programming unit. into substrings. Afterwards, the memory management circuit 502 programs the sub-data strings to the physical programming units respectively and sequentially.

On the other hand, the memory management circuit 502 generates parity information for protecting the sub-data string according to the sub-data string. In detail, the memory management circuit 502 can determine the disk array label corresponding to each parity information according to a preset comparison table or a preset formula, wherein the disk array label is used to indicate which sub-data strings of each parity information belong to the parity information. The buffer is obtained by operation. Accordingly, when the sub-data strings are respectively and sequentially programmed into the physical programming unit, the memory management circuit 502 determines the sub-data strings in the parity information buffer to belong to the same one according to the preset comparison table or the preset formula. The sub-data string of the disk array label is logically operated to generate parity information. In one embodiment, the logical operation method for generating the parity information is, for example, an XOR operation. Then, after computing a set of operation units (eg, a set of physical units), the memory management circuit 502 programs the parity information into the rewritable non-volatile memory module 406 . In particular, the disk array label set by the memory management circuit 502 may correspond to the memory plane and the physical programming unit written in the sub-data string for calculating the parity information, respectively. Based on this, the memory management circuit 502 can use a disk array label comparison table to record the disk array label and the memory plane and the physical programming unit written by the sub-data string corresponding to the disk array label for calculating parity information, and can use Another comparison table records the disk array label and the address where the parity information corresponding to the disk array label is stored.

Specifically, the memory management circuit 502 sets a plurality of disk array labels corresponding to a plurality of word lines and a plurality of memory planes. And one word line connects the multiple disk array labels corresponding to one memory plane and the other word line connects the multiple disk array labels corresponding to the other memory plane at least partially identical. Here, one of the word lines of the rewritable non-volatile memory module 406 is connected to one of the memory planes, and the other word line is connected to the other memory plane, which are different memory planes. And the disk array label is used to indicate the protection relationship between a word line connecting a plurality of physical program units corresponding to one memory plane and another word line connecting a plurality of physical program units corresponding to another memory plane. .

For example, the memory plane of the memory storage device 10 includes a first plane and a second plane, and the first plane connects the first word line and the second word line, and the second plane also connects the first word line and the second word line. The first plane and the second plane respectively correspond to physical programming units, wherein some physical programming units are composed of a plurality of memory cells connected by the first word line, and some physical programming units are a plurality of physical programming units connected by the second word line. composed of storage units. In this exemplary embodiment, the first word line is connected to the first plane and corresponds to the plurality of first disk array labels, and the second word line is connected to the second plane and corresponds to the plurality of second disk array labels. The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels.

In an exemplary embodiment, the disk array labels corresponding to different word lines connected to the same memory plane are different. In an exemplary embodiment, the disk array labels corresponding to different memory planes connected to the same word line are different.

In more detail, the above word lines are connected to a plurality of physical programming units, and the memory plane includes a plurality of physical programming units. Here, the memory management circuit 502 sets a plurality of disk array labels to correspond to a plurality of physical programming units of a plurality of memory planes. The aforementioned disk array label comparison table can record the disk array labels corresponding to each physical programming unit of each memory plane.

6 is a schematic block diagram of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. For the convenience of description, this exemplary embodiment takes the physical units 6101 to 6102 in FIG. 6 as a set of operation units as an example for description. The physical units 6101-6102 respectively include 24 physical programming units, but the present invention does not limit the number of physical programming units.

FIG. 7 is a schematic block diagram of a parity information buffer according to an exemplary embodiment of the present invention. Referring to FIG. 6 and FIG. 7 , the storage unit 702 logically belonging to the parity information buffer temporarily stores parity information, and the parity information can be stored in the storage subunits 720(0) to 720(23) included in the parity information buffer, respectively. . When the memory management circuit 502 receives the write command and the corresponding data from the host system 11, the memory management circuit 502 sequentially writes the data corresponding to the write command to the physical programming units 6101(0)-6101(23) and 6102 (0) to 6102(23). Here, for example, the data is sequentially written into the physical programming units according to the sequence of the physical programming units 6101(0), 6102(0), 6101(1), and 6102(1). In this exemplary embodiment, the physical programming units 6101(0)-6101(23) and the physical programming units 6102(0)-6102(23) correspond to different memory planes.

Take the data written to the physical programming unit 6101(12) as an example. When data is written into the physical programming unit 6101 ( 12 ), the memory management circuit 502 determines that the physical programming unit 6101 ( 12 ) corresponds to the storage sub-unit 720 ( 12 of the storage unit 702 ) according to the preset comparison table or the preset formula. ), and perform logical operation on the written data and the parity information stored in the storage subunit 720(12). In this exemplary embodiment, the parity information stored in the storage subunit 720(12) is determined according to a preset comparison table or a preset formula and corresponds to the same storage subunit 720(12) as the physical programming unit 6101(12). ) of the physical programming unit has the physical programming unit 6102(0). Next, the memory management circuit 502 sets the parity information stored in the storage subunits 720(0) to 720(23) after calculating the parity information according to the data stored in the physical units 6101 to 6102 (ie, a set of operation units). The corresponding disk array labels are 0 to 23, and the calculated parity information is stored in the rewritable non-volatile memory module 406. In particular, the disk array labels 0 to 23 set by the memory management circuit 502 can respectively correspond to the physical programming units 6101(0) to 6101(23) and 6102(0) to which the data for calculating the parity information is written. 6102(23). In this exemplary embodiment, the memory management circuit 502 uses the disk array tag comparison table to record the disk array tags 0-23 and the memory plane and the physical program written by the data for calculating the parity information corresponding to the disk array tags 0-23 Units 6101(0)-6101(23), 6102(0)-6102(23), and use another comparison table to record the addresses of the co-location information corresponding to disk array labels 0-23 and disk array labels 0-23. Here, the correspondence between the disk array labels 0 to 23 generated in this exemplary embodiment, the memory plane and the physical programming unit can be referred to in Table 1 below.

The correspondence between the memory plane, the physical programming unit and the disk array label generated by this exemplary embodiment is shown in Table 1 below. 6 and Table 1 below, in this exemplary embodiment, the memory plane of the memory storage device 10 includes a first plane P0 (ie, the first memory plane) and a second plane P1 (ie, the second memory plane) , and the first plane P0 is connected to the first word line WL0 and the second word line WL1, and the second plane P1 is also connected to the first word line WL0 and the second word line WL1. Here, the physical unit 6101 included in the rewritable non-volatile memory module 406 belongs to the first plane P0, and the physical unit 6102 belongs to the second plane P1. The first plane P0 and the second plane P1 respectively include physical programming units 6101(0)-6101(23) and physical programming units 6102(0)-6102(23), wherein the physical programming units 6101(0)-6101 (11) and 6102(0)-6102(11) are composed of a plurality of memory cells connected to the first word line WL0. The physical programming units 6101(12)-6101(23) and 6102(12)-6102( 23) is composed of a plurality of memory cells connected by the second word line WL1. Based on the above structure, the parity information buffers set by the 48 physical programming units 6101(0)-6101(23) and 6102(0)-6102(23) corresponding to the physical units 6101-6102 in this exemplary embodiment include 24 storages subunit.

Table 1

In this exemplary embodiment, the memory management circuit 502 sets the first word line WL0 to connect the first plane P0 to correspond to a plurality of disk array labels (also referred to as first disk array labels). And the memory management circuit 502 sets the second word line WL1 to connect the second plane P1 to a plurality of disk array labels (also referred to as second disk array labels). In this exemplary embodiment, the memory management circuit 502 sets the first word line WL0 to connect to the physical programming units 6101(0)-6101(11) included in the first plane P0 to correspond to the first disk array labels 0-11, respectively, and The physical programming units 6102 ( 12 ) to 6102 ( 23 ) included in the second word line WL1 connected to the second plane P1 are set to correspond to the second disk array labels 0 to 11 respectively. On the other hand, the memory control circuit unit 404 sets the first word line WL0 to connect the physical programming units 6102(0) to 6102(11) included in the second plane P1 to correspond to the first disk array labels 12 to 23 respectively, and sets The second word line WL1 connects the physical programming units 6101 ( 12 ) to 6101 ( 23 ) included in the first plane P0 and corresponds to the second disk array labels 12 to 23 , respectively. That is to say, in the same memory plane (the first plane P0 or the second plane P1) where the first word line WL0 and the second word line WL1 of the present exemplary embodiment are connected, the disk array labels corresponding to the physical programming units do not have The same disk array label.

Based on the data protection method provided by the present invention, even if a single word line (eg, 2P1WL) connecting different physical planes partially or completely fails, the stored data can still be recovered according to the disk array labeling technology provided by the present invention. On the other hand, even if part or all of two consecutive word lines (eg, 1P2WL) connected to the same physical plane fail, the stored data can be recovered according to the disk array labeling technology provided by the present invention. Compared with the past situation where only one of the entities fails to be protected, the data protection method provided by the embodiment of the present invention can protect the above two situations at the same time. In addition, taking the physical units 6101 to 6102 of the embodiment of the present invention including 24 physical programming units as an example, in the past, when the co-located information recovery technology wanted to protect both the 2P1WL and 1P2WL physical failures, it was necessary to 48 disk array labels and corresponding temporary storage spaces corresponding to a total of 48 physical programming units in units 6101 to 6102 (for example, the storage subunits 710(0) to 710(47) included in the storage unit 701 shown in FIG. 7 ) to store temporary data. This is because only one physical programming unit in a group of physical units corresponding to a group of parity information buffers can fail. Compared with this, the data protection method provided by the present invention only needs to use half of the disk array label and the corresponding temporary storage space to simultaneously protect the two physical failures of 2P1WL and 1P2WL, thereby saving the temporary storage space. It should be noted that those skilled in the art should know how to use the parity information to restore the stored data, so it is not repeated here.

FIG. 8 is a flowchart of a data protection method according to an exemplary embodiment of the present invention. In step S802, a plurality of disk array labels corresponding to a plurality of word lines and a plurality of memory planes are set. In step S804, a write command and data corresponding to the write command are received from the host system. In step S806, the data is sequentially written into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags. In step S808, parity information is generated according to the data, and the disk array label corresponding to the parity information is set.

It is worth noting that each step in FIG. 8 can be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of FIG. 8 can be used in conjunction with the above exemplary embodiments, or can be used alone, which is not limited in the present invention.

To sum up, the data protection method, the memory storage device, and the memory control circuit unit provided by the embodiments of the present invention can set a plurality of disk array labels corresponding to a plurality of word lines and a plurality of memory planes. In this way, under the condition that the capacity of the buffer memory is limited, fewer disk array labels can be used to protect the data in the memory, thereby maximizing the protection effect.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

Claims (18)

1. A data protection method for a memory storage device, the memory storage device comprising a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising a plurality of physical units, each The plurality of physical units include a plurality of physical programming units, each of which corresponds to one of a plurality of word lines and one of a plurality of memory planes, and the data protection method includes: setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, And one of the plurality of word lines is connected to the plurality of disk array tags corresponding to one of the plurality of memory planes and the other of the plurality of word lines is connected to the corresponding to the other plurality of memory planes. said multiple disk array labels are at least partially identical; receiving a write command and data corresponding to the write command from a host system; and writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags in sequence, Generate parity information according to the data, and set the disk array label corresponding to the parity information. 2. The data protection method of claim 1, wherein the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line among the plurality of word lines to the a second word line, the second plane connects the first word line and the second word line, wherein the first word line is connected to the first plane and corresponds to a plurality of first disk array labels, and the second word line is connected to the second plane and corresponds to a plurality of second disk array labels, The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels. 3 . The data protection method of claim 1 , wherein the plurality of disk array labels corresponding to the same plurality of memory planes connected to the plurality of different word lines are different. 4 . 4 . The data protection method according to claim 1 , wherein the plurality of disk array labels corresponding to the plurality of memory planes connected to the same plurality of word lines differently are different. 5 . 5. The data protection method of claim 1, wherein the step of setting the plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes comprises: The plurality of disk array labels are set to correspond to the plurality of memory planes and the plurality of physical programming units. 6. The data protection method according to claim 1, wherein the step of setting the disk array label corresponding to the parity information comprises: The disk array label corresponding to the parity information is set to correspond to the plurality of memory planes and the plurality of physical programming units in which the data for calculating the parity information is written. 7. A memory storage device comprising: a connection interface unit for coupling to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, each of the plurality of physical units includes a plurality of physical programming units, each of the physical programs The UL unit corresponds to one of the plurality of word lines and one of the plurality of memory planes; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used for setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, And one of the plurality of word lines is connected to the plurality of disk array tags corresponding to one of the plurality of memory planes and the other of the plurality of word lines is connected to the corresponding to the other plurality of memory planes. said multiple disk array labels are at least partially identical, The memory control circuit unit is further configured to receive a write command and data corresponding to the write command from the host system, and The memory control circuit unit is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags, The memory control circuit unit is further configured to generate parity information according to the data, and set the disk array label corresponding to the parity information. 8. The memory storage device of claim 7, wherein the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line among the plurality of word lines to the a second word line, the second plane connects the first word line and the second word line, The memory control circuit unit is further configured to set the first word line to connect to the first plane and to correspond to a plurality of first disk array labels, and to set the second word line to connect to the second plane and corresponding to multiple second disk array labels, The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels. 9 . The memory storage device of claim 7 , wherein the plurality of disk array labels corresponding to the same plurality of memory planes connected to the different plurality of word lines are different. 10 . 10. The memory storage device of claim 7, wherein the plurality of disk array labels corresponding to the different memory planes connected to the same plurality of word lines are different. 11. The memory storage device of claim 7, wherein the operation of the memory control circuit unit to set the plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes comprises : The memory control circuit unit is further configured to set the plurality of disk array labels to correspond to the plurality of memory planes and the plurality of physical programming units. 12. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to set the disk array label corresponding to the parity information to correspond to the data used to calculate the parity information. The plurality of memory planes and the plurality of physical programming units written. 13. A memory control circuit unit for controlling a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, each of the plurality of Each physical unit includes a plurality of physical programming units, each of which corresponds to one of a plurality of word lines and one of a plurality of memory planes, and the memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and memory management circuitry, coupled to the host interface and the memory interface, wherein the memory management circuit is used for setting a plurality of disk array labels corresponding to the plurality of word lines and the plurality of memory planes, And one of the plurality of word lines is connected to the plurality of disk array tags corresponding to one of the plurality of memory planes and the other of the plurality of word lines is connected to the corresponding to the other plurality of memory planes. said multiple disk array labels are at least partially identical, The memory management circuit is further configured to receive a write command and data corresponding to the write command from the host system, and The memory management circuit is further configured to sequentially write the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags, The memory management circuit is further configured to generate parity information according to the data, and set the disk array label corresponding to the parity information. 14. The memory control circuit unit of claim 13, wherein the plurality of memory planes include a first plane and a second plane, and the first plane connects a first word line among the plurality of word lines and the second word line, the second plane connects the first word line and the second word line, The memory management circuit is further configured to set the first word line to connect to the first plane and to correspond to a plurality of first disk array labels, and to set the second word line to connect to the second plane and correspond to to multiple second disk array labels, The plurality of first disk array labels are at least partially identical to the plurality of second disk array labels. 15. The memory control circuit unit according to claim 13, wherein the plurality of disk array labels corresponding to the same plurality of memory planes connected by different plurality of word lines are different. 16. The memory control circuit unit of claim 13, wherein the plurality of disk array labels corresponding to the different memory planes connected to the same plurality of word lines are different. 17. The memory control circuit unit of claim 13, wherein the operation of the memory management circuit to set the plurality of disk array tags corresponding to the plurality of word lines and the plurality of memory planes comprises : The memory management circuit is further configured to set the plurality of disk array labels to correspond to the plurality of memory planes and the plurality of physical programming units. 18. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to set the disk array label corresponding to the parity information to correspond to the data used to calculate the parity information. The plurality of memory planes and the plurality of physical programming units written.

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