CN111723045A - Multifunctional memory circuit and integrated circuit chip - Google Patents
Multifunctional memory circuit and integrated circuit chip Download PDFInfo
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- CN111723045A CN111723045A CN202010563369.9A CN202010563369A CN111723045A CN 111723045 A CN111723045 A CN 111723045A CN 202010563369 A CN202010563369 A CN 202010563369A CN 111723045 A CN111723045 A CN 111723045A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
A multifunctional memory circuit and an integrated circuit chip relate to the integrated circuit technology, the multifunctional memory circuit of the invention includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a fourth phase inverter and a fifth phase inverter, wherein the substrate of each MOS transistor is grounded. The invention can respectively realize the functions of SRAM, RAM, ROM, latch, trigger, shift register and the like through configuration, enhance the flexibility and resource utilization rate of FPGA, improve the function/area ratio of FPGA and is beneficial to the integration of hundred million gate level FPGA chips.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
With the process feature size of the FPGA becoming smaller and the integration level scaling moving to the hundred million gate level, how to improve the function/area ratio of the FPGA chip is always the most concerned problem for the FPGA manufacturers. In the prior art, most of the circuit modules in the chip are divided according to functions, and the specific circuit modules realize specific functions, and in the integrated circuit, the more the functions are, the larger the circuit area is, which is not favorable for the miniaturization of the chip.
Disclosure of Invention
The invention aims to provide a basic storage circuit capable of realizing multifunctional multiplexing and an integrated circuit chip with the storage circuit.
The technical solution adopted to solve the technical problems is that the multifunctional memory circuit comprises:
the current output end of the first MOS tube is grounded, and the grid end of the first MOS tube is connected with the first external connecting end;
the current output end of the second MOS tube is connected with the first external connecting end, the current input end of the second MOS tube is connected with the third external connecting end, and the grid end of the second MOS tube is connected with the second external connecting end;
the current output end of the third MOS tube is connected with the current input end of the first MOS tube, the current input end of the third MOS tube is connected with the first reference point, and the grid end of the third MOS tube is connected with the second external connecting end;
the current output end of the sixth MOS tube is connected with the fourth external connecting end, the current input end of the sixth MOS tube is connected with the third external connecting end, and the grid end of the sixth MOS tube is connected with the fifth external connecting end;
a current output end of the seventh MOS tube is connected with the ninth external connecting end, a current input end of the seventh MOS tube is connected with the first reference point, and a grid end of the seventh MOS tube is connected with the fifth external connecting end;
the current output end of the eighth MOS tube is connected with the sixth external connecting end, the current input end of the eighth MOS tube is connected with the fourth external connecting end, and the grid end of the eighth MOS tube is connected with the seventh external connecting end;
a current output end of the ninth MOS tube is connected with the eighth external connecting end, a current input end of the ninth MOS tube is connected with the ninth external connecting end, and a grid end of the ninth MOS tube is connected with the seventh external connecting end;
the input end of the fourth inverter is connected with the third external connecting end, and the output end of the fourth inverter is connected with the first reference point;
the output end of the fifth inverter is connected with the third external connecting end, and the input end of the fifth inverter is connected with the first reference point;
the substrate of each MOS tube is grounded.
The invention also provides an integrated circuit chip with the multifunctional storage circuit.
The invention can respectively realize the functions of SRAM, RAM, ROM, latch, trigger, shift register and the like through configuration, enhance the flexibility and resource utilization rate of FPGA, improve the function/area ratio of FPGA and is beneficial to the integration of hundred million gate level FPGA chips.
Drawings
Fig. 1 is a circuit diagram of the present invention.
Detailed Description
See fig. 1.
The integrated circuit chip of the present invention is built with a multifunctional memory circuit, which includes:
a first MOS transistor 101, which has a current output terminal grounded and a gate terminal connected to a first external connection terminal SHIFT _ IN;
a second MOS transistor 102 having a current output terminal connected to the first external connection terminal SHIFT _ IN, a current input terminal connected to the third external connection terminal SHIFT _ OUT, and a gate terminal connected to the second external connection terminal CLK _ SHIFT;
a current output end of the third MOS tube 103 is connected to a current input end of the first MOS tube, a current input end of the third MOS tube is connected to the first reference point P, and a gate end of the third MOS tube is connected to the second external connection end CLK _ SHIFT;
a sixth MOS transistor 106 having a current output terminal connected to the fourth external connection terminal BLN, a current input terminal connected to the third external connection terminal SHIFT _ OUT, and a gate terminal connected to the fifth external connection terminal WL;
a current output end of the seventh MOS transistor 107 is connected to the ninth external connection end BL, a current input end of the seventh MOS transistor is connected to the first reference point P, and a gate end of the seventh MOS transistor is connected to the fifth external connection end WL;
an eighth MOS transistor 108 having a current output terminal connected to the sixth external connection terminal DAT _ N, a current input terminal connected to the fourth external connection terminal BLN, and a gate terminal connected to the seventh external connection terminal ADDR _ RAM;
a ninth MOS tube 109 having a current output terminal connected to the eighth external connection terminal DAT, a current input terminal connected to the ninth external connection terminal BL, and a gate terminal connected to the seventh external connection terminal ADDR _ RAM;
a fourth inverter 104 having an input terminal connected to the third external connection terminal SHIFT _ OUT and an output terminal connected to the first reference point P;
a fifth inverter 105 having an output terminal connected to the third external connection terminal SHIFT _ OUT and an input terminal connected to the first reference point P;
all the MOS tubes are NMOS tubes, and the substrate is grounded. The current input end of the NMOS tube is a drain end, and the current output end of the NMOS tube is a source end.
Multiple functions can be achieved by configuring each external connection end as follows:
1、SRAM
the second external connection terminal CLK _ SHIFT is at low level; the seventh external connection terminal ADDR _ RAM is at high level; the 4 NMOS transistors 104, 105, 106 and 107 form a 6-transistor SRAM, the fifth external connection end WL is a word line, the ninth external connection end BL and the fourth external connection end BLN are mutually opposite bit lines, and the read-write operation of SRAM data is controlled through the word line and the bit lines.
2、RAM
The second external connection terminal CLK _ SHIFT is at low level; the 6 MOS tubes 104, 105, 106, 107, 108 and 109 form a basic RAM unit. The fifth external connection terminal WL is a clock signal, the seventh external connection terminal ADDR _ RAM is an address signal, and the eighth external connection terminal DAT and the sixth external connection terminal DAT _ N are data inverted from each other. And controlling data of the RAM to perform read-write operation from the DAT and DAT _ N ports through the clock signal and the address signal.
3、ROM
The second external connection terminal CLK _ SHIFT is at low level; the 6 MOS tubes 104, 105, 106, 107, 108 and 109 form a basic ROM unit. The fifth external connection terminal WL is a clock signal, the seventh external connection terminal ADDR _ RAM is an address signal, and the eighth external connection terminal DAT and the sixth external connection terminal DAT _ N are data inverted from each other. The read-only operation of the data of the ROM from the DAT and DAT _ N ports is controlled by the clock signal and the address signal.
4. Latch device
The fifth external connection WL and the seventh external connection ADDR _ RAM are at low level, the 5 MOS transistors 101, 102, 103, 104, 105 constitute a basic latch unit, the second external connection CLK _ SHIFT is clock (level sensitive), the first external connection SHIFT _ IN is data input, and the third external connection SHIFT _ OUT is data output. When CLK _ SHIFT is at high level, the latch samples the data of SHIFT _ IN to latch the data; when CLK _ SHIFT is low, the latch holds the data.
5. Flip-flop
Using two basic memory cells of the present invention and both configured as the latches described IN d above to cascade, i.e. connecting the output port SHIFT _ OUT of the 1 st latch to the input port SHIFT _ IN of the 2 nd latch, and inverting the input ports CLK _ SHIFT of the two basic cells, a flip-flop is formed.
6. Shift register
The even number of 4 or more basic memory cells are used, every two basic memory cells form the trigger described in the above-mentioned e, then the triggers are cascaded, so that the 2, 3, 4 and 5 … … bit shift register can be formed.
Claims (2)
1. A multi-function memory circuit, comprising:
the current output end of the first MOS tube is grounded, and the grid end of the first MOS tube is connected with the first external connecting end;
the current output end of the second MOS tube is connected with the first external connecting end, the current input end of the second MOS tube is connected with the third external connecting end, and the grid end of the second MOS tube is connected with the second external connecting end;
the current output end of the third MOS tube is connected with the current input end of the first MOS tube, the current input end of the third MOS tube is connected with the first reference point, and the grid end of the third MOS tube is connected with the second external connecting end;
the current output end of the sixth MOS tube is connected with the fourth external connecting end, the current input end of the sixth MOS tube is connected with the third external connecting end, and the grid end of the sixth MOS tube is connected with the fifth external connecting end;
a current output end of the seventh MOS tube is connected with the ninth external connecting end, a current input end of the seventh MOS tube is connected with the first reference point, and a grid end of the seventh MOS tube is connected with the fifth external connecting end;
the current output end of the eighth MOS tube is connected with the sixth external connecting end, the current input end of the eighth MOS tube is connected with the fourth external connecting end, and the grid end of the eighth MOS tube is connected with the seventh external connecting end;
a current output end of the ninth MOS tube is connected with the eighth external connecting end, a current input end of the ninth MOS tube is connected with the ninth external connecting end, and a grid end of the ninth MOS tube is connected with the seventh external connecting end;
the input end of the fourth inverter is connected with the third external connecting end, and the output end of the fourth inverter is connected with the first reference point;
the output end of the fifth inverter is connected with the third external connecting end, and the input end of the fifth inverter is connected with the first reference point;
the substrate of each MOS tube is grounded.
2. An integrated circuit chip, characterized in that a multifunctional memory circuit is built in, the multifunctional memory circuit comprising:
the current output end of the first MOS tube is grounded, and the grid end of the first MOS tube is connected with the first external connecting end;
the current output end of the second MOS tube is connected with the first external connecting end, the current input end of the second MOS tube is connected with the third external connecting end, and the grid end of the second MOS tube is connected with the second external connecting end;
the current output end of the third MOS tube is connected with the current input end of the first MOS tube, the current input end of the third MOS tube is connected with the first reference point, and the grid end of the third MOS tube is connected with the second external connecting end;
the current output end of the sixth MOS tube is connected with the fourth external connecting end, the current input end of the sixth MOS tube is connected with the third external connecting end, and the grid end of the sixth MOS tube is connected with the fifth external connecting end;
a current output end of the seventh MOS tube is connected with the ninth external connecting end, a current input end of the seventh MOS tube is connected with the first reference point, and a grid end of the seventh MOS tube is connected with the fifth external connecting end;
the current output end of the eighth MOS tube is connected with the sixth external connecting end, the current input end of the eighth MOS tube is connected with the fourth external connecting end, and the grid end of the eighth MOS tube is connected with the seventh external connecting end;
a current output end of the ninth MOS tube is connected with the eighth external connecting end, a current input end of the ninth MOS tube is connected with the ninth external connecting end, and a grid end of the ninth MOS tube is connected with the seventh external connecting end;
the input end of the fourth inverter is connected with the third external connecting end, and the output end of the fourth inverter is connected with the first reference point;
the output end of the fifth inverter is connected with the third external connecting end, and the input end of the fifth inverter is connected with the first reference point;
the substrate of each MOS tube is grounded.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986958A (en) * | 1998-01-30 | 1999-11-16 | Xilinx, Inc. | DRAM configuration in PLDs |
| US7161841B1 (en) * | 2005-06-29 | 2007-01-09 | Actel Corporation | Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage |
| CN101252018A (en) * | 2007-09-03 | 2008-08-27 | 清华大学 | Ferroelectric Programmable Information Storage Cell Using Novel Sequential Operation |
| US7684232B1 (en) * | 2007-09-11 | 2010-03-23 | Xilinx, Inc. | Memory cell for storing a data bit value despite atomic radiation |
| CN102282623A (en) * | 2009-01-15 | 2011-12-14 | 阿尔特拉公司 | Non-volatile memory circuit including voltage divider with phase change memory devices |
| CN102956261A (en) * | 2011-08-23 | 2013-03-06 | 深圳市国微电子股份有限公司 | Programmable memory cell circuit for FPGA (field programmable gate array) |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN107508594A (en) * | 2017-07-14 | 2017-12-22 | 成都华微电子科技有限公司 | Low-power consumption SRAM type FPGA |
| US10360333B1 (en) * | 2018-03-09 | 2019-07-23 | Kabushiki Kaisha Toshiba | Configuration memory circuit |
| JP2019160371A (en) * | 2018-03-14 | 2019-09-19 | 株式会社東芝 | Memory circuit and electronic device |
| CN110532222A (en) * | 2019-08-30 | 2019-12-03 | 中国电子科技集团公司第五十八研究所 | A kind of FPGA switch unit based on STT-MRAM |
-
2020
- 2020-06-19 CN CN202010563369.9A patent/CN111723045B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5986958A (en) * | 1998-01-30 | 1999-11-16 | Xilinx, Inc. | DRAM configuration in PLDs |
| US7161841B1 (en) * | 2005-06-29 | 2007-01-09 | Actel Corporation | Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage |
| CN101252018A (en) * | 2007-09-03 | 2008-08-27 | 清华大学 | Ferroelectric Programmable Information Storage Cell Using Novel Sequential Operation |
| US7684232B1 (en) * | 2007-09-11 | 2010-03-23 | Xilinx, Inc. | Memory cell for storing a data bit value despite atomic radiation |
| CN102282623A (en) * | 2009-01-15 | 2011-12-14 | 阿尔特拉公司 | Non-volatile memory circuit including voltage divider with phase change memory devices |
| CN102956261A (en) * | 2011-08-23 | 2013-03-06 | 深圳市国微电子股份有限公司 | Programmable memory cell circuit for FPGA (field programmable gate array) |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN107508594A (en) * | 2017-07-14 | 2017-12-22 | 成都华微电子科技有限公司 | Low-power consumption SRAM type FPGA |
| US10360333B1 (en) * | 2018-03-09 | 2019-07-23 | Kabushiki Kaisha Toshiba | Configuration memory circuit |
| JP2019160371A (en) * | 2018-03-14 | 2019-09-19 | 株式会社東芝 | Memory circuit and electronic device |
| CN110532222A (en) * | 2019-08-30 | 2019-12-03 | 中国电子科技集团公司第五十八研究所 | A kind of FPGA switch unit based on STT-MRAM |
Non-Patent Citations (2)
| Title |
|---|
| 张惠国;唐玉兰;于宗光;陶宇峰;: "FPGA高性能查找表的设计与实现" * |
| 杨海钢;孙嘉斌;王慰;: "FPGA器件设计技术发展综述" * |
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