CN111722821B - Method and device for realizing input and output of high-definition multimedia interface - Google Patents
Method and device for realizing input and output of high-definition multimedia interface Download PDFInfo
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Abstract
The invention discloses a realization method of input and output of a high-definition multimedia interface, which comprises the steps that business logic running in programmable logic PL of a programmable logic array FPGA obtains input and output configuration parameters of the high-definition multimedia interface HDMI from a non-bare computer program with an operating system in a processing system PS running in the FPGA through a bus protocol, and configures the input and output configuration parameters to an input and output function IP soft core HDMI-IP for realizing the HDMI, and the HDMI-IP soft core is operated according to the business logic to process an input signal into a required output signal. The invention enables the HDMI-IP soft core and the business logic in the FPGA to be flexibly configured and deployed as the business application development supported by the system, thereby realizing the input and output of the high-definition multimedia interface in the business angle and improving the compatibility and the expandability of the realized high-definition multimedia interface function.
Description
Technical Field
The invention relates to the field of high-definition video signal input and output, in particular to a method for realizing high-definition multimedia interface (HDMI) input and output.
Background
The high definition multimedia interface (High Definition Multimedia Interface) is a fully digital video and audio transmission interface that can transmit uncompressed audio and video signals.
A more typical scheme of the existing HDMI input-output technology is based on a programmable logic array (FPGA) scheme. Referring to fig. 1, fig. 1 is a schematic diagram of an architecture for implementing a high-definition multimedia interface based on an FPGA in the prior art. From a functional perspective, the FPGA includes a processing system (PS, processing System) in which a plurality of sub-logic arrays are deployed in the PL section for implementing an input-output function IP soft core set of HDMI, also referred to as an HDMI-IP soft core set, and programmable logic PL (Programmable Logic), in which an original bare metal program (stand clone) without an operating system is run. The HDMI-IP soft cores run under the control of the bare metal program, so that the functions of input signal analysis and identification, output signal coding synthesis and the like of HDMI signals are realized, the HDMI-IP soft core and bare metal program architecture is provided, and the input signals are output after being cooperatively processed by a plurality of soft cores in the HDMI-IP soft core set. The method avoids the defect that the traditional AD & DA chip mode is excessively dependent on a specific AD & DA chip, for example, due to the performance limitation of the AD & DA chip, the video compatibility of high definition is insufficient, and once the circuit design is solidified, the corresponding video processing characteristics and performance are solidified, so that the method is not beneficial to the function upgrading and replacement of the same product platform.
The existing FPGA-IP soft core and bare metal program architecture excessively depends on the internal logic of the FPGA, the external configuration depends on the bare metal program with single performance characteristics, the functions of perfect detection, management, debugging and the like are lacking, and the integration with the top-layer application service logic is not facilitated, so that the problems of low development iteration speed, long development period and the like of the HDMI video scheme of the HDMI-IP soft core based on the FPGA are caused.
Disclosure of Invention
The invention provides a method for realizing input and output of a High Definition Multimedia Interface (HDMI) so as to facilitate deployment of HDMI-IP soft cores.
The invention provides a method for realizing input and output of a high-definition multimedia interface, which comprises the following steps,
service logic running in programmable logic PL of the programmable logic array FPGA obtains input and output configuration parameters of a high definition multimedia interface HDMI from a non-bare computer program with an operating system in a processing system PS running in the FPGA through a bus protocol and configures the input and output configuration parameters to an input and output function IP soft core HDMI-IP for realizing HDMI,
and operating the HDMI-IP soft core according to the service logic, and processing an input signal into a required output signal.
Preferably, the non-bare computer program comprises a driver and a service application program, wherein the driver and the service application program are installed in an operating system, and the driver provides a service function interface for the service application program and accesses the IP soft core through a bus protocol;
wherein,,
the driver includes the following functional programs: the method comprises the steps of initializing and configuring global resources and HDMI-IP soft cores, entering a main program of a business logic processing flow, a bus interaction program for accessing PL by PS through a bus protocol, and an application function and an interface program for realizing an HDMI function interface for a business application program;
the HDMI-IP soft core comprises at least more than one HDMI-IP soft core for processing m paths of input signals into n paths of output signals, wherein m and n are natural numbers.
Preferably, the operating system is a Linux system, the bus protocol is an advanced extensible interface AXI bus protocol, the bus interactive program is an AXI interactive program,
the driver accessing the IP soft core via a bus protocol includes,
when the AXI interaction program reads and writes data through the AXI bus and any IP soft core in the PL, the AXI interaction program maps a register for accessing the AXI bus in the PL to a reserved memory space in the PS and encapsulates a read-write access interface for reading and writing the memory in the AXI section; the reserved memory space comprises an AXI interval memory for AXI interaction;
during read-write operation, an AXI read-write interface applies for AXI interval memory mapping, and performs read-write operation on the AXI interval memory according to a configured data packet structure;
the data packet structure comprises a type code, data content CRC check and a data packet end code.
Preferably, the HDMI-IP soft cores include an HDMI-IP soft core for processing an input signal and an HDMI-IP soft core for processing an output signal;
the service logic running in the programmable logic PL of the programmable logic array FPGA obtains input and output configuration parameters of the high-definition multimedia interface HDMI from a non-bare computer program with an operating system running in the processing system PS of the FPGA through a bus protocol, and configures the input and output configuration parameters to an input and output function IP soft core HDMI-IP for implementing HDMI, including,
the main program configures global resources, after initializing each function program in the driver program and each HDMI-IP soft core for realizing business application, starting business logic,
the service logic obtains configuration parameters for processing the input signals and configuration parameters for processing the output signals through an AXI interaction program and respectively configures the configuration parameters to an HDMI-IP soft core for processing the input signals and an HDMI-IP soft core for processing the output signals;
and according to service logic, operating the HDMI-IP soft core for processing the input signal, and operating the HDMI-IP soft core for processing the output signal, and processing the output signal.
Preferably, the driver further comprises an interrupt processing program for receiving and processing interrupt information reported by the HDMI-IP soft core, wherein the interrupt processing program comprises a Linux bottom layer driver process for interrupting reporting, and a Linux application layer process for providing callback functions for each interrupt to carry out branch processing.
Preferably, the method further comprises the steps of,
when the HDMI-IP soft core is interrupted in the running process, the interruption information is reported to the Linux bottom driving process in the interruption processing program,
the Linux bottom layer driving process receives the interruption information from the HDMI-IP soft core or carries out interruption detection on the PL;
performing interrupt counting on the acquired HDMI-IP soft core interrupt information, and updating an interrupt mark record;
judging whether interrupt inquiry from the Linux application layer process exists or not, if so, reporting each interrupt information to the Linux application layer process, and updating interrupt records; clearing the reported interrupt count, and clearing an interrupt mark until the interrupt recorded by the interrupt record is reported to the Linux application layer process;
the Linux application layer process inquires interrupt information from a Linux bottom layer driving process, determines a corresponding callback function according to the inquired interrupt information and an AXI read-write interface, and calls the corresponding callback function to perform interrupt processing, wherein the callback function defines an interface and/or parameters of the callback function in a registration mode, the callback function comprises at least one processing function, and the processing function is obtained from registration of the callback function.
Preferably, the driver further comprises a debugging and monitoring program for monitoring and recording the running states of all drivers and/or the respective HDMI-IP soft cores,
the method may further comprise the steps of,
in the debugging phase, the debugging and monitoring program performs debugging control on the HDMI and records at least one of the following information: the state of each HDMI-IP soft core, the running state of the driver, the system state, the time stamp information and the history information,
in normal operating conditions, the debugging and monitoring program monitors and records at least one of the following information: the current state of each HDMI-IP soft core, the current running state of the driver, the system state, the time stamp information and the history information.
Preferably, the driver further includes a console interaction program for command interaction with the user operation console, the console interaction program including one of a print redirection function, an interaction control interface function, an interaction tool function for interaction with the console, or any combination thereof;
the application functions and interface programs comprise at least one of the following functional controls:
a first functionality control for HDMI interface receive path selection,
a second function control for acquiring the data format received by the HDMI interface,
a third function control for acquiring the connection state of the received data of the HDMI interface,
a fourth function control for acquiring the connection state of the HDMI transmitting data;
a fifth function control for configuring the HDMI interface to locally transmit output;
a sixth function control for acquiring a current selection path of the HDMI;
a seventh function control for configuring the extended display capability identification EDID received by the HDMI interface;
and the eighth function control is used for acquiring the identification of the extended display capability sent by the HDMI interface.
The invention provides a device for realizing input and output of a high-definition multimedia interface, which comprises,
the service logic module running in the PL of the FPGA obtains the input and output configuration parameters of the HDMI from the non-bare computer program module running in the PS of the FPGA and with an operating system through a bus protocol, and configures the input and output configuration parameters to the HDMI-IP soft core module for realizing the input and output functions of the HDMI,
and the HDMI-IP soft core module operates the HDMI-IP soft core according to the service logic to process the input signal into a required output signal.
The invention also provides a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program realizes the steps of the method for realizing the input and the output of the high-definition multimedia interface when being executed by a processor.
According to the implementation method of the high-definition multimedia interface input and output, through the non-bare computer program with an operating system in the processing system PS running in the FPGA, an interaction channel between the PS and the PL is established downwards, and an interaction channel between the PS and service application is established upwards, so that HDMI-IP soft cores and service logic in the FPGA can be flexibly configured and deployed as the service application development supported by the system, the high-definition multimedia interface input and output is realized in terms of service, and the compatibility and the expandability of the realized high-definition multimedia interface function are improved; furthermore, the functions of the high-definition multimedia interface are improved through the driving programs with multiple functions, and debugging in the development process is facilitated and troubleshooting of the high-definition multimedia interface in the working state is facilitated through the debugging and monitoring functions in the driving programs.
Drawings
Fig. 1 is a schematic diagram of an architecture for implementing a high-definition multimedia interface based on an FPGA in the prior art.
Fig. 2 is a schematic diagram of a system architecture for implementing HDMI input/output according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of the software included in the driver.
Fig. 4 is a schematic diagram of a flow of the main program.
FIG. 5 is a schematic diagram of an application and DSP call included in the APP functionality and interface routine.
FIG. 6 is a schematic diagram of an interrupt handler handling interrupts.
Fig. 7 is a schematic flow chart of interruption reporting of a Linux bottom-layer driving process.
FIG. 8 is a flow chart of interrupt handling by a Linux application layer process.
FIG. 9 is a schematic diagram of the interactive functions included in the console interactive program.
FIG. 10 is a schematic diagram of the debugging and monitoring functions included in the debugging and monitoring program.
Fig. 11 is a schematic diagram of an AXI interactive program implementing an access mechanism for an AXI bus.
Fig. 12 is a schematic diagram of an embodiment of implementing HDMI interface input/output according to the architecture of the present invention.
Fig. 13 is a flow chart illustrating a process of inputting an input signal to output in the HDMI input/output device.
Fig. 14 is a schematic diagram of an implementation apparatus of input/output of the high-definition multimedia interface.
Detailed Description
In order to make the objects, technical means and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings.
The invention constructs at least a driver for HDMI-IP soft core in PL of FPGA in PS of FPGA as non-bare computer program, which controls flexible deployment and development of input and output functions of HDMI according to business logic in FPGA, wherein, the driver and HDMI-IP soft core are accessed by bus protocol, the non-bare computer program is a program with operating system and capable of running on embedded platform. For example, a Linux system program.
Referring to fig. 2, fig. 2 is a schematic diagram of a system architecture for implementing HDMI interface input/output according to an embodiment of the present invention. The system includes a system program running Linux operating system in PS of FPGA, a PL including HDMI-IP soft core and service LOGIC, and a hardware layer (not shown in the figure) for providing physical bearers for PS and PL, which can be understood as an actual hardware circuit design. The system program mainly comprises a driving program HDMI_DRV and a service application program APP, wherein the HDMI_DRV upwards provides an HDMI related functional interface of the service application program APP, is responsible for managing an HDMI-IP soft core set in PL downwards and realizes service interaction with a service LOGIC LOGIC. HDMI-IP soft cores in PL, service LOGIC, and hdmi_drv in PS interact through a bus protocol such as an advanced extensible interface (AXI) bus.
Referring to fig. 3, fig. 3 is a schematic diagram of functional software included in a driver, where the driver includes a main body program, an Application (APP) function and an interface program, an interrupt handler, a console interactive program, a debug and monitor program, and an AXI interactive program.
Wherein,,
and the main program performs initialization configuration on the global resource and the HDMI-IP soft core set according to service application from the service application program, and finally enters a service logic processing flow of the HDMI-IP soft core for processing the input signal into a corresponding output signal.
The APP function and the interface program are used for providing an HDMI function interface for the service application program and implementing internal functions of the HDMI interface.
The interrupt processing program is used for receiving and processing interrupt information reported by the HDMI-IP soft core set; the interrupt processing adopts the interrupt report of a Linux bottom-layer driving process, and is matched with the interrupt detection operation of a Linux application-layer process, such as select response, so as to ensure the real-time performance of interrupt response; and the Linux application layer process provides a callback function for each interrupt to carry out branch processing.
The console interaction program is used for carrying out command interaction with the user operation console.
The debugging and monitoring program is used for monitoring and recording the running state of the whole HDMI_DRV and/or the state of each HDMI-IP soft core in the HDMI-IP soft core set.
AXI interactivity is used for implementation of HDMI-IP soft cores and service LOGIC in PL with driver interactivity channels in PS other than AXI interactivity.
Each of the software programs in the driver is explained below.
Referring to fig. 4, fig. 4 is a schematic diagram showing a flow of a main program, in which an initialization global parameter, a parameter in an AXI interactive program, a parameter in each IP soft core, a parameter in an interrupt program, a parameter in a debug and monitor program, and a parameter in an interactive program are initialized, and after the parameter in each program is initialized, a main service logic in PL is started, and the operation of each HDMI-IP soft core for processing a current input signal into an output signal is controlled according to the main service logic.
The above-mentioned initialization of the various parameters of the various software functional programs may not be in sequence and the initialization of the functional parameters may not be performed for the software functions that do not currently need to be run, for example, the debugging and monitoring programs may be initialized during the debugging phase and the initialization of the parameters may not be performed during the non-debugging phase.
Referring to fig. 5, fig. 5 is a schematic diagram of an APP function and an application and DSP call included in an interface program. The APP function and interface program comprises a first function control used for selecting an HDMI interface receiving passage, a second function control used for acquiring an HDMI interface receiving data format, a third function control used for acquiring an HDMI interface receiving data connection state, a fourth function control used for acquiring an HDMI interface sending data connection state, a fifth function control used for configuring HDMI interface local sending output, a sixth function control used for acquiring an HDMI interface current selecting passage, a seventh function control used for configuring HDMI interface receiving extended display capability identification (EDID), and an eighth function control used for acquiring HDMI interface sending extended display capability identification. It should be understood that the above-described functions are not limited thereto, but may be developed and selected according to actual needs.
Referring to FIG. 6, FIG. 6 is a schematic diagram of an interrupt handler handling interrupts. The interrupt processing program comprises a Linux bottom layer driving process for interrupt reporting and a Linux application layer process for providing callback functions for each interrupt to carry out branch processing.
Referring to fig. 7, fig. 7 is a schematic flow chart of interruption reporting of a Linux bottom-layer driving process. The Linux bottom driving process obtains HDMI-IP soft core interrupt information in PL, for example, receives HDMI-IP soft core interrupt information from PL, or detects the interruption of PL; when the HDMI-IP soft core interrupt information is obtained, interrupt counting is carried out, and an interrupt mark is updated so as to record the current interrupt; judging whether interrupt inquiry of the Linux application layer process exists, if so, reporting each interrupt information to the Linux application layer process, updating the interrupt record, clearing the reported interrupt count, and clearing the interrupt mark until the interrupt recorded by the interrupt record is reported to the Linux application layer process.
Referring to fig. 8, fig. 8 is a schematic flow chart of interrupt processing performed by a Linux application layer process. Firstly, registering callback functions to define interfaces and/or parameters of each callback function so as to establish callback function sets, then, performing interrupt detection, namely, inquiring whether interrupt report exists to a Linux bottom driving process, if yes, determining the corresponding callback function according to interrupt information and a read-write interface of an AXI, and calling the corresponding callback function to perform interrupt processing; wherein the callback function comprises several processing functions, which can be correspondingly obtained from the registration of the callback function.
Referring to fig. 9, fig. 9 is a schematic diagram of the interactive functions included in the console interactive program. The console interaction program includes one or any combination of print redirection functionality, interaction control interface functionality, and interaction tool functionality for interacting with the console.
Referring to fig. 10, fig. 10 is a schematic diagram of the debugging and monitoring functions included in the debugging and monitoring program. In the debugging stage, the debugging and monitoring program performs debugging control on the HDMI and records at least one of the following information: the state of each HDMI-IP soft core, the running state of a driver, the system state, timestamp information and history information; in normal operating conditions, the debugging and monitoring program monitors and records at least one of the following information: the current state of each HDMI-IP soft core, the current running state of the driver, the system state, the time stamp information and the history information; the debugging and monitoring program comprises a printing grade control function, a system state recording function, an HDMI debugging control function, a time stamp recording function and a history information recording function.
It should be understood that the interactive functions included in the console interactive program, and the debugging and monitoring functions included in the debugging and monitoring program may not be limited to the above functions, and may be developed according to actual requirements.
In the existing bare engine control program, the read-write access of the bus is realized by adopting a mode of directly accessing the register, and in Linux, the read-write operation of the access register cannot be directly performed due to the memory remapping and a memory management mechanism. In view of this, the present invention maps the access registers of the AXI bus in PL to a specific reserved memory space of PS, which contains the AXI interval memory for AXI interaction; the AXI interaction program manages the memory space of the AXI interval by adopting a memory mapping application mode, independently encapsulates a read-write access interface for reading and writing the memory of the AXI interval, and can realize the read-write operation of corresponding bit numbers, such as one of 8 bits, 16 bits, 32 bits and 64 bits or the read-write operation of any combination according to the requirement of HDMI-IP soft core configuration.
Referring to fig. 11, fig. 11 is a schematic diagram of an AXI interactive program implementing an AXI bus access mechanism. In the figure, when the AXI interactive program reads and writes data through the AXI bus and any HDMI-IP soft core in the PL, the AXI interactive program maps a register for access of the AXI bus in the PL into a specific reserved memory space of PS; during the reading and writing process, the AXI reading and writing interface applies for AXI interval memory mapping, and performs reading and writing operation on the AXI interval memory according to the configured data packet structure. The data packet structure comprises 4 bytes of type codes, n bytes of data contents, 4 bytes of CRC check of the data contents and 4 bytes of data packet end codes. The CRC check of the data content is used for guaranteeing the correctness of the read-write operation. Through the AXI bus access mechanism, the AXI interaction program realizes communication between the HDMI-IP soft core and the driver.
Referring to fig. 12, fig. 12 is a schematic diagram of an embodiment of implementing HDMI interface input/output according to the architecture of the present invention. Through m HDMI inputs, which may be a PC or any other and forced source as an input source, and outputs output signals of any n resolutions according to specific needs, may be output to connect various LCD or LED display devices. m and n are natural numbers.
The HDMI input/output device comprises an FPGA module, wherein a system program with an operating system, such as a Linux system, is configured in PS of the FPGA; the method comprises the steps of configuring m paths of input, n arbitrary resolution outputs and service application of display equipment parameters connected with all the outputs through a service application program in a Linux system, wherein the configuration of the service application can be carried out through an APP function and an interface program; in PL of the FPGA, each HDMI-IP soft core and service logic required to process m-way input into n resolutions are configured, and each HDMI-IP soft core and service logic is debugged by a debugging and monitoring program in a debugging stage.
Referring to fig. 13, fig. 13 is a schematic flow chart of a process of inputting a signal to output in the HDMI interface input/output device. When any input signal is input into the HDMI input/output device and output at any resolution (hereinafter referred to as input/output service for convenience of description), the FPGA module in the HDMI input/output device performs the following processing:
step 1301, the main program in the linux system configures global resources, and initializes AXI interactive program, interrupt handler, debug and monitor program, console interactive program, AXI interactive program, and various HDMI-IP soft cores for implementing the input/output service,
step 1302, enabling the service logic in PL by the main program, configuring required parameters to each HDMI-IP soft core for implementing the input/output service through AXI bus protocol, so that each HDMI-IP soft core operates in coordination with the service logic based on the input signal, and processes the input signal into a required output signal, for example, implementing input signal parsing and identification of the HDMI signal, output signal encoding synthesis, and the like;
in this step, parameters required for the HDMI-IP soft core for frame format processing are configured to the HDMI-IP soft core by an AXI interactive program, for example, according to a frame format, and the first HDMI-IP soft core is operated in accordance with service logic; according to the frame rate, configuring parameters required by the HDMI-IP soft core for frame rate processing to the HDMI-IP soft core through an AXI interactive program, and operating the HDMI-IP soft core according to service logic; … and so on.
For another example, the service logic obtains configuration parameters for processing the input signal and configuration parameters for processing the output signal through an AXI interactive program, and configures the configuration parameters to an HDMI-IP soft core for processing the input signal and an HDMI-IP soft core for processing the output signal respectively; and according to service logic, operating the HDMI-IP soft core for processing the input signal, and operating the HDMI-IP soft core for processing the output signal, and processing the output signal.
Taking as an example the implementation of the input output traffic of the video input signal of the first resolution, the video output signal of the second resolution, in this step,
for a video input signal of a first resolution, the processing steps are as follows:
(1) Acquiring a basic clock of an input signal through an AXI interaction program, calculating clock parameters, configuring the clock parameters to a first HDMI-IP soft core for video clock analysis, operating the first HDMI-IP soft core according to service logic, and locking a video clock of the input signal;
(2) Obtaining video clock parameters obtained by locking a video clock by a first HDMI-IP soft core through an AXI interactive program, calculating a video data stream frame rate identification parameter, configuring the video data stream frame rate identification parameter to a second HDMI-IP soft core for carrying out frame rate identification on an input signal, operating the second HDMI-IP soft core according to service logic, and carrying out frame rate identification on the input video data stream;
(3) Acquiring frame rate parameters obtained by performing frame rate identification on a second HDMI-IP soft core through an AXI interaction program, calculating a video data stream analysis parameter, configuring the video data stream analysis parameter to a third HDMI-IP soft core for performing video time sequence and format identification on an input signal, operating the third HDMI-IP soft core according to service logic, and performing video time sequence and format identification on the input video data stream;
(4) Acquiring a video format acquired by video timing sequence and format identification of a third HDMI-IP soft core through an AXI interaction program, and configuring service logic for realizing the input and output service in PL so as to process an input video data stream;
the step of identifying the video input signal at the first resolution is thus completed.
The video output steps are as follows:
(1) Clock parameters calculated according to a video clock required by a video output signal are configured to a fourth HDMI-IP soft core for video clock synthesis through an AXI interaction program, the fourth HDMI-IP soft core is operated according to service logic, and the video clock of the output signal is locked;
(2) Configuring a fifth HDMI-IP soft core for synthesizing and outputting video data streams through an AXI interaction program, running the fifth HDMI-IP soft core according to service logic, and performing Display Data Channel (DDC) and State and Control Data Channel (SCDC) interaction under a second resolution with a service application through the AXI interaction program;
(3) And configuring the time sequence and format parameters calculated according to the time sequence and format required by the video output signal to a fifth HDMI-IP soft core for synthesizing and outputting the video data stream through an AXI interaction program, operating the fifth HDMI-IP soft core according to service logic, and entering a ready state for outputting the video data.
The processed video data stream is thus output in the format of a video output signal of the second resolution. Similarly, each input/output service can configure the required parameters to the HDMI-IP soft core through the AXI interaction program, and each HDMI-IP soft core is operated according to service logic, so that the input/output service is realized.
When parameters are configured to HDMI-IP soft core through AXI interaction program, mapping a register for accessing AXI bus in PL into PS-specific reserved memory space, wherein part of reserved memory is used as AXI interval memory; in the read-write process, the AXI read-write interface applies for an AXI interval memory, and performs read-write operation on the memory according to the configured data packet structure, so that parameters required by the HDMI-IP soft core are configured. The data packet structure comprises 4 bytes of type codes, n bytes of data contents, 4 bytes of CRC check of the data contents and 4 bytes of data packet end codes. The CRC check of the data content is used for guaranteeing the correctness of the read-write operation.
Step 1303, when any HDMI-IP soft core generates an interrupt in the running process, acquiring the interrupt by a Linux bottom driving process in the interrupt processing program, recording the number of times of the interrupt and an interrupt flag,
when a Linux application layer driving process in an interrupt processing program inquires an interrupt to a Linux bottom layer driving process, the Linux bottom layer driving process reports the interrupt to the Linux application layer driving process;
the Linux application layer driver judges the interruption, determines the corresponding callback function, and calls the callback function to process each interruption.
Through the steps 1301-1303, the control of the HDMI-IP soft core is realized, so that the input/output service is realized.
Step 1304, to monitor the operation of the input/output service, the current state may be recorded and/or the history information may be recorded by a debug and monitor program; and/or to interact with the console through a console interaction program.
The control mode of Linux+FPGA-IP soft core is used, so that flexible deployment and development of the input and output video of the HDMA interface, such as 4K ultra-high definition, are realized; through the use of the FPGA-IP soft core, the defect that the traditional AD & DA mode excessively depends on a specific AD & DA chip is avoided; the control of the IP core is integrated into the drive of the Linux system, so that the defects of low development speed and high debugging difficulty commonly existing in the FPGA-IP soft core and bare program architecture are avoided by utilizing rich debugging and development interfaces of the Linux system, and the advantages of integrated and cooperative processing of the control of the IP core and the Linux layer business application are realized, and the product functions can be updated and upgraded rapidly and flexibly according to the specific application scene requirement development under the condition of not modifying a single board circuit. So that various business requirements have expandability and flexibility.
Referring to fig. 14, fig. 14 is a schematic diagram of an implementation apparatus of input/output of a high definition multimedia interface according to the present invention, which includes,
a non-bare computer program module running a non-bare computer program with an operating system in the PS of the FPGA,
the service logic module running in the PL of the FPGA obtains the input and output configuration parameters of the high-definition multimedia interface HDMI from the non-bare engine program module through a bus protocol and configures the input and output configuration parameters to the HDMI-IP soft core module for realizing the input and output functions of the HDMI,
and the HDMI-IP soft core module runs the HDMI-IP soft core according to the service logic and processes the input signal into a required output signal.
The embodiment of the invention also provides a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program realizes the steps of the method for realizing the input and output of the high-definition multimedia interface when being executed by a processor.
For the apparatus/network side device/storage medium embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and the relevant points are referred to in the description of the method embodiment.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.
Claims (10)
1. A method for realizing input and output of a high definition multimedia interface is characterized in that the method comprises the following steps,
service logic running in programmable logic PL of the programmable logic array FPGA obtains input and output configuration parameters of a high definition multimedia interface HDMI to a non-bare computer program with an operating system running in a processing system PS of the FPGA through a bus protocol, and configures the input and output configuration parameters to an HDMI-IP soft core for realizing the input and output functions of the HDMI,
operating the HDMI-IP soft core according to the service logic, and processing an input signal into a required output signal;
wherein,,
the non-bare engine programs include a driver installed in the operating system that provides a business function interface to the business application program, accessing the HDMI-IP soft core via a bus protocol.
2. The method of claim 1, wherein the driver comprises the following functional program: the method comprises the steps of initializing and configuring global resources and HDMI-IP soft cores, entering a main program of a business logic processing flow, a bus interaction program for accessing PL by PS through a bus protocol, and an application function and an interface program for realizing an HDMI function interface for a business application program;
the HDMI-IP soft core comprises at least one HDMI-IP soft core for processing m paths of input signals into n paths of output signals, wherein m and n are natural numbers.
3. The method of claim 2, wherein the operating system is a Linux system, the bus protocol is an advanced extensible interface AXI bus protocol, the bus interworking program is an AXI interworking program,
the driver accessing the IP soft core via a bus protocol includes,
when the AXI interaction program reads and writes data through the AXI bus and any IP soft core in the PL, the AXI interaction program maps a register for accessing the AXI bus in the PL to a reserved memory space in the PS and encapsulates a read-write access interface for reading and writing the memory in the AXI section; the reserved memory space comprises an AXI interval memory for AXI interaction;
during read-write operation, an AXI read-write interface applies for AXI interval memory mapping, and performs read-write operation on the AXI interval memory according to a configured data packet structure;
the data packet structure includes a type code, data content, a data content CRC check, and a data packet end code.
4. The method of claim 3, wherein the HDMI-IP soft core comprises an HDMI-IP soft core for processing an input signal and an HDMI-IP soft core for processing an output signal;
the service logic running in the programmable logic PL of the programmable logic array FPGA obtains the input and output configuration parameters of the high-definition multimedia interface HDMI from the non-bare computer program running in the processing system PS of the FPGA and configures the input and output configuration parameters to the HDMI-IP soft core for implementing the input and output functions of the HDMI, including,
the main program configures global resources, after initializing each function program in the driver program and each HDMI-IP soft core for realizing business application, starting business logic,
the service logic obtains configuration parameters for processing the input signals and configuration parameters for processing the output signals through an AXI interaction program and respectively configures the configuration parameters to an HDMI-IP soft core for processing the input signals and an HDMI-IP soft core for processing the output signals;
and according to service logic, operating the HDMI-IP soft core for processing the input signal, and operating the HDMI-IP soft core for processing the output signal, and processing the output signal.
5. The method of claim 4, wherein the driver further comprises an interrupt handler for receiving and processing interrupt information reported by the HDMI-IP soft core, the interrupt handler comprising a Linux underlying driver process for interrupt reporting, and a Linux application layer process for providing callback functions for each interrupt for branching.
6. The method of claim 5, further comprising,
when the HDMI-IP soft core is interrupted in the running process, the interruption information is reported to the Linux bottom driving process in the interruption processing program,
the Linux bottom layer driving process receives interrupt information from the HDMI-IP soft core, or carries out interrupt detection on PL;
performing interrupt counting on the acquired HDMI-IP soft core interrupt information, and updating an interrupt record;
judging whether interrupt inquiry from the Linux application layer process exists or not, if so, reporting each interrupt information to the Linux application layer process, and updating interrupt records; clearing the reported interrupt count, and clearing the interrupt record until the interrupt recorded by the interrupt record is reported to the Linux application layer process;
the Linux application layer process inquires interrupt information from a Linux bottom layer driving process, determines a corresponding callback function according to the inquired interrupt information and an AXI read-write interface, and calls the corresponding callback function to perform interrupt processing, wherein the callback function defines an interface and/or parameters of the callback function in a registration mode, the callback function comprises at least one processing function, and the processing function is obtained from registration of the callback function.
7. The method of claim 4, wherein the driver further comprises a debug and monitor program for monitoring and recording the operating status of all drivers and/or individual HDMI-IP soft cores,
the method may further comprise the steps of,
in the debugging stage, the debugging and monitoring program performs debugging control on the HDMI and records at least one of the following information: the state of each HDMI-IP soft core, the running state of the driver, the system state, the time stamp information and the history information,
in normal operating conditions, the debugging and monitoring program monitors and records at least one of the following information: the current state of each HDMI-IP soft core, the current running state of the driver, the system state, the time stamp information and the history information.
8. The method of any of claims 2 to 7, wherein the driver further comprises a console interaction program for command interaction with a user-operated console, the console interaction program comprising one of a print redirection function, an interaction control interface function, an interaction tool function for interacting with the console, or any combination thereof;
the application functions and interface programs comprise at least one of the following functional controls:
a first functionality control for HDMI interface receive path selection,
a second function control for acquiring the data format received by the HDMI interface,
a third function control for acquiring the connection state of the received data of the HDMI interface,
a fourth function control for acquiring the connection state of the HDMI transmitting data;
a fifth function control for configuring the HDMI interface to locally transmit output;
a sixth function control for acquiring a current selection path of the HDMI;
a seventh function control for configuring the extended display capability identification EDID received by the HDMI interface;
and the eighth function control is used for acquiring the identification of the extended display capability sent by the HDMI interface.
9. An implementation device for high-definition multimedia interface input and output is characterized in that the device comprises,
the service logic module running in the PL of the FPGA is used for obtaining the input and output configuration parameters of the high-definition multimedia interface HDMI from the non-bare engine program module running in the PS of the FPGA and provided with an operating system through a bus protocol, and configuring the input and output configuration parameters to the HDMI-IP soft core module for realizing the input and output functions of the HDMI,
the HDMI-IP soft core module is used for operating the HDMI-IP soft core according to the service logic, processing the input signal into the required output signal,
wherein,,
the non-bare engine program module comprises a driver and a business application program, wherein the driver and the business application program are installed in an operating system, and the driver provides a business function interface for the business application program and accesses the HDMI-IP soft core through a bus protocol.
10. A computer-readable storage medium, wherein a computer program is stored in the storage medium, which when executed by a processor, implements the method steps of implementing the high-definition multimedia interface input/output as claimed in any one of claims 1 to 8.
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