CN111710678B - Semiconductor memory device with a plurality of memory cells - Google Patents

Abstract

The invention discloses a semiconductor memory device, comprising a semiconductor substrate having a memory region and a peripheral region around the memory region, bit line structures located on the semiconductor substrate and extending in a first direction through the memory region and the peripheral region, spacer structures located between the bit line structures, storage node contact structures located in spaces defined by the spacer structures and the bit line structures in the memory region and connected to the semiconductor substrate, and a sacrificial layer located in the spaces defined by the spacer structures and the bit line structures in the peripheral region, the invention is characterized in that the memory cell area and the peripheral area of the device have the same cell arrangement, thereby solving the micro-loading effect problem caused by different pattern densities and providing more memory cell areas.

Description

Semiconductor memory device with a plurality of memory cells

Technical Field

Embodiments disclosed herein relate to a semiconductor memory device, and more particularly, to a semiconductor memory device having a spacer structure between bit lines and a bit line contact structure in a peripheral region.

Background

A memory device is an integrated circuit that is typically used in a computer system to store data in the form of one or more matrices of individual memory cells. The memory device can perform writing and reading operations using bit lines (also referred to as digit lines, data lines, or sense lines) that can be electrically connected to the memory cells along columns of the matrix and word lines (also referred to as access lines) that can be electrically connected to the memory cells along rows of the matrix. Each memory cell is individually addressable via a combination of a bit line and a word line.

The memory device may be volatile, semi-volatile, or non-volatile in nature. Non-volatile memory devices can store data for a long period of time without power, volatile memory devices dissipate the stored data and require constant refreshing/rewriting to maintain their data storage. The memory device uses a capacitor or other components to store charges, and reads the charges of the capacitor to determine which memory state the memory cell is in, such as a "0" or "1" memory state, so as to achieve the purpose of data storage and reading. The memory device also has electronic components such as transistors to control the switching of the gate and the storage and release of charge. Peripheral circuit regions exist around a memory cell array region of a memory device, and bit lines and word lines extend from the memory cell array region to the peripheral circuit region, where they are connected to external circuits via other interconnection structures such as wires and contacts.

In the fabrication of memory devices or other circuits, it is a constant goal of industry to continually shrink, and to make the components more compact, to achieve higher storage capacity per unit area. However, as memory devices continue to shrink, many problems to be overcome, such as micro-loading effect due to different pattern densities or insufficient layout space due to too tight a feature-to-feature structure, are encountered in the fabrication process. The present invention is motivated by overcoming some of the above-mentioned problems encountered in the fabrication of circuits.

Disclosure of Invention

In order to solve the problems encountered in the memory device process, the present invention provides a novel semiconductor memory device, which is characterized in that the memory cell region and the peripheral region of the device have the same cell arrangement, so as to solve the micro-loading effect problem caused by different pattern densities and to make more memory cell regions, and the bit line contact structure located in the peripheral region has an elongated shape and adopts a mode of alternately arranging the peripheral regions at two sides, so that the process tolerance of the contact structure during connection can be effectively increased, and the problem of insufficient space of layout space can be overcome.

One aspect of the present invention is to provide a semiconductor memory device, which includes a semiconductor substrate having a memory region and a peripheral region surrounding the memory region, bit line structures located on the semiconductor substrate and extending in a first direction through the memory region and the peripheral region, spacer structures located between the bit line structures, storage node contact structures located in spaces defined by the spacer structures and the bit line structures in the memory region and connected to the semiconductor substrate, and sacrificial layers located in spaces defined by the spacer structures and the bit line structures in the peripheral region.

Another aspect of the present invention is to provide a semiconductor memory device, including a semiconductor substrate, bit line structures on a device isolation layer in a peripheral region of the semiconductor substrate, spacer structures on the device isolation layer and between the bit line structures, a sacrificial layer on the device isolation layer and between the bit line structures, and bit line contact structures directly above the bit line structures, wherein each of the bit line contact structures is connected to one of the bit line structures in an alternating manner.

Another aspect of the present invention is to provide a semiconductor memory device, which includes a semiconductor substrate having a device isolation layer defining an active region, wherein the active region includes a first doped region located in the middle of the active region and two second doped regions located at two ends of the active region, respectively, and a word line embedded in the semiconductor substrate and passing through the active region between the first doped region and the second doped region.

These and other objects of the present invention will become more apparent to those skilled in the art after a reading of the following detailed description of the preferred embodiment illustrated in the various figures and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate some embodiments of the invention and together with the description serve to explain its principles. In these figures:

FIG. 1 is a plan view of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a cross-sectional view taken along line B-B' of FIG. 1;

FIG. 4 is a sectional view taken along line C-C' of FIG. 1;

FIG. 5 is a sectional view taken along line D-D' of FIG. 1;

FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 1 according to another embodiment of the present disclosure;

FIG. 7 is a sectional view taken along line E-E' of FIG. 1; and

fig. 8 is a plan view of a semiconductor memory device according to another embodiment of the present disclosure.

It should be noted that all the figures in this specification are schematic in nature, and that for the sake of clarity and convenience, various features may be shown exaggerated or reduced in size or in proportion, where generally the same reference signs are used to indicate corresponding or similar features in modified or different embodiments.

Wherein the reference numerals are as follows:

1a first doped region

1b second doped region

100 semiconductor substrate

102 memory cell area

104 peripheral region

106 insulating layer

108 spacer structure

110 storage node contact structure

112 sacrificial layer

114 bit line contact structure

114a upper half part

114b lower half part

116 external lead

118 device isolation layer

120 insulating interlayer

122 polysilicon layer

124 silicide layer

126 metal layer

128 hard mask layer

130 spacer wall

132 cover insulating layer

134 recessed area

136 bitline contact spacer

138 gate hard mask layer

140 gate insulating layer

ACT active region

BL bit line

In line C1

In line C2

D1 first direction

D2 second direction

Third direction D3

WL word line

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, which will reference features described with reference to the accompanying drawings so that the reader can understand and achieve the technical effects. It will be understood by the reader that the description herein is by way of illustration only and is not intended to be limiting. The various embodiments of the disclosure and the various features of the embodiments that are not mutually inconsistent can be combined or rearranged in various ways. Modifications, equivalents, or improvements therein may be apparent to those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

It should be readily understood by the reader that the meaning of "on …", "above …" and "above …" in this case should be read in a broad manner such that "on …" not only means "directly on" something "but also includes the meaning of" on "something with intervening features or layers therebetween, and" on … "or" above … "not only means" on "something" or "above" but also includes the meaning of "on" or "above" something with no intervening features or layers therebetween (i.e., directly on something).

Moreover, spatially relative terms such as "below …," "below …," "below," "above …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature, as illustrated in the figures.

As used herein, the term "substrate" refers to a material to which a subsequent material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any horizontal pair of surfaces at the top and bottom surfaces or between the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (where contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

In the drawings of the present specification, fig. 1 is a plan view illustrating a semiconductor memory device according to an embodiment of the present application, which illustrates a plan layout view of the present semiconductor memory device. Fig. 2 to 5 are cross-sectional views taken along lines a-a ', B-B', C-C ', and D-D' in fig. 1, respectively, illustrating relative positions and connections of components in the memory cell region and the peripheral region of the semiconductor memory device.

Please refer to fig. 1. The semiconductor memory device of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate, and/or a silicon germanium substrate. The semiconductor substrate 100 has a memory cell region 102 and a peripheral region 104 surrounding the memory cell region 102, the memory cell region 102 is used for arranging memory cells of the semiconductor memory device, and a plurality of memory cells are arranged in a matrix pattern in the memory cell region 102 and can store charges to generate a distinctive memory state. The peripheral region 104 is used for configuring peripheral circuits of the memory device, such as column decoders, row decoders, sense amplifiers, or I/O control modules. Active regions ACT are defined in the memory cell region 102 of the semiconductor substrate 100, and each active region ACT is separated by a surrounding device isolation layer. In the process, the device isolation layer may be formed by performing a photolithography process on the semiconductor substrate 100 to form respective separated active regions ACT, and filling the recess between the active regions ACT with an isolation material, such as silicon oxide. In an example, the active area ACT has a stripe shape in a plan view and has a long axis extending to the third direction D3. The plurality of active regions ACT are uniformly arranged in a staggered manner on a plane. It is noted that, for simplicity, only the portion of the peripheral region 104 on one side of the memory cell region 102 is shown in fig. 1, in practice, the peripheral region 104 is disposed around the memory cell region 102, and only the portion of the memory cell region 102 where the line C-C 'and the line D-D' pass through has the corresponding active region ACT drawn to compare the cross-sectional view thereof, and in practice, the active regions ACT are uniformly distributed over the entire memory cell region 102.

Refer back to fig. 1. The semiconductor substrate 100 is provided with a plurality of word line structures WL parallel to each other and spaced apart by a predetermined interval, and extending through the memory cell region 102 in a first direction D1. The semiconductor substrate 100 further has a plurality of bit line structures BL disposed parallel to each other and spaced apart by a predetermined distance, and extending through the memory cell region 102 and the peripheral region 104 in a second direction D2, wherein the second direction D2 is preferably orthogonal to the first direction D1, an angle between the third direction D3 and the first direction D1 is preferably between 45 degrees and 90 degrees, and an angle between the second direction D2 and the first direction D1 is preferably between 0 degrees and 45 degrees. The word line structure WL is usually embedded in the semiconductor substrate 100 and serves as an access transistor for controlling switching of a gate and access of charges, and the bit line structure BL is usually provided on the semiconductor substrate 100 and connected to the active region ACT for writing and reading. An insulating layer 106 is formed around the bit line structure BL to isolate the bit line structure BL from surrounding components.

Refer back to fig. 1. A plurality of spacer structures 108 are disposed between the bit line structures BL and the bit line structures BL on the semiconductor substrate 100, and are located substantially right above the word line structures WL and spaced apart from each other by a certain distance. In the memory cell region 102, the spacer structure 108 and the bit line structure BL may together define a storage node region on the semiconductor substrate 100, on which a storage node contact structure 110 is disposed. In practice, a charge storage element such as a capacitor is disposed on the storage node contact structure 110, but this element is not essential, and for simplicity of illustration, it will not be shown in the following figures. On the other hand, in the peripheral region 104, since there is no memory cell, the space defined by the spacer structure 108 and the bit line structure BL will not be used for disposing the storage node contact structure 110. Instead, the space is filled with the sacrificial layer 112, which is the portion left by the process of forming the spacer structure 108, and the original sacrificial layer in the memory cell region 102 is removed after the spacer structure 108 is formed, and the space is used to dispose the storage node contact structure 110.

In the present embodiment, a spacer structure 108 and a storage node contact structure 110 or a sacrificial layer 112 separated therefrom are disposed between the bit line structures BL in both the memory cell region 102 and the peripheral region 104. Either the spacer structure 108 or the sacrificial layer 112 is formed of a dielectric insulating material, but the materials are different. For example, the sacrificial layer 112 may be formed using spin-on hard mask (S0H) silicon oxide, and the spacer structure 108 may be formed using an insulating material having etch selectivity with respect to the sacrificial layer 112, such as silicon nitride. Such features are quite distinguishable from the known art. For the conventional technology, there is no spacer structure and sacrificial layer pattern between the bit line structures in the peripheral region, and only the memory cell region has such a lattice pattern. Therefore, in the prior art, the patterns of the peripheral region and the memory cell region are quite different, and on the basis of this, significant micro-loading effect exists in the process, so that the patterns formed by these regions are different and inconsistent with the predetermined pattern. In contrast, in the present embodiment, the peripheral region 104 and the memory cell region 102 are designed to have substantially similar grid patterns, so that the patterns formed in the two regions are more consistent during the manufacturing process, thereby greatly reducing the effect of uneven patterns caused by the micro-loading effect.

Refer back to fig. 1. In the peripheral region 104, a bit line contact structure 114 is further disposed above the bit line structure BL for connecting the bit line structure BL to an external conductive line 116, and further connecting the bit line structure BL to an external circuit, such as a column decoder, through the external conductive line 116, so that the column decoder selects a specific bit line structure BL to transmit data during operation. In the embodiment of the present invention, the bit line contact structures 114 are alternately disposed on the peripheral region 104 (only one side of which is shown) at two sides of the memory cell region 102, and the bit line contact structures 114 have an elongated shape, and the long side direction thereof is parallel to the second direction in which the bit line structures BL extend. More specifically, the long side of the bit line contact structure 114 may be longer than the length of the spacer structure 108 and/or the length of the sacrificial layer 112. The arrangement and features of the bit line contact structure 114 can effectively increase the process margin of the bit line contact structure 114 during connection, so as to overcome the problem of insufficient space in layout.

It is noted that in some embodiments, a dummy area or a redundant repair area may be disposed between the memory cell area 102 and the peripheral area 104, and a dummy memory cell or a self-correction circuit may be disposed therein. Since these regions and components are not essential to the present invention, they will not be shown or described in detail herein or in the drawings.

After the plan layout of the semiconductor memory device of the present invention is explained, the relative positions and connection relationships of the respective components in the vertical direction of the semiconductor memory device of the present invention will be explained next by using fig. 2 to 5. Referring now to fig. 2 and 3, cross-sectional structures of the periphery region 104 including the bitline contact structures 114 are illustrated, wherein section lines a-a 'of fig. 2 cut through the sacrificial layer 112 along the first direction D1, and section lines B-B' of fig. 3 cut through the spacer structures 108 along the first direction D1.

As shown in fig. 2 and 3, in the peripheral region 104, the bit line structure BL is an extended device isolation layer disposed on the device isolation layer 118, i.e., the device isolation layer isolating the active region ACT in the memory cell region 102. An insulating interlayer 120 is further disposed between the bit line structure BL and the device isolation layer 118. In the embodiment of the invention, each bit line structure BL may sequentially include a polysilicon layer 122, a silicide layer 124, a metal layer 126 and a hard mask layer 128 stacked from bottom to top. Preferably, the material of the polysilicon layer 122 may be doped polysilicon, the material of the metal layer 126 may be tungsten, aluminum, titanium or tantalum, and the material of the hard mask layer 128 may be silicon nitride. Spacers 130 are also formed on the sidewalls of the bit line structures BL, and a conformal insulating layer 106 is formed thereon to isolate the bit line structures BL from surrounding devices. The material of the spacer 130 may be, for example, silicon oxide. The material of the insulating layer 106 is etch selective with respect to both the spacer 130 and the insulating interlayer 120, such as a silicon nitride layer and/or a silicon oxynitride layer.

Referring to fig. 2 and fig. 3 again, depending on the location, a sacrificial layer 112 or a spacer structure 108 is formed between the bit line structure BL and the bit line structure BL in the peripheral region 104, wherein top surfaces of the sacrificial layer 112 and the spacer structure 108 are flush with a top surface of the bit line structure BL. In the fabrication process, the bit line structure BL and the bit line structure BL are first filled with the sacrificial layer 112, and the sacrificial layer 112 may be formed by using a spin-on hard mask (S0H) material, such as S0H silicon oxide. Thereafter, the spacer structure 108 is formed by patterning the spacer structure 108 through a photolithography process and filling the spacer structure with a spacer material. The spacer structure 108 may be formed of an insulating material having an etch selectivity with respect to the sacrificial layer 112. For example, the spacer structures 127 may be formed of silicon nitride. A cap insulating layer 132 is then formed over the bit line structure BL, the spacer structure 108 and the sacrificial layer 112.

Finally, a bit line contact structure 114 is formed directly above and in contact with the bit line structure BL. In the embodiment of the invention, the bit line contact structure 114 is divided into an upper portion 114a with a larger planar area and a lower portion 114b with a smaller planar area, wherein the upper portion 114a is formed in the insulating cover layer 132, the lower portion 114b is formed at the position of the hard mask layer 128 of the original bit line structure BL, the center lines of the upper portion 114a and the lower portion 114b are aligned, and the left and right portions thereof are symmetrical. In actual manufacturing, a photolithography process is performed to define a pattern of the bit line contact structure 114 in the upper portion 114a of the cover insulating layer 132, the non-conductive hard mask layer 128 of the bit line structure BL is removed, and then a deposition process is performed to fill a contact material into the etched space to form the bit line contact structure 114, wherein the bit line contact structure 114 is in direct contact with the metal layer 126 of the bit line structure BL. In the embodiment of the present invention, the design of the different planar areas of the upper and lower halves of the bit line contact structure 114 can increase the contact area and the process margin when the bit line structure BL is connected to the upper external conductive line 116.

In other embodiments, as shown in fig. 6, the center lines C1 and C2 of the upper half 114a and the lower half 114b of the bitline contact structure 114 may not be aligned, so that the upper half 114a is horizontally offset from the bitline structure BL with respect to the lower half 114b, resulting in asymmetry of the left and right halves of the bitline contact structure 114. Such a phenomenon may be caused by a pattern shift of the bit line contact structure 114 during its patterning by a photolithography process. However, since the upper portion 114a of the bit line contact structure 114 is designed to have a larger planar area, it is able to effectively increase the process margin for its fabrication, overcoming such offset problem.

Referring now to fig. 4 and 5, cross-sectional structures of the memory cell region 102 are illustrated, wherein a section line C-C 'of fig. 4 cuts through the storage node contact structure 110 along the first direction D1, and a section line D-D' of fig. 5 cuts through the spacer structure 108 along the first direction D1.

As shown in fig. 4 and 5, in the memory cell region 102, the substrate is composed of an active region ACT and a device isolation layer 118 for isolating the active regions ACT, unlike the peripheral region 104. A portion of the active region ACT and the device isolation layer 118 are patterned by a photolithography process to form word line trenches 2 along the second direction D, and the word line trenches are filled with a conductive material to form a word line structure WL. The material of the word line structure WL may be a metal, such as tungsten, aluminum, titanium, and/or tantalum. The remaining trench space on the word line structure WL is filled with a gate hard mask layer 138, such as a silicon nitride layer. A gate insulating layer 140 is formed between the word line structure WL and the active region ACT below the word line structure WL to isolate the word line structure WL from the active region ACT.

Refer back to fig. 4 and 5. A first doped region 1a and a second doped region 1b may be formed in the active region ACT, respectively at both sides of the word line structure WL and at the center and both ends of the active region ACT (see fig. 1). The first and second doped regions 1a and 1b may be formed through an ion implantation process and may include a dopant of a conductivity type opposite to that of the active region ACT. The bottom surfaces of the first and second doping regions 1a and 1b may be positioned at a predetermined depth downward from the top surface of the active region ACT. In addition, an insulating interlayer 120 may be formed on the surfaces of the active region ACT and the device isolation layer 118 to isolate the active region ACT below from the components above. The insulating interlayer 120 may be formed of a single insulating layer or a plurality of insulating layers, such as a silicon nitride layer, and/or a silicon oxynitride layer, etc. After the formation of the insulating interlayer 120, the active region ACT and the device isolation layer 118 may be patterned again through a photolithography process to form a recess region 134 exposing the first doping region 1a, which corresponds to a central portion of the active region ACT. The bottom surface of the recess region 134 may be higher than the bottom surface of the first doping region 1a (as indicated by the dotted line). A polysilicon layer 122 of a portion of the bit line structure BL is formed in the recess 134 as a bit line contact directly contacting the first impurity region 1 a. In addition, the minimum width of the recess region 134 may be greater than the width of each bit line structure BL. The polysilicon layer 122 of the bit line structure BL may be separated from the adjacent storage node contact structure 110 by a bit line contact spacer 136. The bit line contact spacer 136 may be formed of an insulating material having an etch selectivity with respect to the insulating interlayer 107, for example, the bit line contact spacer 121 may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.

Refer back to fig. 4 and 5. Like the peripheral region 104, a spacer structure 108 is formed between the bit line structures BL in the memory cell region 102. Unlike the peripheral region 104, in the memory cell region 102, the space defined by the spacer structure 108 and the bit line structure BL is used to form storage node contact structures 110, which are formed by removing the sacrificial layer 112 and filling the sacrificial layer with a conductive material, each storage node contact structure 110 corresponds to the second doped region 1b of the active region ACT, and in order to make contact with the two, the insulating interlayer 120 between the two is removed by an etching process, so that a portion of the active region ACT and the device isolation layer 118 is removed, and a portion of the storage node contact structure 110 extends into the substrate. The storage node contacts 110 may be formed from a number of components including, for example, doped semiconductor materials (e.g., doped silicon), metals (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), and/or metal-semiconductor alloys (e.g., metal silicides). In some other embodiments, the storage node contacts 110 may include, in order from bottom to top, a polysilicon layer, a metal silicide layer, and a landing pad, on which respective corresponding capacitors are also connected as a storage node. Since the above-mentioned portions are not the main points of the present invention, the detailed descriptions of these portions will be omitted herein in order to avoid obscuring the focus of the present invention.

Reference is made back to fig. 1. In the embodiment of the present invention, the semiconductor memory device located at the boundary between the memory cell region 102 and the peripheral region 104 has a different structure and connection relationship than a normal semiconductor memory device. For such a semiconductor memory device, the active region ACT may pass only one word line WL instead of two. Furthermore, in some embodiments, referring to fig. 7, for the doped region of such a semiconductor memory device, the second doped region 1b beside the word line WL is connected to a storage node contact structure 110, as shown by the circle F in fig. 1. As for the other end of the active region ACT, since there is no word line WL, it has only a first doped region 1a, and crosses the memory cell region 102 and the peripheral region 104, and its portion located in the peripheral region 104 is connected to the sacrificial layer 112 that is not replaced by the storage node contact structure 110, as shown by the circle G in fig. 1, which is different from the arrangement that all the second doped regions 1b in the memory cell region 102 are connected to the storage node contact structure 110. In other embodiments, as shown in fig. 8, the active region ACT may be formed entirely in the peripheral region 104, but the connection structure is different from that of the active region ACT in the memory cell region 102. Both of the second doping regions 1b of the active region ACT entirely in the peripheral region 104 are connected up to the sacrificial layer 112 without being connected to any storage node contact structure 110.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (16)

1. A semiconductor memory device, comprising:

a semiconductor substrate having a memory cell region and a peripheral region around the memory cell region;

a word line structure located in the semiconductor substrate and extending through the memory cells in a first direction;

a bit line structure located above the semiconductor substrate and extending through the memory cell region and the peripheral region in a second direction;

spacer structures located between the bitline structures and above the wordline structures;

a storage node contact structure located in a space defined by the spacer structure and the bit line structure in the memory cell region and connected to the semiconductor substrate; and

and the sacrificial layer is positioned in a space defined by the spacer structure and the bit line structure in the peripheral area.

2. The semiconductor memory device according to claim 1, wherein a portion of the bit line structure in the peripheral region is located on a device isolation layer.

3. The semiconductor memory device according to claim 2, further comprising an insulating interlayer between the bit line structure and the device isolation layer.

4. The semiconductor memory device of claim 1, wherein said bitline structures extend from said peripheral region on one side of said memory cell region through said memory cell region to said peripheral region on the other side of said memory cell region, and further comprising bitline contact structures located on said peripheral region on both sides of said memory cell region and connected in an alternating manner on said bitline structures on both sides of said peripheral region.

5. The semiconductor memory device of claim 4, wherein the bit line contact structure is in direct contact with a metal layer of the bit line structure.

6. The semiconductor memory device according to claim 4, wherein the bit line contact structure has a long side, the long side being parallel to an extending direction of the bit line structure.

7. The semiconductor memory device according to claim 4, wherein a long side of the bit line contact structure is longer than the spacer structure and the sacrificial layer.

8. The semiconductor memory device of claim 4, further comprising a cap insulating layer on the bit line structures, the spacer structures, and the sacrificial layer, and the bit line contact structures are in the cap insulating layer.

9. The semiconductor memory device of claim 1, wherein the spacer structure and the sacrificial layer are both dielectric insulating materials and are different materials.

10. A semiconductor memory device, comprising:

a semiconductor substrate;

the bit line structure is positioned on a device isolation layer of the peripheral area of the semiconductor substrate;

spacer structures on the device isolation layers and between the bit line structures;

a sacrificial layer on the device isolation layer and between the bit line structures; and

bit line contact structures located right above the bit line structures, wherein each bit line contact structure is connected to one of the bit line structures in an alternating manner, wherein the bit line contact structures comprise an upper half portion and a lower half portion, and a middle line of the upper half portion is aligned with or not aligned with a middle line of the lower half portion.

11. The semiconductor memory device of claim 10, further comprising a blanket insulating layer over said bitline structures, said spacer structures, and said sacrificial layer, wherein said upper half of said bitline contact structures are located in said blanket insulating layer and said lower half of said bitline contact structures are located between said spacer structures and between said sacrificial layer.

12. The semiconductor memory device of claim 10, further comprising an insulating interlayer between the bitline structure, the spacer structure, and the sacrificial layer and the device isolation layer.

13. The semiconductor memory device of claim 10, wherein the spacer structure and the sacrificial layer are both dielectric insulating materials and are different materials.

14. A semiconductor memory device, comprising:

the semiconductor substrate is provided with a device isolation layer for defining an active region, wherein the active region comprises a first doping region positioned in the middle of the active region and two second doping regions respectively positioned at two ends of the active region; and

a word line embedded in the semiconductor substrate and passing through the active region between the first doped region and the second doped region;

at least one second doping region is upwards connected to the sacrificial layer between the bit line structures of the peripheral region of the semiconductor substrate.

15. The semiconductor memory device of claim 14, wherein one of said second doped regions beside said word line is connected up to a storage node contact structure, and the other of said second doped regions is connected up to said sacrificial layer.

16. The semiconductor memory device according to claim 14, wherein both of the second doped regions are connected up to the sacrificial layer.

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