CN111708238A

CN111708238A - Array substrate and display panel

Info

Publication number: CN111708238A
Application number: CN202010622466.0A
Authority: CN
Inventors: 金慧俊; 简守甫; 秦丹丹; 王听海
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-09-25
Anticipated expiration: 2040-06-30
Also published as: CN111708238B

Abstract

The embodiment of the invention discloses an array substrate and a display panel comprising the same, wherein the array substrate comprises a display area and a non-display area surrounding the display area, and a first pin, a second pin and a third pin are arranged on one non-display side; the second pins are arranged on two sides of the first pins, and the first pins and the second pins are arranged opposite to the third pins; wherein, in the second direction, the distance between two nonadjacent pins in the plurality of first pins and any one third pin in the plurality of third pins is less than the distance between at least one first pin positioned between the two nonadjacent first pins and any one third pin in the plurality of third pins; in the second direction, at least two second pins exist, wherein the distance between the second pin close to the first pin and any one of the third pins is smaller than the distance between the second pin far from the first pin and any one of the third pins.

Description

Array substrate and display panel

Technical Field

The invention relates to the field of display, in particular to an array substrate and a display panel comprising the same.

Background

With the continuous development of the display market, the visual effect of the display screen is more and more strictly required by consumers, so that the requirements on the appearance design of the display screen are diversified, and the requirements on the screen occupation ratio are higher and higher. The trend of the comprehensive screen technology is to pursue a screen proportion of more than or equal to 90% through the design of an ultra-narrow frame or even no frame, and under the condition that the total area of the machine body is not changed, the display area is maximized, and the visual effect is more brilliant.

The method that the integrated circuit Chip is bound On the Glass (COG, Chip On Glass) is a technology that is used more in the current display module, but the method that the integrated circuit Chip (IC) is directly bound and attached to the Glass of the display panel occupies the area of the non-display area of the screen of the display panel, and is not beneficial to further realizing the narrow-frame full-screen design of the liquid crystal display panel.

Disclosure of Invention

In view of the foregoing, the present invention provides an array substrate and a display panel.

An embodiment of the present invention provides an array substrate, including: the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; two adjacent scanning lines and two adjacent data lines are intersected to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array; a non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, the first non-display area and the second non-display area are arranged oppositely, and the third non-display area and the fourth non-display area are arranged oppositely; the third non-display area and the fourth non-display area are provided with a grid driving circuit, and the grid driving circuit comprises a plurality of driving signal lines; the first non-display area comprises an IC setting area and an FPC setting area; the IC setting area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal wires; the plurality of first pins and the plurality of third pins are arranged oppositely; in the second direction, a distance between two nonadjacent first pins in the plurality of first pins and any one third pin in the plurality of third pins is smaller than a distance between at least one first pin located between the two nonadjacent first pins and any one third pin in the plurality of third pins; the plurality of second pins are located on two sides of the plurality of first pins, and at least two second pins exist in the second direction, wherein the distance between the second pin close to the first pin and any one of the plurality of third pins is smaller than the distance between the second pin far from the first pin and any one of the plurality of third pins.

The embodiment of the invention provides a display panel, which can comprise the array substrate.

According to the array substrate and the display panel provided by the embodiment of the invention, under the condition that the first pin, the second pin and the third pin are arranged, the first pin and the third pin can be arranged closer to the display area on the premise that the display performance is ensured, namely the first safety distance, the second safety distance and the third safety distance are ensured, that is, compared with the prior art, the width of the first non-display area in the second direction can be reduced, the display area occupation ratio can be further improved, and the display effect is improved.

Drawings

Fig. 1 is a schematic top view of an array substrate in the prior art;

FIG. 2 is a schematic diagram of a top view of an IC corresponding to the IC of FIG. 1;

FIG. 3 is an enlarged schematic view of the first non-display area in FIG. 1;

FIG. 4 is a schematic diagram of another top view of an IC corresponding to the IC of FIG. 1;

FIG. 5 is a schematic view of another enlarged structure of the first non-display area in FIG. 1;

fig. 6 is a schematic top view illustrating an array substrate according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a top view structure of an IC disposed corresponding to that in fig. 6 according to an embodiment of the present invention;

FIG. 8 is an enlarged view of the first non-display area of FIG. 6;

FIG. 9 is a schematic view of another enlarged structure of the first non-display area in FIG. 6;

FIG. 10 is a schematic view of another enlarged structure of the first non-display area in FIG. 6;

fig. 11 is another enlarged schematic view of the first non-display area in fig. 6.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples.

It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

To better understand the idea of the present invention, first, a prior art is introduced, and please refer to fig. 1 to fig. 3, which are an array substrate and a related structure in the prior art, specifically, fig. 1 is a schematic top view structure of an array substrate in the prior art, fig. 2 is a schematic top view structure of an IC (integrated circuit) disposed corresponding to fig. 1, and fig. 3 is an enlarged schematic structural diagram of a first non-display area in fig. 1.

Referring to fig. 1 to 3 in combination, in the prior art, the array substrate includes a display area 230', in which a plurality of scan lines extending along a first direction (horizontal direction shown in the figure) and a plurality of data lines extending along a second direction (vertical direction shown in the figure) are disposed, and two adjacent scan lines and two adjacent data lines intersect to form a pixel area; in each pixel region, a driving transistor and the like are further included to drive each pixel for light-emitting display. All the pixel areas of the display area are arranged in an array.

In the prior art, the array substrate further includes a non-display region 240 ' surrounding the display region 230 ', wherein the non-display region 240 ' includes a first non-display region 241 ', a second non-display region 242 ', a third non-display region 243 ' and a fourth non-display region 244 '. Wherein the first non-display region 241 'and the second non-display region 242' are oppositely disposed, and the third non-display region 243 'and the fourth non-display region 244' are oppositely disposed. In the prior art shown in fig. 1, the first non-display region 241 'is generally referred to as a step region because the first non-display region 241' is generally not covered by the opposite substrate and forms a step-like shape after the array substrate is attached to the opposite substrate, and is generally referred to as a "step region". The step region, that is, the first non-display region 241', is generally provided with a display chip for driving, and is generally provided with a Flexible Printed Circuit (FPC) connected to a main board or the like. Referring to fig. 1, in the related art, an IC setting region 200 ' and an FPC setting region 220 ' are provided in a first non-display region 241 ', a plurality of pins for connection with an IC are provided in the IC setting region 200 ', and a plurality of pins for connection with an FPC are provided in the FPC setting region 220 '. In the third non-display region 243 ' and the fourth non-display region 244 ', a gate driving circuit that drives the scan lines in the display region 230 ' to operate is generally disposed, and the gate driving circuit generally includes a plurality of driving signal lines, such as a clock signal line, a high-low level signal line, a start control line, a reset control line, and the like.

Referring to fig. 2, in the prior art, an IC is generally provided with pins at two sides thereof, for example, a data line driving output pin 102' at an upper side thereof as shown in the figure, for outputting a driving signal to a data line after being electrically connected to a first pin of a corresponding driving data line on an array substrate. Since there are many data lines on the array substrate, the data line driving output pins 102' usually occupy one side of the whole IC and are arranged in multiple rows on the IC. On the lower side of the illustrated IC, an IC drive input pin 106' is provided for electrical connection with a third pin on the array substrate, and a drive signal is input to the IC. Because the number of the driving input pins 106 ' is small, the driving signal output pins 104 ' are further disposed on two sides of the driving input pins 106 ' for electrically connecting with the second pins of the array substrate and transmitting driving signals to the driving signal lines.

Referring to fig. 3, in the prior art, corresponding to pins on an IC, in a first non-display area of an array substrate, a first pin 202 ', a second pin 204 ', and a third pin 206 ' are disposed, where positions of the first pin 202 ', the second pin 204 ', and the third pin 206 ' correspond to positions of a data line driving output pin 102 ', a driving signal output pin 104 ', and an IC driving input pin 106 ' of the IC in fig. 2. That is, the first pin 202 ' is disposed opposite to the third pin 206 ', and the second pin 204 ' is disposed at two sides of the third pin 206 ' and opposite to the first pin 202 '. The first pin 202 ', the second pin 204', and the third pin 206 'are all located in the IC arrangement area 200'.

Referring to fig. 3, in the prior art, the first pins 202 'are electrically connected to the data lines 210', that is, each of the first pins 202 'is electrically connected to one of the data lines 210'. Since the display area is located above the IC layout area 200 'and the width of the display area in the first direction (horizontal direction) is much larger than the width of the IC in the first direction, a fan-shaped area, called "fan-out area", is formed by the leads connecting the first leads 202' and the data lines 210 'in the process of extending from the first leads 202' to the display area. To ensure a good connection of the IC, there will be a third safety distance DC between the slope of the fan-out area and the first pin 202'.

Referring to fig. 3, in the prior art, the second lead 204 'is electrically connected to the driving signal line 212', and the driving signal line 212 'extends from the IC layout area 200' to the third non-display area and the fourth non-display area. As shown in the figure, the driving signal line 212 'extends downward from the second pin 204' and then bends upward, that is, the driving signal line 212 'is led out from the second pin 204' in a direction away from the display area 230 'and then bends and extends in a direction close to the display area 230'. The third pin 206 'is electrically connected with the fourth pin 226' through a signal line, the fifth pin 224 'is arranged on two sides of the fourth pin 226', and the fourth pin 226 'and the fifth pin 224' are arranged in the FPC arrangement area for electrically connecting with the FPC.

In the prior art, in order to ensure the transmission of each signal and the performance of each component, a second safety distance DB needs to be ensured between the first pin 202 'and the third pin 206'. In the process that the driving signal line is led out far away from the display area 230 ', a first safety distance DA is required to be ensured between the driving signal line and the fourth pin 226 ' and the fifth pin 224 '.

Due to the existence of the first safety distance DA, the second safety distance DB, and the third safety distance DC, the width of the first non-display area 241' in the second direction (the vertical direction in the figure) is inevitably too wide, which is not favorable for narrowing the frame, providing a screen occupation ratio, and improving the display effect.

Therefore, in the prior art, researchers have proposed another array substrate, please refer to fig. 1, fig. 4 and fig. 5, in which fig. 4 is another schematic top view structure of an Integrated Circuit (IC) disposed corresponding to fig. 1, and fig. 5 is another schematic enlarged structure of the first non-display area in fig. 1.

Referring to fig. 4, in the prior art, a data line driving output pin 102' is disposed on an upper side of the figure for outputting a driving signal to a data line after being electrically connected to a first pin of a corresponding driving data line on an array substrate. On the lower side of the illustrated IC, an IC drive input pin 106' is provided for electrical connection with a third pin on the array substrate, and a drive signal is input to the IC. And driving signal output pins 104 'are further arranged on two sides of the data line driving output pin 102' and are used for being electrically connected with the second pins of the array substrate and transmitting driving signals to the driving signal lines.

Referring to fig. 5, in the prior art, corresponding to pins on an IC, in a first non-display area of an array substrate, a first pin 202 ', a second pin 204 ', and a third pin 206 ' are disposed, where positions of the first pin 202 ', the second pin 204 ', and the third pin 206 ' correspond to positions of a data line driving output pin 102 ', a driving signal output pin 104 ', and an IC driving input pin 106 ' of the IC in fig. 4. That is, the first pin 202 ' is disposed opposite to the third pin 206 ', and the second pin 204 ' is disposed at two sides of the first pin 202 ' and opposite to the third pin 206 '. The first pin 202 ', the second pin 204', and the third pin 206 'are all located in the IC arrangement area 200'.

Referring to fig. 5, in the prior art, the first pins 202 'are electrically connected to the data lines 210', that is, each of the first pins 202 'is electrically connected to one of the data lines 210'. Since the display area is located above the IC layout area 200 'and the width of the display area in the first direction (horizontal direction) is much larger than the width of the IC in the first direction, a fan-shaped area, called "fan-out area", is formed by the leads connecting the first leads 202' and the data lines 210 'in the process of extending from the first leads 202' to the display area.

Referring to fig. 5, in the prior art, the second lead 204 'is electrically connected to the driving signal line 212', and the driving signal line 212 'extends from the IC layout area 200' to the third non-display area and the fourth non-display area. As shown in the figure, the driving signal line 212 'extends upward from the second pin 204', and the driving signal line 212 'is led out from the second pin 204' to a direction close to the display area 230 'and extends to a direction close to the display area 230'. That is, in the prior art, the driving signal line 212 'is located at both sides of the data line and also includes the fan-out area, and at this time, in order to ensure good connection of the IC, there is a third safety distance DC between the oblique line of the fan-out area and the first pin 202'. The third safety distance DC is determined by a diagonal line closest to the edge, i.e. by a drive signal line closest to the edge.

The third pin 206 'is electrically connected with the fourth pin 226' through a signal line, the fifth pin 224 'is arranged on two sides of the fourth pin 226', and the fourth pin 226 'and the fifth pin 224' are arranged in the FPC arrangement area for electrically connecting with the FPC.

In the prior art, in order to ensure the transmission of each signal and the performance of each component, a second safety distance DB needs to be ensured between the first pin 202 'and the third pin 206'.

In the prior art shown in fig. 4 and 5, the first safety distance DA is determined by the distance between the third pin 206 ' and the fourth pin 226 ' and the fifth pin 224 '. At this time, the distances between the third and fourth leads 206 ', 226' and 224 'in fig. 5 have been greatly reduced compared to the related art of fig. 3, and the width of the first non-display region 241' in the second direction (the vertical direction is illustrated) can be greatly improved. However, since the driving signal line 212 'is disposed close to the data line 210', electrostatic discharge is easily caused, and finally display defects are caused.

In order to improve display ratio and display effect, an embodiment of the present invention provides an array substrate, including: the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; two adjacent scanning lines and two adjacent data lines are intersected to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array; a non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, the first non-display area and the second non-display area are oppositely arranged, and the third non-display area and the fourth non-display area are oppositely arranged; the third non-display area and the fourth non-display area are provided with a grid driving circuit, and the grid driving circuit comprises a plurality of driving signal lines; the first non-display area comprises an IC setting area and an FPC setting area; the IC setting area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal wires; the plurality of first pins and the plurality of third pins are arranged oppositely; in the second direction, a distance between two nonadjacent first pins in the plurality of first pins and any one third pin in the plurality of third pins is smaller than a distance between at least one first pin located between the two nonadjacent first pins and any one third pin in the plurality of third pins; the plurality of second pins are located on two sides of the plurality of first pins, and at least two second pins exist in the second direction, wherein the distance between the second pin close to the first pin and any one of the plurality of third pins is smaller than the distance between the second pin far from the first pin and any one of the plurality of third pins.

The following detailed description will be made in conjunction with the accompanying drawings. Referring to fig. 6 to 8, fig. 6 is a schematic top view structure diagram of an array substrate according to an embodiment of the present invention, fig. 7 is a schematic top view structure diagram of an IC disposed corresponding to fig. 6 according to an embodiment of the present invention, and fig. 8 is an enlarged structure diagram of a first non-display area in fig. 6.

In this embodiment, the array substrate includes a display area 230, wherein a plurality of scan lines extending along a first direction (shown in the figure horizontal direction) and a plurality of data lines extending along a second direction (shown in the figure vertical direction) are disposed in the display area 230, and two adjacent scan lines and two adjacent data lines intersect to form a pixel area; in each pixel region, a driving transistor and the like are further included to drive each pixel for light-emitting display. All the pixel areas of the display area are arranged in an array.

Referring to fig. 6, the array substrate according to the embodiment of the present invention includes a display region 230 and a non-display region 240 surrounding the display region 230, wherein the non-display region 240 includes a first non-display region 241, a second non-display region 242, a third non-display region 243 and a fourth non-display region 244. Wherein the first non-display area 241 and the second non-display area 242 are oppositely disposed, and the third non-display area 243 and the fourth non-display area 244' are oppositely disposed. Similar to the prior art shown in fig. 1, in the present embodiment, in the first non-display region 241, an IC setting region 200 and an FPC setting region 220 are provided, a plurality of pins for connection with an IC are provided on the IC setting region 200, and a plurality of pins for connection with an FPC are provided on the FPC setting region 220. In the third non-display region 243 and the fourth non-display region 244, a gate driving circuit that drives the scan lines in the display region 230 to operate is provided, and the gate driving circuit generally includes a plurality of driving signal lines, such as a clock signal line, a high-low level signal line, a start control line, a reset control line, and the like.

Referring to fig. 7, in the present embodiment, the IC10 has pins on both sides thereof, for example, a data line driving output pin 102 is disposed on the upper side of the figure, and is used for outputting a driving signal to the data line after being electrically connected to the first pin of the corresponding driving data line on the array substrate. As the array substrate is provided with a plurality of data lines. An IC drive input pin 106 is provided on the lower side of the illustrated IC, and is electrically connected to a third pin on the array substrate to input a drive signal to the IC. And driving signal output pins 104 are further arranged on two sides of the data line driving output pin 102, and are used for being electrically connected with the second pins of the array substrate and transmitting driving signals to the driving signal lines. In this embodiment, the distance between two non-adjacent data line driving output pins 102 and any one IC driving input pin 106 of the plurality of second IC driving input pins 106 in the second direction (vertical direction shown in the figure) is smaller than the distance between at least one data line driving output pin 102 located between the two non-adjacent data line driving output pins 102 and any one IC driving input pin 106 of the plurality of IC driving input pins 106. That is, in the IC10 corresponding to the array substrate provided in the present embodiment, the data line driving output pins 102, which are located at two sides, are closer to the IC driving input pin 106 than the pins located at the middle.

In the present embodiment, the data line driving output pins 102 are divided into a first group and a second group with the symmetry center of the IC10 along the second direction (the vertical direction is shown), wherein the first group includes all the data line driving output pins 102 located on one side of the symmetry center of the IC10, and the second group includes all the data line driving output pins 102 located on the other side of the symmetry center of the IC 10. In the first group/the second group, the data line driving output pin 102 is shifted away from the display area as it is farther from the center of symmetry of the IC, that is, shifted closer to the IC driving input pin 106 as it is farther from the center of symmetry of the IC. In some other embodiments of the present invention, the data line driving output pins 102 further include a third group, the third group is located between the first group of data line driving output pins 102 and the second group of data line driving output pins 102, and the distance between the third group of data line driving output pins 102 and the IC driving input pin 106 is equal to and greater than the distance between the first group/second group of data line driving output pins 102 and the IC driving input pin 106 compared with the first group of data line driving output pins 102 and the second group of data line driving output pins 102.

In this embodiment, the plurality of driving signal output pins 104 are located at two sides of the plurality of data line driving output pins 102, and in the second direction (vertical direction shown in the figure), at least two driving signal output pins 104 exist, wherein the distance between the driving signal output pin 104 close to the data line driving output pin 102 and any one of the plurality of IC driving input pins 106 is smaller than the distance between the driving signal output pin 104 far from the data line driving output pin 102 and any one of the plurality of IC driving input pins 106. That is, in the present embodiment, the driving signal output pin 104 located outside the data line driving output pin 102 is shifted to the display area, that is, to the direction away from the IC driving input pin 106, the farther away from the data line driving output pin 102. In this embodiment, the driving signal output pins 104 located at two sides of the data line driving output pin 102 are divided into a fourth group and a fifth group, and in the fourth/fifth group of driving signal output pins 104, as they are far from the symmetry center of the IC, they are shifted toward a direction close to the display area, that is, as they are far from the symmetry center of the IC, they are shifted toward a direction far from the IC driving input pin 106.

Referring to fig. 8, in the present embodiment, corresponding to pins on an IC, a first pin 202, a second pin 204, and a third pin 206 are disposed in a first non-display area of an array substrate, where positions of the first pin 202, the second pin 204, and the third pin 206 correspond to positions of a data line driving output pin 102, a driving signal output pin 104, and an IC driving input pin 106 of the IC in fig. 7. That is, the first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed at two sides of the first pin 202 and opposite to the third pin 206. The first pin 202, the second pin 204 and the third pin 206 are all located in the IC layout area 200.

Referring to fig. 8, in the present embodiment, the first pins 202 are electrically connected to the data lines 210, that is, each of the first pins 202 is electrically connected to one of the data lines 210. Since the display area is located above the IC layout area 200 and the width of the display area in the first direction Dx is much larger than the width of the IC in the first direction Dx, a sector area, called "fan-out area", is formed by the leads connecting the first leads 202 and the data lines 210 in the process of extending from the first leads 202 to the display area. That is, the first non-display area includes a plurality of data leads, and both ends of the plurality of data leads are electrically connected with the plurality of data lines and the plurality of first leads, respectively; at least one of the plurality of data wirings includes an inclined section extending in a direction crossing both the first direction Dx and the second direction Dy. Generally, the fan-out area will contain many parallel arranged oblique lines, and the area closest to the edge will have longer oblique lines. To ensure a good connection of the IC, there will be a third safety distance DC between the slope of the fan-out area and the first pin 202.

In this embodiment, two non-adjacent first pins 202 exist, and in the second direction Dy, a distance between any one of the plurality of third pins 206 and at least one first pin 202 located between the two non-adjacent first pins 202 is smaller than a distance between any one of the plurality of third pins 206 and at least one first pin 202 located between the two non-adjacent first pins 202. That is, in the array substrate provided in the present embodiment, the first pins 202, which are located at two sides, are closer to the third pins 206 than the pins located at the middle.

In this embodiment, the first leads 202 are divided into a first group and a second group by a symmetry center of the array substrate along the second direction Dy, where the first group includes all the first leads 202 located on one side of the symmetry center of the array substrate, and the second group includes all the first leads 202 located on the other side of the symmetry center of the array substrate. In the first group/the second group, the first leads 202 are shifted toward the direction away from the display area as they are away from the symmetry center of the array substrate, that is, shifted toward the third leads 206 as they are away from the symmetry center of the array substrate. In some other embodiments of the present invention, the first pins 202 further include a third group of first pins, the third group of first pins being located between the first group of first pins and the second group of first pins, and the distance between the third group of first pins 202 and the third pins 206 is equal everywhere and greater than the distance between the first group/second group of first pins 202 and the third pins 206 compared to the first group of first pins 202 and the second group of first pins 202. In some other embodiments of the present invention, the first pins may include a plurality of sets of first and second groups of first pins, and when the array substrate is provided with a plurality of IC arrangement regions, there may be a set of first pins corresponding to each IC arrangement region, where the set of first pins includes a first group of first pins and a second group of second pins, and the set of first pins is centered on a symmetry center of the set of first pins, and the farther away from the symmetry center, the farther away from the display region the pins are. Furthermore, each set of first pins comprises a third set of first pins positioned between the first set of first pins and the second set of first pins, in addition to the first set of first pins and the second set of first pins.

In this embodiment, the plurality of second pins 204 are located at two sides of the plurality of first pins 202, and in the second direction Dy, at least two second pins 204 exist, wherein a distance between the second pin 204 close to the first pin 202 and any one of the plurality of third pins 206 is smaller than a distance between the second pin 204 far from the first pin 202 and any one of the plurality of third pins 206. That is, in the present embodiment, the second pin 204 located outside the first pin 202 is offset to the display area, i.e. offset to the direction away from the third pin 206, the farther away from the first pin 202. In this embodiment, the second pins 204 located at two sides of the first pin 202 are divided into a fourth group and a fifth group, and in the fourth/fifth group of the second pins 204, as they are far from the symmetry center of the array substrate, they are shifted toward the direction close to the display area, that is, as they are far from the symmetry center of the array substrate, they are shifted toward the direction far from the third pin 206. In some other embodiments of the present invention, when the array substrate includes a plurality of sets of first pins, the second pins are located on both sides of all the first pins.

In the present embodiment, as shown in fig. 8, in the second direction Dy, the leading direction of the first pin 202 and the data line 210 is the upward direction, and the leading direction of the second pin 204 and the driving signal line 212 is the downward direction, that is, the leading direction of the first pin 202 electrically connected to the plurality of data lines 210 is opposite to the leading direction of the plurality of second pins 204 electrically connected to the plurality of driving signal lines 212. Since the drawing direction of the driving signal line 212 is opposite to the drawing direction of the data line in the present embodiment, the third safety distance DC between the slope of the fan-out area and the first pin 202 is limited only by the slope of the data lead electrically connected to the data line, and is not limited by the driving signal line in the present embodiment. Due to the widths of the display area and the IC setting area of the array substrate, generally, the straight line region from the first pin to the fan-out area is also in a shape with a wide middle and narrow ends, and the third safety distance DC is the width of the narrower region at the two sides of the straight line region. And the width of the linear region is wider at the middle portion of the lead-out line. In this embodiment, compared with the prior art shown in fig. 3 or fig. 5, the first leads 202 in the middle area of this embodiment are retracted toward the display area. Since the middle portion of the outgoing line has a wider width of the straight line region, the retraction of the first pin 202 does not affect the setting of the third safety distance DC, that is, the retraction of the first pin 202 does not affect the setting of the width from the first pin 202 to the non-display region in the display region.

Further, referring to fig. 8, the leading-out direction of the second leads 204 and the driving signal lines 212 is led out in a direction away from the display area, and then bent to extend in a direction close to the display area, so that, as shown in the figure, the driving signal lines 212 occupy a part of the space in the downward position area of the driving signal lines 212 in the bending process. In the present embodiment, the second lead 204 is more away from the symmetric center of the array substrate along the second direction Dy, and is more shifted toward the display region. Therefore, in the bending process of the lead lines of the driving signal lines 212, the lead lines at the outermost edges may be shifted toward the display region. Therefore, the space occupied by all the lead lines of the driving signal lines under the second lead is much smaller than the space occupied by the lead lines of the driving signal lines 212 'under the second lead 204' in fig. 3. In addition, in this embodiment, the second pin 204 is close to the cheap position of the display area, and corresponds to the fan-out area of the data line, and this area is the bevel edge area of the fan-shaped outgoing line, and the second pin is also arranged in the direction close to the bevel edge in the upward offset process, so that the occupied position is originally the blank area below the fan-out area, and the layout improvement of other components is not required to be additionally performed.

Further, since the lead lines of the first pin 202 and the data line 210 are drawn in the upward direction in the figure, the lead lines of the second pin 204 and the driving signal line 212 are drawn in the downward direction in the figure. The driving signal line 212 may be bent at a position close to the frame region. In an objective way, the distance between the signal line 210 and the driving signal line 212 is increased, and therefore, the problem that static electricity or parasitic capacitance is easily generated between the data line 210 'and the driving signal line 212' in the prior art as shown in fig. 5 is solved.

With continued reference to fig. 8, in the present embodiment, a third lead 206 is disposed in the IC disposing area at a position opposite to the first lead 202. The third pin 206 is used to electrically connect with a fourth pin 226 of the FPC mounting area to receive a driving signal for driving the IC from the FPC. In this embodiment, the number of the third leads 206 is much smaller than the number of the first leads 202, so that the extension width of the plurality of third leads 206 in the first direction Dx in the IC layout area 200 is much smaller than the extension width of the plurality of first leads 202 in the first direction Dx. In this embodiment, since the plurality of first pins 202 are retracted toward the display area, on the basis of ensuring the second safety distance DB between the first pins 202 and the third pins 206, the second pins 206 of this embodiment may also be closer to the display area than the prior art in fig. 3 or fig. 5. This is because the second safety distance DB is a distance between the closest one of the first pins 202 and the closest one of the third pins 206, in this embodiment, since the extension width of the plurality of third pins 206 in the first direction Dx is much smaller than the extension width of the plurality of first pins 202 in the first direction Dx, and the plurality of first pins are offset toward the display region as they are located at the center of symmetry of the array substrate. Therefore, in the present embodiment, the second safety distance is a distance between the third pin 206 at the two sides and the first pin 202 adjacent thereto in the second direction. Since the plurality of first pins 202 opposite to the third pins 206 are closer to the display area than the plurality of first pins 202 not opposite to the third pins 206, correspondingly, all the third pins are also retracted to the display area by a partial distance compared with the prior art. The first pin 202, which is not opposite to the third pin, is not limited by the second safety distance DB because no other pin is disposed on the opposite side, and may be closer to the edge of the IC disposition region, which is far from the display region, than the first pin opposite to the third pin 206.

Further, referring to fig. 8, in the present embodiment, the FPC mounting area is located on a side of the IC mounting area 200 away from the display area, and a plurality of fourth pins 226 and a plurality of fifth pins 224 are disposed in the FPC mounting area. The fourth pin 226 is disposed opposite to the third pin 206 and is used for providing a driving signal to the third pin 206, and the fourth pin is used for connecting with other pins of the FPC, inputting other signals, and may be electrically connected with some other elements on the array substrate. Between the third pin 206 and the fourth pin 226, a first safety distance DA is ensured.

Through the setting of first pin, second pin and the third pin that this embodiment provided, can guarantee to show the performance, guarantee first safe distance, second safe distance and third safe distance promptly under the prerequisite for first pin 202, third pin 206 are more close to the display area setting, also promptly, compare prior art, can reduce the width of first non-display area 241 on second direction Dy, can further improve the display area and account for than, improve the display effect.

Furthermore, in this embodiment, the first non-display area includes a plurality of data leads, and two ends of the plurality of data leads are electrically connected to the plurality of data lines and the plurality of first leads, respectively; at least one of the plurality of first leads includes an inclined section, and the extending direction of the inclined section intersects with both the first direction and the second direction; the arrangement direction of the second pins of the fourth group or the fifth group and the extension direction of the inclined section form an included angle, and the included angle is greater than or equal to 0 degree and smaller than 45 degrees. Referring to fig. 8, the extending direction of the fourth group of third leads 206 is Do, where the extending direction of the fourth group of third leads 206 is defined as a connecting line of corresponding positions of the plurality of third leads 206, such as the geometric center of the third leads, or the extending direction of a connecting line of vertices corresponding to the edges, and the extending direction of the fourth group of third leads 206 is Do intersecting both the first direction Dx and the second direction Dy. The data lead is a fan-out area part, and the extending direction of the fan-out inclined section is crossed with the first direction Dx and the second direction Dy. In fig. 8, the extending direction of the fourth group of third pins 206 is an angle θ between Do and the extending direction of the inclined segment of the fan-out region, where the angle θ is greater than or equal to 0 ° and less than 45 °. By such an arrangement, the space below the fan-out area can be fully utilized, and the positions of the third pins 206 can be reasonably arranged to provide arrangement space for the outgoing lines of the driving signal lines 212 and the third pins 206.

Further, in the present embodiment, any one of the plurality of first leads 202 and any one of the plurality of second leads 204 are identical in size and shape. Therefore, signals transmitted from the IC to the array substrate can be guaranteed, and the transmission effect is the same. And the plurality of first pins 202 and the plurality of second pins 204 can be uniformly arranged, so that an excessive difference between the routing lines is avoided. In the embodiment, the width of the driving signal line 212 is generally 5 to 10 times as wide as the data line 210 for transmitting the driving signal of the gate driving circuit.

Referring to fig. 9, fig. 9 is another enlarged schematic structural diagram of the first non-display area in fig. 6. In this embodiment, the same structure as that in the embodiment shown in fig. 8 can be referred to the description related to fig. 8, and only the difference will be described in detail. In this embodiment, the distance between any two adjacent first pins is smaller than the distance between two adjacent first pins and the distance between two adjacent second pins. In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204 and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed at two sides of the first pin 202 and opposite to the third pin 206. The first pin 202, the second pin 204 and the third pin 206 are all located in the IC layout area 200.

In this embodiment, the distance between two non-adjacent pins of the plurality of first pins 202 and any one third pin 206 of the plurality of third pins 206 in the second direction (vertical direction shown in the figure) is smaller than the distance between at least one first pin 202 located between the two non-adjacent first pins 202 and any one third pin 206 of the plurality of third pins 206. That is, in the array substrate provided in the present embodiment, the first pins 202, which are located at two sides, are closer to the third pins 206 than the pins located at the middle.

In this embodiment, the plurality of second pins 204 are located on two sides of the plurality of first pins 202, and in the second direction, there are at least two second pins 204, wherein a distance between the second pin 204 close to the first pin 202 and any one of the plurality of third pins 206 is smaller than a distance between the second pin 204 far from the first pin 202 and any one of the plurality of third pins 206. That is, in the present embodiment, the second pin 204 located outside the first pin 202 is offset to the display area, i.e. offset to the direction away from the third pin 206, the farther away from the first pin 202. In this embodiment, the second pins 204 located at two sides of the first pin 202 are divided into a fourth group and a fifth group, and in the fourth/fifth group of the second pins 204, as they are far from the symmetry center of the array substrate, they are shifted toward the direction close to the display area, that is, as they are far from the symmetry center of the array substrate, they are shifted toward the direction far from the third pin 206.

In addition, in the present embodiment, the size and shape of any one of the plurality of first leads 202 is the same as that of any one of the plurality of second leads 204. In comparison with the embodiment of fig. 8, in this embodiment, in the embodiment, the distance between any two adjacent first pins is smaller than the distance between two adjacent first pins and the distance between two adjacent second pins.

In this embodiment, the first pin 202 is used for transmitting a data line driving signal, and the second pin 204 is used for transmitting a driving signal of a gate driving circuit. In general, the driving signal of the gate driving circuit has a voltage greater than that of the data line, so the width of the driving signal line 212 is greater than that of the data line 210. The first pin 202 and the second pin 204 have the same size and shape, and when the pins are the same, the signals transmitted by the pins are different, so that electrostatic discharge or parasitic capacitance is easily generated. Therefore, the distance between the first pin 202 and the second pin should be set to be larger than the distance between any adjacent two first pins 202. More specifically, generally, the width of the driving signal line 212 is 5 to 10 times the width of the data line 210, and therefore, the distance between the adjacent first pins 202 and the adjacent second pins 204 should be 5 to 10 times the distance between the adjacent first pins 202, so as to ensure the safety of the static electricity and the capacitance between the adjacent first pins 202 and the adjacent second pins 204. Furthermore, since the second pins 204 transmit signals higher than the first pins 202, the distance between any adjacent second pins 204 is greater than the distance between any adjacent first pins 202. Therefore, the safety of static electricity and parasitic capacitance between the adjacent second pins 204 is ensured, and the display effect is ensured.

Under the condition that first pin, second pin and the third pin that provides through this embodiment set up, can guarantee to show the performance, guarantee promptly under first safe distance, second safe distance and the prerequisite of third safe distance for first pin 202, third pin 206 are more close to the display area and set up, promptly, compare prior art, can reduce the width of first non-display area 241 on second direction Dy, can further improve the display area and account for the ratio, improve the display effect.

Referring to fig. 10, fig. 10 is a schematic view of another enlarged structure of the first non-display area in fig. 6. In this embodiment, the same structure as that in the embodiment shown in fig. 8 can be referred to the description related to fig. 8, and only the difference will be described in detail. In addition, in order to more clearly illustrate the relationship of the first pin, the second pin, and the third pin, in fig. 10, elements such as a data line, a driving signal line, and the like are omitted, and only the first pin, the second pin, and the third pin are shown. In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204 and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed at two sides of the first pin 202 and opposite to the third pin 206. The first pin 202, the second pin 204 and the third pin 206 are all located in the IC layout area 200.

Further, in the present embodiment, the boundary of one second lead 204 closest to the plurality of first leads 202 in the second direction does not exceed the boundaries of the two closest first leads in the second direction. Please continue to refer to fig. 10. In this embodiment, the first pins 202 are arranged in two rows, and the second pins 204 are arranged in one row. The boundaries in the second direction (the illustrated vertical direction) of the two closest first pins are indicated by the illustrated dashed lines, the two boundaries being defined by the upper boundary of the first pin 202 near the display area and the lower boundary of the first pin 202 of the principle display area, of the two first pins 202. In this embodiment, the upper boundary of the second pin 204 closest to the first pin 202 does not exceed the upper boundary of the first pin 202 closest to the second pin 204 in the row of the first pins 202 closest to the display area, and the lower boundary of the second pin 204 does not exceed the lower boundary of the first pin 202 closest to the second pin 204 in the row of the first pins 202 farthest from the display area. In some other embodiments of the present invention, the plurality of first pins may be arranged in a plurality of rows, and the plurality of second pins may be arranged in a plurality of rows, where the number of rows of the first pins is greater than the number of rows of the first pins. When the first pins and the second pins comprise a plurality of rows, the upper boundary of one second pin, closest to the first pins, of the row in the display area in the second pins does not exceed the upper boundary of one first pin, closest to the second pins, of the row in the display area in the first pins; the lower boundary of one second pin which is farthest from one row in the display area and is closest to the first pin does not exceed the lower boundary of one first pin which is farthest from one row in the display area and is closest to the second pin. That is, in the embodiment of the present invention, the extending width of the plurality of first leads 202 in the second direction (the vertical direction is illustrated) is greater than the extending width of the plurality of second leads 204 in the second direction. This is because, in the array substrate, the number of data lines is generally about thousands to thousands, and the number of driving signal lines is generally about tens to twenty, and in order to arrange the data lines closely, the first pins 202 electrically connected to the data lines are arranged in a plurality of rows. In addition, referring to fig. 8 and fig. 10 together, in the second direction, the leading direction of the first pin 202 and the data line 210 is the upward direction in the figure, and the leading direction of the second pin 204 and the driving signal line 212 is the downward direction in the figure, that is, the leading direction of the first pin 202 electrically connected with the plurality of data lines 210 is opposite to the leading direction of the plurality of second pins 204 electrically connected with the plurality of driving signal lines 212. Therefore, when the first pins and the second pins each include a plurality of rows, an upper boundary of one of the second pins closest to the first pins in a row of the display area is set not to exceed an upper boundary of one of the first pins closest to the second pins in the row of the display area. Therefore, a lead wire arrangement area of the data wire fan-out area is reserved above the second pin, so that the second pin and the fan-out area of the data wire keep a proper distance. A setting area of the driving signal wire is reserved below the second lead wire, so that enough space is provided for setting the turning wire of the driving signal wire.

Referring to fig. 11, fig. 11 is another enlarged schematic view of the first non-display area in fig. 6. In this embodiment, the same structure as that in the embodiment shown in fig. 8 can be referred to the description related to fig. 8, and only the differences will be described in detail.

In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204 and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed at two sides of the first pin 202 and opposite to the third pin 206. The first pin 202, the second pin 204 and the third pin 206 are all located in the IC layout area 200.

In this embodiment, a distance between two non-adjacent first pins 202 of the plurality of first pins 202 and any one third pin 206 of the plurality of third pins 206 in the second direction Dy is smaller than a distance between at least one first pin 202 located between the two non-adjacent first pins 202 and any one third pin 206 of the plurality of third pins 206. That is, in the array substrate provided in the present embodiment, the first pins 202, which are located at two sides, are closer to the third pins 206 than the pins located at the middle.

Further, with reference to fig. 11, in the present embodiment, a sixth pin 205 is further disposed in the first non-display area, and the sixth pin 205 is not electrically connected to any lead. In the IC setting area 200 of the first non-display area, an IC is finally required to be set, and corresponding pins on the IC are electrically connected with various pins of the IC setting area 200. Generally, each type of pin, such as the first pin 202, the second pin 204 and the third pin 206, is formed by a conductor, and the conductor generally has a certain thickness to ensure the conductive connection performance. The pins have the function of transmitting new energy, play a role of supporting in the process of binding the IC, and can be simultaneously used as a supporting pad to bear the IC. Besides the pins, various leads can also play a certain bearing role. In the IC setting area, in the blank area, i.e., the positions where various pins are not set and the positions where various leads are not set, corresponding elements capable of supporting may be absent, which may cause the problems of IC loosening, poor contact, etc. due to the lack of support after the subsequent IC is bound.

Therefore, in this embodiment, in the first non-display area, the sixth pin 205 is further disposed, and the sixth pin 205 is not electrically connected to any other lead, and only plays a role of support. The sixth lead 205 is fabricated in the same layer as the first lead 202, the second lead 204, and the third lead 206. Further, in the present embodiment, a plurality of sixth pins 205 are included, and the sixth pins are located at two sides of the third pin 206 in the IC layout area 200 and are disposed opposite to the second pins 204. Thus, because the number of the third pins 206 is small, only a few lead wires of the driving signal line 212 are arranged below the third pins, the IC lacks a support at a position opposite to the third pins 206, and the sixth pin 205 is arranged at the position, which is beneficial to improving the stability of the subsequent IC after being bound and ensuring the display effect.

The embodiment of the invention further comprises a display panel, and the display panel may comprise the array substrate as described in the above embodiment, wherein the array substrate is provided with a first pin, a second pin and a third pin in a first non-display area of the array substrate. The first pin and the third pin are arranged oppositely, and the second pin is positioned at two sides of the first pin and arranged oppositely to the third pin. The first pin, the second pin and the third pin are all located in the IC setting area.

In this embodiment, a distance between two nonadjacent pins of the plurality of first pins and any one of the plurality of third pins in the second direction is smaller than a distance between at least one first pin located between the two nonadjacent first pins and any one of the plurality of third pins. That is, in the array substrate provided in this embodiment, the first pins, which are located at the pins at both sides, are closer to the third pin than the pins located in the middle.

In this embodiment, the plurality of second pins are located on two sides of the plurality of first pins, and in the second direction, at least two second pins exist, where a distance between the second pin close to the first pin and any one of the plurality of third pins is smaller than a distance between the second pin far from the first pin and any one of the plurality of third pins. That is, in the present embodiment, the second pin located outside the first pin is offset to the display region more away from the first pin, that is, is offset to the direction away from the third pin. In this embodiment, the second pins located at two sides of the first pin are divided into a fourth group and a fifth group, and in the fourth group/the fifth group of the second pins, as the second pins are far from the symmetric center of the array substrate, the second pins are shifted toward a direction close to the display area, that is, as the second pins are far from the symmetric center of the array substrate, the second pins are shifted toward the third pins.

The display panel that this embodiment provided, through first pin, under the condition that second pin and third pin set up, can guarantee to show the performance, guarantee promptly under first safe distance, second safe distance and the prerequisite of third safe distance for first pin, third pin are more close to the display area and set up, also promptly, compare prior art, can reduce the width of first non-display area in the second side, can further improve the display area and account for than, improve display effect.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. An array substrate includes:

the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; two adjacent scanning lines and two adjacent data lines are intersected to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array;

a non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, wherein the first non-display area and the second non-display area are arranged oppositely, and the third non-display area and the fourth non-display area are arranged oppositely; the third non-display area and the fourth non-display area are provided with a grid driving circuit, and the grid driving circuit comprises a plurality of driving signal lines;

the first non-display area comprises an IC setting area and an FPC setting area; the IC setting area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal wires; the plurality of first pins and the plurality of third pins are arranged oppositely; in the second direction, a distance between two nonadjacent first pins in the plurality of first pins and any one third pin in the plurality of third pins is smaller than a distance between at least one first pin located between the two nonadjacent first pins and any one third pin in the plurality of third pins; the plurality of second pins are located on two sides of the plurality of first pins, and at least two second pins exist in the second direction, wherein the distance between the second pin close to the first pin and any one of the plurality of third pins is smaller than the distance between the second pin far from the first pin and any one of the plurality of third pins.

2. The array substrate of claim 1, wherein:

in the second direction, a leading-out direction in which the plurality of first pins are electrically connected to the plurality of data lines is opposite to a leading-out direction in which the plurality of second pins are electrically connected to the plurality of driving signal lines.

3. The array substrate of claim 1, wherein:

the plurality of first pins comprise a plurality of first groups which are continuously arranged and a plurality of second groups which are continuously arranged; in the first group and the second group, the arrangement direction of the plurality of first pins is shifted toward a direction away from the display area as the first pins are away from the center of symmetry of the first non-display area.

4. The array substrate of claim 3, wherein:

the plurality of first pins further comprise a plurality of third groups which are continuously arranged, and the third groups are located between the first groups and the second groups.

5. The array substrate of claim 1, wherein:

the plurality of second pins comprise a plurality of continuously arranged fourth groups and a plurality of continuously arranged fifth groups; the fourth group and the fifth group are respectively positioned at two sides of the plurality of first pins; in the fourth group and the fifth group, the arrangement direction of the plurality of second pins is shifted toward the display region as it goes away from the center of symmetry of the first non-display region.

6. The array substrate of claim 5, wherein:

the first non-display area comprises a plurality of data leads, and two ends of the data leads are respectively and electrically connected with the data lines and the first leads; at least one of the plurality of data leads includes an inclined section, an extending direction of the inclined section intersects both the first direction and the second direction; the arrangement direction of the second pins of the fourth group or the fifth group and the extension direction of the inclined section form an included angle, and the included angle is greater than or equal to 0 degree and smaller than 45 degrees.

7. The array substrate of claim 1, wherein:

the FPC setting area is provided with a plurality of fourth pins and a plurality of fifth pins, and the fourth pins are electrically connected with the third pins.

8. The array substrate of claim 1, wherein:

any one of the plurality of first pins and any one of the plurality of second pins are identical in size and shape.

9. The array substrate of claim 1, wherein:

the distance between any two adjacent first pins is smaller than the distance between two adjacent first pins and the distance between two adjacent second pins.

10. The array substrate of claim 1, wherein:

the boundary of one second pin, which is closest to the plurality of first pins, in the second direction does not exceed the boundaries of the two first pins, which are closest to the second pin, in the second direction.

11. The array substrate of claim 1, wherein:

and a sixth pin is also arranged in the first non-display area and is not electrically connected with any lead.

12. A display panel comprising the array substrate according to any one of claims 1 to 11.