CN1116771A - Method for the fabrication of a semiconductor device - Google Patents
Method for the fabrication of a semiconductor device Download PDFInfo
- Publication number
- CN1116771A CN1116771A CN95104257A CN95104257A CN1116771A CN 1116771 A CN1116771 A CN 1116771A CN 95104257 A CN95104257 A CN 95104257A CN 95104257 A CN95104257 A CN 95104257A CN 1116771 A CN1116771 A CN 1116771A
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- CN
- China
- Prior art keywords
- bit line
- storage electrodes
- dielectric film
- layer
- contact hole
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for producing semiconductor devices, and the invention forms a storage electrode which has the same height with a bit line in a region without the bit line, thus leading steps between a unit region and a perimeter circuit region to be moderate and avoiding usage of extra storage electrode masks; when a contact orifice of the storage electrode is formed by using a contact orifice mask of the storage electrode and corrosion techniques, a corrosion blocking layer on the bit line is taken as an automatic-alignment corrosion blocking layer, therefore, the cylindrical storage electrode can be created. The invention not only can ensure simple techniques and improve reliability, but also can ensure that the focus depth of subsequent photoetching techniques has sufficient tolerance.
Description
The present invention relates generally to make the method for semiconductor device, be particularly related to the method that in DRAM, forms a capacitor, it can relax step between cellular zone and the peripheral circuit region, thereby decapacitation guarantees to improve production efficiency and the outer enough tolerances that can also guarantee the postorder photoetching process depth of focus of reliability.
According to the highly integrated trend of recent semiconductor device, along with dwindling of cell size, the enough capacitor of formation capacity is more and more difficult.For avoiding this class difficult problem, many solutions have been proposed.For example, in order to increase capacitor volume, in the DRAM device of forming by MOS transistor and capacitor, adopt high medium of a kind of dielectric constant or thin deielectric-coating.
Yet these solutions have it self problem.High to known dielectric constant medium, for example Ta
2O
5, TiO
2And SrTiO
3Do deep research.But these materials can not be used for practice in fact, because its reliability all is not verified as yet as node puncture voltage and film characteristics.With the reduced thickness of deielectric-coating, may in the device course of work, deielectric-coating be broken, thereby bring adverse influence to capacitor.
Except the solution of this employing medium, consider and guarantee enough jumbo difficulty, once propose to increase the surface area of storage electrodes.For example,, adopt a kind of needle construction (pin structure), be to utilize an electric conducting material that a plurality of many silicon layers are interconnected, or adopt cylindrical structure in order to increase the surface area of capacitor.
For understanding technical background of the present invention better, below to the explanation of conventional the making an explanation property of semiconductor device of adopting the cylindrical shape capacitor.
After setting up MOSFET on the semiconductor substrate, on the whole surface of resulting structures, form interlayer dielectric.Form the contacted bit line (bit line) that drains with MOSFET.Then, the place mat planarization layer (blanket planarization layer) of one better step coverage is set on resulting structures,, corrodes then as BPSG (boron-phosphorosilicate glass), form the contact hole of storage electrodes, expose the source electrode of MOSFET by these holes.Add that a conductive layer is to cover the contact hole of storage electrodes.On contact hole, form the thick oxide-film figure of cylindrical shape subsequently, on the sidewall of this oxide-film figure, form cylindrical shape conductive gasket (conductive spacer).Make mask with oxide-film figure and conductive gasket, the etching conductive layer is so that stay the conducting layer figure of still staying in the contact hole.Then, remove the thick oxide-film figure of cylindrical shape, finish the making of the cylindrical shape storage electrodes of forming by conductive gasket and conducting layer figure.
As mentioned above, the highly integrated requirement of semiconductor device is dwindled in semiconductor device by the occupied area of electric capacity.This is faced with the problem that capacity reduces with regard to making semiconductor device.A kind of conventional solution of this problem is to increase storage electrodes.Yet, because of storage electrodes increase and draw step between cellular zone and the peripheral circuit region become higher, thereby brought difficulty to post-order process.Such as, be used to form the photoetching process of metal line, be difficult to form precision graphic.So, be significantly low with regard to production efficiency and device functional reliability.
Because above-mentioned routine techniques uses contact mask and storage electrodes mask respectively, make the processing complexity that becomes reduce production efficiency again.
So, main purpose of the present invention is to overcome the problem that above-mentioned prior art runs into, and a kind of method of making semiconductor device is provided, by forming its height and bit line in the zone that does not have bit line, can lower the step between cellular zone and the peripheral circuit region with high storage electrodes.
Another object of the present invention is to provide a kind of method of not using extra storage electrodes mask can set up the cylindrical shape storage electrodes.
Another purpose of the present invention is to provide the method for simple manufacturing semiconductor device.
A further object of the present invention is to provide a kind of method of making semiconductor device, can guarantee enough degree of depth tolerances for the photoetching process of postorder.
Further purpose of the present invention is to provide the method that can improve production efficiency and reliability.
Based on creatively research in earnest of the inventor, by providing a kind of method of making semiconductor device to achieve the above object, this method may further comprise the steps: set up the MOSFET structure of being made up of gate oxidation films, gate electrode, the first dielectric film figure and source electrode and drain electrode on semiconductor chip; Form second dielectric film, the first rotten barrier layer and the 3rd dielectric film on the whole surface of resulting structures successively, the selective etching of said first corrosion layer is different from said the 3rd dielectric film than (etch selection ratio); Use the bit line contact mask to corrode successively from said the 3rd dielectric film, form the bit line contact hole, expose drain electrode by this hole to said second dielectric film; Sidewall at said bit line contact hole forms first insulating cell; Deposit bit line conductive layer, the 4th insulating film layer and second corrosion barrier layer successively on the whole surface of resulting structures; Use the bit line mask to corrode successively from said second corrosion barrier layer, form bit line, the 4th dielectric film and second corrosion respectively and stop figure to said bit line conductive layer; Insert the position that does not have said bit line that has been corroded with the pentasyllabic quatrain velum; Use the storage electrodes contact mask to corrode successively from said pentasyllabic quatrain velum, form the storage electrodes contact hole, expose said source electrode by this hole to said second dielectric film; Sidewall at said storage electrodes contact hole forms second insulating cell; Along the surface that is exposed in said storage electrodes contact hole conducting layer figure is set, said conducting layer figure plays the effect of storage electrodes; And on said storage electrodes, form deielectric-coating and plate electrode successively.
With reference to accompanying drawing,, can make above-mentioned purpose of the present invention and other advantage become more clear by detailed description to the preferred embodiment of the present invention.
Fig. 1 is the layout of the mask permutations used in making semiconductor device according to the present invention of expression.
Fig. 2 A～2E is that the constructed profile of the method for semiconductor device along I-I line of Fig. 1 made in expression.
Fig. 3 is the constructed profile of another embodiment of the present invention.
Can better understand the application of the preferred embodiment of the present invention with reference to accompanying drawing, wherein use identical label to represent identical and corresponding parts respectively.
With reference to Fig. 1, this is a section layout figure who is similar to general DRAM device, has represented to make according to the present invention the arrangement of the used mask of conductor device on the half.As shown in Figure 1, an active area A is formed with the source region in a zigzag, and each is longitudinally arranged by the grid line that separates that grid line mask B represents, also has vertical with the grid line bit line of being represented by bit line mask D.In this layout, also have storage electrodes contact mask E, each all is arranged in an end of active area, and bit line contact mask C is arranged in the middle part of active mask A.
Importantly do not adopt any storage electrodes mask separately.As will be described in further detail below, be similar to conventional storage electrodes mask, storage electrodes mask E is self aligned with following barrier layer, and the formation contact hole exposes the source electrode of MOSFET by this hole.
Fig. 2 represents to make the complete section sectional view of the preferred steps of semiconductor device along I-I line of Fig. 1 according to an embodiment.Explain these steps in conjunction with Fig. 2 A～2E.
Shown in Fig. 2 A, method of the present invention is from the formation of MOSFET.Promptly, on the predetermined area of semiconductor chip 1, be formed for after the dielectric film of element separation 2, the conductive layer of deposit gate oxide, gate electrode and first dielectric film successively all sidedly on resulting structures, use grid mask (in Fig. 1, representing) corrosion then with label " B ", the grid structure that formation is made of gate oxidation figure 3, gate electrode 4 and the first dielectric film figure 5, then, with the grid structure is mask, impurity is injected in the semiconductor chip 1, formation source electrode 6 and drain electrode 6 ', the conduction type of said impurity is different from the type of said semiconductor chip.Afterwards, this method is included in and forms thin second dielectric film 7, first corrosion barrier layer 8 and place mat the 3rd dielectric film 9 that is used for planarization on the MOSFET structure successively.Preferably use oxide-film for second dielectric film 7, preferably use silicon fiml, preferably use selective etching than a kind of material that is different from first corrosion barrier layer for the 3rd dielectric film 9 for first corrosion barrier layer 8.
With reference to Fig. 2 B, at first use bit line contact mask (among Fig. 2 B with label " C " representative) corrode successively drain electrode 6 ' on from the 3rd dielectric film 9 to gate oxidation films figure 3, form bit line contact hole 18, by this hole expose drain electrode 6 '.Then, the sidewall at bit line contact hole 18 forms first insulating cell 10.Then, deposit bit line conductive layer, the 4th insulating film layer that is used for planarization and second corrosion barrier layer successively on the whole surface of resulting structures, and use bit line mask (representing with label " E " among Fig. 1) corrosion, form bit line 11, the 4th dielectric film 12 and second corrosion respectively and stop figure 13.At the position that is corroded promptly is not have the zone of bit line 11 to fill with pentasyllabic quatrain velum 14BPSG.Deposit place mat photosensitive film, exposure under the situation that storage electrodes contact mask (representing with label " E " among Fig. 1) arranged, and, form photosensitive film figure 22 through developing process, expose by this figure and comprise that whole pentasyllabic quatrain velum 14 reaches near the predetermined area of the part second corrosion barrier layer figure 13.
To the second corrosion barrier layer figure 13, a kind of its selective etching is than the material that is different from third and fourth dielectric film 9,12, and for example nitride film share.When using first corrosion of nitride film do to stop 8, the second corrosion barrier layer figure 13 can prepare with silicon fiml.
Because second dielectric film 7 makes that first conductive gasket 10 that forms is thicker than what form on all the other zones in contact hole 18 on the grid structure side wall.
As for pentasyllabic quatrain velum 14, after finishing bit line 11 formation, deposit pentasyllabic quatrain velum layer, past again deep etch is until exposing the second corrosion barrier layer figure 13.
With reference to Fig. 2 C, use the photosensitive film figure 22 and second corrosion to stop that the exposed position of figure 13 makes mask, corrode pentasyllabic quatrain velum and the 3rd dielectric film 9 successively, then corrode the exposed part of first corrosion barrier layer 8 and second dielectric film 7.Its result forms storage electrodes contact hole 19, exposes source electrode 6.After removing photosensitive film figure 22, second insulating cell 15 is set on the sidewall of storage electrodes contact hole 19.
With reference to Fig. 2 D, deposit has the conductive layer that is used for storage electrodes 16 of predetermined thickness on the whole surface of the resulting structures of Fig. 2 C, for example silicon fiml, then formation photosensitive film 17 on the conductive layer 16 storage electrodes contact hole 19 in.About this point, the one place mat photosensitive film of deposit thickly toward deep etch, only stays the photosensitive film in the hole again.
With reference to Fig. 2 E, make mask with photosensitive film 17, the conductive layer 16 of selective etching storage electrodes, formation storage electrodes 16 '.Then, remove photosensitive film 17 and second corrosion stops figure 13.Further procedure of processing, though not shown, can conclude storage electrodes 16 ' the surface on form deielectric-coating, be on deielectric-coating, to form plate electrode.
According to the abovementioned embodiments of the present invention, use second corrosion to stop that figure and storage electrodes contact mask not only can be formed self-aligned the storage electrodes contact hole, and can not use the storage electrodes mask, in contact hole, form storage electrodes.Thereby it is minimum that step is forced into, and that is because the difference in height between storage electrodes and the bit line almost can be ignored.
Fig. 3 represents another embodiment of the present invention, is with the difference of embodiment 1, has removed second insulating cell on the storage electrodes lateral wall.Its result has increased the effective surface area of storage electrodes.In conjunction with some part among Fig. 2, describe present embodiment in detail.
Before second insulating cell 15 that forms Fig. 2 C, make the end thermal oxidation of the bit line 11 that exposes by formation storage electrodes contact hole 19, form oxide-film 30.Then, the sidewall at contact hole 19 forms second insulating cell 15.Carry out the technology shown in Fig. 2 D and the 2E, with form storage electrodes 16 '.At last, remove second insulating cell 15.If it is with Preparation of Silicon Coating first corrosion barrier layer 8,, also oxidized in the process that forms oxide-film 30 owing to forming the end that contact hole 19 exposes.On the cylindrical shape storage electrodes that this both side surface is all exposed, form deielectric-coating and plate electrode, the capacitor that can obtain having abundant capacitance.
As mentioned before, according to the present invention,, can alleviate the step between cellular zone and the peripheral circuit region fully owing to form storage electrodes at the low-lying place that does not have bit line.Certainly, smooth step helps to carry out the procedure of processing of postorder, for example makes photoetching easy.Second corrosion on bit line stops figure, and when using the storage electrodes contact mask to corrode, it plays a part the autoregistration corrosion barrier layer, thereby contact hole can be wide as much as possible in the limit of contact mask.Photoetching process subsequently is running easily just.Owing to not using any storage electrodes mask to form storage electrodes, this has just reduced processing step, thereby has improved productivity ratio.
After reading the preamble explanation,, can be more readily understood other characteristics of the present invention disclosed herein, advantage and embodiment for those of ordinary skills.About this point; though very described specific embodiments of the invention in detail; but under the prerequisite that does not break away from as specification spirit of the present invention claimed in illustrated and the claim and category, can carry out various variations and remodeling to these embodiments.
Claims (8)
1. method of making the semiconductor device comprise a MOSFET and a capacitor on semiconductor chip comprises following each step:
On semiconductor chip, set up a MOSFET structure that constitutes by gate oxidation films, gate electrode, the first dielectric film figure and source electrode and drain electrode;
Form second dielectric film, first corrosion barrier layer and the 3rd dielectric film on the whole surface of resulting structures successively, the selective etching ratio of said first corrosion layer is different from said the 3rd dielectric film;
Use the bit line contact mask to corrode successively, form the bit line contact hole, expose drain electrode by this hole from said the 3rd dielectric film to the second dielectric film;
Sidewall at said bit line contact hole forms first insulating cell;
Deposit bit line conductive layer, the 4th insulating film layer and second corrosion barrier layer successively on the whole surface of resulting structures;
Use the bit line mask to corrode successively from said second corrosion barrier layer, form bit line, the 4th dielectric film and second corrosion respectively and stop figure to said bit line conductive layer;
Insert the position that does not have said bit line that has been corroded with the pentasyllabic quatrain velum;
Use the storage electrodes contact mask to corrode successively from said pentasyllabic quatrain velum, form the storage electrodes contact hole, expose said source electrode by this hole to said second dielectric film;
Sidewall at said storage electrodes contact hole forms second insulating cell;
Along the surface that is exposed in said storage electrodes contact hole conducting layer figure is set, said conducting layer figure plays the effect of storage electrodes; And
On said storage electrodes, form deielectric-coating and plate electrode successively.
2. a basis the process of claim 1 wherein that said first corrosion barrier layer and said second corrosion barrier layer are respectively by silicon layer and nitride film preparation.
A basis the process of claim 1 wherein the said the 3rd and the pentasyllabic quatrain velum prepare by boron-phosphorosilicate glass.
4. method according to claim 1, the step of wherein said preparation conducting layer figure is after forming second insulating cell, conductive layer by deposit predetermined thickness on the whole surface of resulting structures, insert photosensitive film on the conductive layer in said storage electrodes contact hole, and corrode said conductive layer with said photosensitive film as mask and finish.
5. method of making the semiconductor device comprise a MOSFET and a capacitor on semiconductor chip comprises following each step:
On semiconductor chip, set up a MOSFET structure that constitutes by gate oxidation films, gate electrode, the first dielectric film figure and source electrode and drain electrode;
Form second dielectric film, first corrosion barrier layer and the 3rd dielectric film on the whole surface of resulting structures successively, the selective etching ratio of said first corrosion layer is different from said the 3rd dielectric film;
Use the bit line contact mask to corrode successively from said the 3rd corrosion barrier layer, form the bit line contact hole, expose drain electrode by this hole to said second dielectric film;
Sidewall at said bit line contact hole forms first insulating cell;
Deposit bit line conductive layer, the 4th insulating film layer and second corrosion barrier layer successively on the whole surface of resulting structures;
Use the bit line mask to corrode successively from said second corrosion barrier layer, form bit line, the 4th dielectric film and second corrosion respectively and stop figure to said bit line conductive layer;
Insert the position that does not have said bit line that has been corroded with the pentasyllabic quatrain velum;
Use the storage electrodes contact mask to corrode successively from said pentasyllabic quatrain velum, form the storage electrodes contact hole, expose said source electrode by this hole to said second dielectric film;
The end of the said bit line of oxidation, described end is exposed when forming said storage electrodes contact hole;
Sidewall at said storage electrodes contact hole forms second insulating cell;
Along the surface that is exposed in said storage electrodes contact hole conducting layer figure is set, said conducting layer figure plays the effect of storage electrodes;
Remove said second insulating cell, expose inside and outside relatively two surfaces of said storage electrodes; And
On said storage electrodes, form deielectric-coating and plate electrode successively.
6. method according to claim 5, wherein said first corrosion barrier layer and said second corrosion barrier layer are respectively by silicon layer and nitride film preparation.
7. one kind requires 5 method according to power, the wherein said the 3rd and the pentasyllabic quatrain velum prepare by boron-phosphorosilicate glass.
8. method according to claim 5, the step of wherein said preparation conducting layer figure is after forming second insulating cell, conductive layer by deposit predetermined thickness on the whole surface of resulting structures, insert photosensitive film on the conductive layer in said storage electrodes contact hole, and corrode said conductive layer with said photosensitive film as mask and finish.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR94-9963 | 1994-05-07 | ||
| KR1019940009963A KR0126640B1 (en) | 1994-05-07 | 1994-05-07 | Semiconductor device and manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1116771A true CN1116771A (en) | 1996-02-14 |
| CN1049300C CN1049300C (en) | 2000-02-09 |
Family
ID=19382624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN95104257A Expired - Fee Related CN1049300C (en) | 1994-05-07 | 1995-05-05 | Method for the fabrication of a semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR0126640B1 (en) |
| CN (1) | CN1049300C (en) |
| GB (1) | GB2289984B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099707C (en) * | 1996-07-29 | 2003-01-22 | 三星电子株式会社 | Method for manufaturing semiconductor device having capacitor on metal structure |
| CN100539113C (en) * | 2005-10-18 | 2009-09-09 | 台湾积体电路制造股份有限公司 | Anchor Damascene Structures |
| CN101140901B (en) * | 2006-09-06 | 2011-09-28 | 海力士半导体有限公司 | Method for manufacturing semiconductor device |
| CN101288080B (en) * | 2005-10-12 | 2012-05-23 | 国际商业机器公司 | Method for designing mask , system and method for delivering lithographical process design parameter |
| CN107785371A (en) * | 2013-03-11 | 2018-03-09 | 台湾积体电路制造股份有限公司 | Static random access memory device |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2324408A (en) * | 1997-01-21 | 1998-10-21 | United Microelectronics Corporation | Forming DRAM cells |
| CN1059983C (en) * | 1997-07-04 | 2000-12-27 | 联华电子股份有限公司 | Method of forming dynamic random access memory |
| JP2000012687A (en) * | 1998-06-23 | 2000-01-14 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| GB2341427A (en) * | 1998-09-08 | 2000-03-15 | Gerard Francis Robinson | Sealing member |
| JP3241020B2 (en) * | 1999-03-26 | 2001-12-25 | 日本電気株式会社 | Method for manufacturing semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DD299990A5 (en) * | 1990-02-23 | 1992-05-14 | Dresden Forschzentr Mikroelek | One-transistor memory cell arrangement and method for its production |
| DE69126559T2 (en) * | 1990-02-26 | 1997-10-02 | Nippon Electric Co | Semiconductor memory device |
| US5128549A (en) * | 1990-03-30 | 1992-07-07 | Beckman Instruments, Inc. | Stray radiation compensation |
| JP3123073B2 (en) * | 1990-11-08 | 2001-01-09 | 日本電気株式会社 | Method for manufacturing semiconductor memory device |
-
1994
- 1994-05-07 KR KR1019940009963A patent/KR0126640B1/en not_active IP Right Cessation
-
1995
- 1995-05-05 GB GB9509207A patent/GB2289984B/en not_active Expired - Fee Related
- 1995-05-05 CN CN95104257A patent/CN1049300C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1099707C (en) * | 1996-07-29 | 2003-01-22 | 三星电子株式会社 | Method for manufaturing semiconductor device having capacitor on metal structure |
| CN101288080B (en) * | 2005-10-12 | 2012-05-23 | 国际商业机器公司 | Method for designing mask , system and method for delivering lithographical process design parameter |
| CN100539113C (en) * | 2005-10-18 | 2009-09-09 | 台湾积体电路制造股份有限公司 | Anchor Damascene Structures |
| CN101140901B (en) * | 2006-09-06 | 2011-09-28 | 海力士半导体有限公司 | Method for manufacturing semiconductor device |
| CN107785371A (en) * | 2013-03-11 | 2018-03-09 | 台湾积体电路制造股份有限公司 | Static random access memory device |
| CN107785371B (en) * | 2013-03-11 | 2021-01-05 | 台湾积体电路制造股份有限公司 | Static random access memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR950034516A (en) | 1995-12-28 |
| GB2289984A (en) | 1995-12-06 |
| CN1049300C (en) | 2000-02-09 |
| KR0126640B1 (en) | 1998-04-02 |
| GB9509207D0 (en) | 1995-06-28 |
| GB2289984B (en) | 1998-03-11 |
| GB2289984A8 (en) | 1997-07-14 |
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Granted publication date: 20000209 Termination date: 20130505 |