CN111668302A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a via layer disposed over a substrate, a barrier layer disposed over the via layer, and a nitride layer disposed over the barrier layer. The semiconductor device also includes a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending to the nitride layer. In addition, the semiconductor device further includes a gate electrode disposed over the compound semiconductor layer, and a pair of source/drain electrodes disposed on both sides of the gate electrode. The source/drain electrode extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

Description

Semiconductor device and method of manufacturing the same

technical field

Embodiments of the present invention relate to semiconductor devices, and more particularly, to high electron mobility transistors and methods of fabricating the same.

Background technique

High electron mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a field effect transistor A field effect transistor (FET) consists of semiconductor materials with different energy gaps. A two-dimensional electron gas (2DEG) layer is created adjacent to the formed interface of different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, high electron mobility transistors can have the advantages of high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and thus are suitable for high-power devices.

When designing high electron mobility transistors, low on-resistance (R _on ) and high switching voltage (V _th ) are the main considerations. However, the two-dimensional electron gas of the GaN high electron mobility transistor does not need doping, and its carrier sources are mainly surface states and unintentional doping, which are essentially caused by defects. free charge carriers. Therefore, the two-dimensional electron gas of the GaN high electron mobility transistor is very sensitive to changes in the electric field, and electromagnetic dispersion (dispersion) occurs during the switching operation.

Therefore, while existing gallium nitride high electron mobility transistors are generally satisfactory for their intended purpose, they are not completely satisfactory in all respects. How to effectively solve the influence of electromagnetic scattering on device performance is the focus of current technology development.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a semiconductor device. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, and a nitride layer disposed over the barrier layer. The semiconductor device also includes a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer compliantly disposed over a portion of the barrier layer and extending over the nitride layer. In addition, the above-mentioned semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on both sides of the gate electrode. The source/drain electrodes extend through the spacer layer, the nitride layer and at least a portion of the barrier layer.

Embodiments of the present invention provide a method for fabricating a semiconductor device. The method includes forming a channel layer over a substrate, forming a barrier layer over the channel layer, forming a nitride layer over the barrier layer, etching back the nitride layer and the barrier layer to form a recess, wherein the recess A spacer layer is conformally formed over the nitride layer and in the recess through the nitride layer and a portion of the barrier layer, and a compound semiconductor layer is formed over the spacer layer. The compound semiconductor layer described above has an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer is filled into the recess. The method further includes forming a gate electrode over the compound semiconductor layer, and forming a pair of source/drain electrodes on both sides of the gate electrode, wherein the source/drain electrodes extend through the spacer layer, the nitride layer and at least part of the barrier layer.

The following examples and accompanying reference drawings will provide a detailed description.

Description of drawings

Some embodiments of the present invention will be described in detail below with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the devices may be arbitrarily enlarged or reduced to clearly represent the components of the embodiments of the invention.

1-5 are schematic cross-sectional views illustrating various intermediate stages of an example method for forming the semiconductor device of FIG. 6, according to some embodiments;

FIG. 6 is a schematic diagram of a semiconductor device.

Description of reference numerals

10～Semiconductor device;

100～substrate;

102～nucleation layer;

104~buffer layer;

106 ~ channel layer;

108 ~ barrier layer;

110～Nitride layer;

112～notch;

114 ~ spacer layer;

116～compound semiconductor layer;

116a ~ upper part;

116b ~ lower part;

118～gate electrode;

120～source/drain electrode;

W1, W2 ~ thickness.

Detailed ways

The following disclosure provides many different embodiments or examples to illustrate different components of embodiments of the invention. The following will disclose specific examples of the various components of the present specification and their arrangement, so as to simplify the description of the present invention. Of course, these specific examples are not intended to limit the invention. For example, if the following description of the invention describes that the first part is formed on or above the second part, it means that it includes the embodiment in which the first and second parts are formed in direct contact, and also includes the embodiment that the formed first and second parts are in direct contact. Additional components may be formed between the first and second components described above, the first and second components being embodiments that are not in direct contact. Furthermore, the various examples in the description may use repeated reference symbols and/or wording. These repeated symbols or words are used for simplicity and clarity, and are not used to limit the relationships between the various embodiments and/or the configurations.

Furthermore, for convenience in describing the relationship of one device or component to another device or component(s) in the figures, spatially relative terms such as "below", "below", "lower", "above" may be used , "upper" and similar terms. In addition to the orientation depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. When the device is turned in a different orientation (eg, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation. It should be understood that additional operations may be provided before, during, and/or after the method described in the embodiments of the present invention, and in other embodiments of the method, some of the described operations may be replaced or omitted.

Herein, the terms "about", "approximately", "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or within 3% Within %, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, “about”, “approximately” and “approximately” can still be implied without the specific description of “about”, “approximately” and “approximately”. probably" meaning.

Several variations of example methods and structures are described herein. Those of ordinary skill in the art will readily appreciate that other modifications can be made within the scope of other embodiments. Although some method embodiments are discussed as being performed in a particular order, various other method embodiments can be performed in another logical order and can include fewer or more steps than those discussed herein. In some figures, the device symbols of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting such figures.

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, which are particularly suitable for high electron mobility transistors (HEMTs). In some embodiments of the present invention, by disposing a nitride layer and a spacer layer on the barrier layer, and truncating the two layers in the gate region to form a notch, the electromagnetic dispersion problem of the device can be eliminated, while the The thickness of the barrier layer outside the gate region can be made thicker to reduce the on-resistance, and the gate doping can also be reduced without reducing the switching voltage. In this way, the deadlock of on-resistance (R _on ), switching voltage (threshold voltage, V _th ), and tripartite trade-off of electromagnetic scattering can be resolved.

FIGS. 1-5 are schematic cross-sectional views illustrating various intermediate stages of an example method for forming the semiconductor device 10 of FIG. 6 in accordance with some embodiments.

FIG. 1 illustrates initial steps of a method of forming a semiconductor device 10 in accordance with an embodiment of the present invention. As shown in FIG. 1, a substrate 100 is provided. Next, a buffer layer 104 is formed on the substrate 100 , a channel layer 106 is formed on the buffer layer 104 , and a barrier layer 108 is formed on the channel layer 106 . In some embodiments, a nucleation layer 102 may be formed between the substrate 100 and the buffer layer 104 , as shown in FIG. 1 .

The substrate 100 described above may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (eg, using p-type or n-type) doped (dopant) or undoped. In general, a semiconductor-on-insulator substrate includes a layer of semiconductor material formed on an insulator. For example, the insulating layer may be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a poly-silicon (poly-silicon) layer, or a stacked combination of the above-mentioned film layers. The above insulating layer is provided on a substrate, usually a silicon (silicon) or aluminum nitride (AlN) substrate. Other substrates may also be used, such as multi-layered or gradient substrates. In some embodiments, the semiconductor material of the semiconductor substrate may include silicon with different crystal planes, including Si(111) or Si(110). In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire (Sapphire) substrate.

The above-mentioned nucleation layer 102 can alleviate the lattice difference between the substrate 100 and the film layer grown above, so as to improve the crystal quality. The nucleation layer 102 is selective. In some embodiments, the material of the nucleation layer 102 may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or a combination thereof. For example, the thickness of the nucleation layer 102 may be in the range of about 1 nanometer (nm) to about 500 nanometers, such as about 200 nanometers. In some embodiments, the nucleation layer 102 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy ( Molecular Beam Epitaxy, MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or a combination of the foregoing.

The buffer layer 104 may relieve the strain of the channel layer 106 subsequently formed over the buffer layer 104 to prevent defects from forming in the channel layer 106 above, the strain being caused by the mismatch between the channel layer 106 and the substrate 102 . In other embodiments, as mentioned above, the nucleation layer 102 may not be provided, and the buffer layer 104 may be formed directly on the substrate, so as to simplify the process steps and also achieve improved effects. In some embodiments, the material of the buffer layer 104 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 104 may be or include gallium nitride (Gallium Nitride, GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), other suitable materials , or a combination of the foregoing. For example, the thickness of the buffer layer 104 may range from about 500 nanometers to about 50,000 nanometers. In some embodiments, the buffer layer 104 may be formed by a deposition process, such as metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), Other suitable processes, or a combination of the above.

Through the piezoelectric polarization effect and the respective spontaneous polarizations caused by the different lattice constants between the channel layer 106 and the barrier layer 108 , the channel layer 106 and the barrier layer 108 can be formed between the channel layer 106 and the barrier layer 108 . A two-dimensional electron gas (2DEG) (not shown) is formed on the hetero interface between the two. The semiconductor device 10 shown in FIG. 6 is a high electron mobility transistor (HEMT) using two-dimensional electron gas (2DEG) as conductive carriers. In some embodiments, channel layer 106 and barrier layer 108 are free of dopants. In some other embodiments, the channel layer 106 and the barrier layer 108 may have dopants, such as n-type dopants or p-type dopants. In a specific embodiment of the present invention, the channel layer 106 acts as a source of two-dimensional electron gas by its own unintentional doping. For example, the above-mentioned unintentional doping may be a defect present in the background, a free donor, or the like. In some embodiments, the unintentionally doped dopant concentration ranges from about 5× ^{10 16} to about 5× ^{10 17} cm ⁻³ .

In some embodiments, the material of the channel layer 106 may include one or more group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the channel layer 106 may be or include GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or a combination thereof. In some embodiments, the thickness of the channel layer 106 may range between about 0.05 micrometers (micrometer, μm) and about 1 micrometer, eg, about 0.2 micrometers. According to some embodiments, the channel layer 106 may be formed by a deposition process, such as metal organochemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), others appropriate process, or a combination of the above.

In some embodiments, the material of the barrier layer 108 may comprise a III-V compound semiconductor material, such as a III-nitride. For example, the barrier layer 108 may be or include AlN, AlGaN, AlInN, AlGaInN, other suitable materials, or a combination thereof. The barrier layer 108 may comprise a single-layer or multi-layer structure. Compared with the general high electron mobility transistor, the high electron mobility transistor of the embodiment of the present invention has a thicker barrier layer, and thus can significantly reduce the on-resistance (R _on ) of the device. For example, the barrier layer 108 has a maximum thickness W1, which may be in the range of about 10 nanometers to about 60 nanometers, such as about 40 nanometers. In some embodiments, the barrier layer 108 may be formed by a deposition process, such as metal organochemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) , other suitable processes, or a combination of the foregoing.

With continued reference to FIG. 1 , a nitride layer 110 is formed over the barrier layer 108 . This nitride layer 110 can protect the barrier layer 108 from oxidation in subsequent processes. In addition, the nitride layer 110 can also eliminate the electromagnetic scattering problem of the device, which will be described in detail later. In some embodiments, the material of the nitride layer 110 may be or include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN), nitride Indium Gallium (InGaN), other suitable materials, or a combination of the above. In some embodiments, the thickness of the nitride layer 110 may range from about 1 nanometer to about 20 nanometers, eg, about 5 nanometers. According to some embodiments, the nitride layer 110 may be formed by a deposition process, such as metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), Other suitable processes, or a combination of the above.

Next, as shown in FIG. 2 , the nitride layer 110 and the barrier layer 108 are etched back to form recesses 112 , wherein the recesses 112 pass through the nitride layer 110 and a portion of the barrier layer 108 . The above-mentioned recesses 112 correspond to the positions where the gate electrodes 118 (not shown in FIG. 3 , but the description of FIG. 5 can be referred to below) are intended to be formed. The notch 112 is formed so that a portion of the barrier layer 108 located below the notch 112 has a reduced thickness W2. This reduced thickness W2 is located below the gate electrode 118 to be formed later (not shown in FIG. 2, but reference is made to the description below with respect to FIG. 5), which helps to increase the switching voltage ( _Vth ) of the device ). In some embodiments, this reduced thickness W2 may be in the range of about 5 nanometers to about 15 nanometers, eg, about 10 nanometers.

Generally speaking, the two-dimensional electron gas of GaN high electron mobility transistors mainly comes from two sources, one is the free carriers from surface states, and the other is unintentional doping from the channel layer. ; and because of the heterostructure and polarization electric field between the barrier layer and the channel layer, the source of the two-dimensional electron gas is usually the former. Therefore, when the semiconductor device is in the off state, the carriers in the channel layer are trapped by the high electric field on the surface. When the semiconductor device is switched from the off state to the on state, the confined carriers in the channel layer 106 cannot be released in time (ie, the relaxation time is too long), resulting in a decrease in current, which is electromagnetic Scattering problem. In the embodiment of the present invention, since the nitride layer accommodates most of the free carriers from the surface state, the channel layer of the lower layer must be forced to absorb carriers from unintentional doping, thus avoiding the closed state of the channel layer. high electric field effects. In addition, the nitride layer 110 is cut off by the notch 112, so when the semiconductor device 10 is turned on, the nitride layer 110 does not participate in current conduction, so there is no electromagnetic scattering problem. In this way, the nitride layer 110 can withstand the high electric field of the surface state instead of the channel layer 116 to avoid the electromagnetic scattering problem of the semiconductor device 10 .

In some embodiments, the nitride layer 110 and the barrier layer 108 may be etched back through a patterning process to form the recess 112 . For example, the patterning process described above may include a photolithography process (eg, photoresist coating, soft bake, mask aligning, exposure, post exposure bake, photoresist development, other suitable process, or a combination of the above), an etching process (eg, a wet etch process, a dry etch process, other suitable processes, or a combination of the above), other suitable processes, or a combination of the above. In some embodiments, a patterned photoresist layer (not shown) having openings corresponding to the notches 112 may be formed on the nitride layer 110 by a photolithography process, and then an etching process may be performed to remove the patterning Parts of the nitride layer 110 and the barrier layer 108 are exposed by the openings of the photoresist layer to form recesses 112 in the nitride layer 110 and the barrier layer 108 . The patterned photoresist layer can then be removed by a process such as ashing or wet strip.

Referring to FIG. 3 , the spacer layer 114 is compliantly formed on the nitride layer 110 and in the recess 112 , so the spacer layer 114 is compliantly formed on the bottom surface and sidewalls of the recess 112 . In some embodiments, the bandgap of the spacer layer 114 is larger than that of the subsequently formed compound semiconductor layer 116 (not shown in FIG. 3 , but please refer to the description of FIG. 5 below). Therefore, the spacer layer 114 can prevent the dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10 to avoid an increase in on-resistance and reduce the electromagnetic scattering problem of the device. In addition, during the subsequent etching process for forming the compound semiconductor layer 116 , the spacer layer 114 may also serve as an etch stop layer (ESL) to stop the etching process.

The spacer layer 114 may be formed of a material having a different etch selectivity than that in the adjacent film layer or feature (ie, the compound semiconductor layer 116 ). In some embodiments, the spacer layer 114 is an aluminum-containing nitride. For example, the material of the spacer layer 114 may be or include AlN, AlGaN, AlInN, AlGaInN, other suitable materials, or a combination thereof. In a specific embodiment, the spacer layer 114 described above is AlN. Furthermore, in some embodiments, the thickness of the spacer layer 114 may be in the range of about 1 nanometer to about 7 nanometers, eg, about 2 nanometers.

FIG. 4 illustrates the formation of the compound semiconductor layer 116 . In some embodiments, the compound semiconductor layer 116 is conformally formed on the spacer layer 114, and then a pattern is defined by photolithography, wherein the compound semiconductor layer has an upper portion 116a and a lower portion 116b, wherein the lower portion 116b of the compound semiconductor layer 116 defines a pattern The portion filled in the recess 112 for the compound semiconductor layer 116 is shown in FIG. 4 . In other words, the compound semiconductor layer 116 corresponds to the position where the gate electrode 118 (not shown in FIG. 3 , but the description of FIG. 5 can be referred to below) is intended to be formed. The compound semiconductor layer 116 can suppress the generation of two-dimensional electron gas (2DEG) under the gate electrode 118 to achieve a normally-off state of the semiconductor device.

In some embodiments, the material of the compound semiconductor layer 116 may be p-type doped or n-type doped gallium nitride (GaN). For example, the thickness of the upper portion 116a of the compound semiconductor layer 116 may be in the range of about 5 to about 100 nanometers, such as about 60 nanometers, and the thickness of the lower portion 116b of the compound semiconductor layer 116 may be in the range of about 7 to about 72 nanometers, For example about 40 nanometers. In some embodiments, the doping concentration of the upper portion 116a of the compound semiconductor layer 116 may be different from the doping concentration of the lower portion 116b of the compound semiconductor layer 116 .

In some embodiments, the compound semiconductor layer 116 may be formed by a deposition process and a patterning process. For example, a deposited material layer may be formed on the spacer layer 114 by a deposition process, wherein a portion of the deposited material layer fills the recess 112 . In some embodiments, the patterning process includes forming a patterned mask layer (not shown) on the deposited material layer, then etching portions of the deposited material layer not covered by the patterned mask layer, and forming a compound semiconductor layer 116.

In some embodiments, the deposition process may include metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), similar processes, or combinations of the foregoing.

In some embodiments, the patterned mask layer may be a photoresist, such as a positive type photoresist or a negative type photoresist. In other embodiments, the patterned mask layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, similar materials, or combinations of the foregoing. In some embodiments, spin-on coating (spin-on coating), physical vapor deposition (PVD), chemical vapor deposition (chemical vapor deposition, CVD), other suitable processes, or a combination of the above may be used. The above patterned mask layer is formed.

In some embodiments, the deposited material layer may be etched by a dry etch process, a wet etch process, or a combination of the foregoing. For example, the etching of the deposited material layer includes reactive ion etch (RIE), inductively-coupled plasma (ICP) etch, neutron beam etch (NBE), electron Electron cyclotron resonance (ERC) etching, other suitable etching processes, or a combination of the above.

In some embodiments, the upper portion 116a of the compound semiconductor layer 116 may extend to the surface of the spacer layer 114 outside the notch, that is, the compound semiconductor layer 116 has a T-shape in a schematic cross-sectional view, as shown in FIG. 4 . In other embodiments, the upper portion 116a of the compound semiconductor layer 116 does not extend to the surface of the spacer layer 114 outside the notch, and the compound semiconductor layer 116 has a rectangular shape (not shown) in the schematic cross-sectional view. In some embodiments, the upper surface of the compound semiconductor layer 116 may be uneven. In some embodiments, the length of the upper portion 116a of the compound semiconductor layer 116 extending to the surface of the spacer layer 114 outside the notch may be asymmetric.

In some embodiments, the formation of the compound semiconductor layer 116 further includes doping with a dopant to increase the switching voltage (V _th ) of the semiconductor device 10 . For example, when the material of the compound semiconductor layer 116 is p-type doped gallium nitride, the dopant may include magnesium (Mg). Generally speaking, during the process of a semiconductor device, multiple heat treatments are usually performed, so that the dopants are thermally diffused out of the compound semiconductor layer and into other components, thereby affecting the performance of the semiconductor device, such as increasing the on-resistance and causing the device’s breakdown. Electromagnetic scattering problem. However, in the embodiment of the present invention, since the compound semiconductor layer 116 is separated from other components by the spacer layer 114 , the thermal diffusion of dopants in the compound semiconductor layer 116 can be prevented from entering other components. In this way, the problem of increasing on-resistance and electromagnetic scattering of the device can be avoided, and the performance of the semiconductor device 10 can be improved.

In addition, in the embodiments of the present invention, since the barrier layer 108 under the predetermined position of the gate electrode 118 has a reduced thickness W2 (see FIG. 5 ), the reduced thickness W2 helps to improve the switching of the semiconductor device 10 Voltage. In other words, under the same switching voltage, the compound semiconductor layer 116 can have a smaller dopant concentration, which reduces the influence of thermal diffusion of the dopant to other components, which also helps to reduce the electromagnetic scattering problem of the device.

Referring to FIG. 5 , a gate electrode 118 is formed on the compound semiconductor layer 116 . In some embodiments, the material of the gate electrode 118 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al) ), copper (Cu), titanium nitride (TiN), similar materials, alloys of the above, multilayer structures of the above, or a combination of the above, and the semiconductor material may be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly- Ge). In some embodiments, the step of forming the gate electrode 118 may include fully depositing a layer of conductive material (not shown) for the gate electrode 118 over the substrate 100, and performing a patterning process on the layer of conductive material to form The gate electrode 118 is on the compound semiconductor layer 116 . The deposition process to form the conductive material may be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (eg, sputtering), a combination of the foregoing, or the like.

6, a pair of source/drain electrodes 120 are disposed on both sides of the gate electrode 118, wherein the pair of source/drain electrodes 120 extend through the spacer layer 114, the nitride layer 110, and a portion the barrier layer 108. In some embodiments, the formation of the source/drain 120 pair includes performing a patterning process to etch the spacer layer 114 , the nitride layer 110 , and a portion of the barrier layer 108 on both sides of the compound semiconductor layer 116 , A pair of notches is formed through the spacer layer 114 and the nitride layer 110 and extending to the barrier layer 108, then a conductive material is deposited over the pair of notches, and a patterning process is performed on the deposited conductive material to achieve the desired The location forms the pair of source/drain 120 . The deposition process and materials used to form the pair of source/drain electrodes 120 may be similar to the deposition process and materials of the gate electrode 118 and will not be repeated here.

Although in the embodiment shown in FIG. 6, the source/drain pair 120 is located on the spacer layer 114, passes through the spacer layer 114 and the nitride layer 110 and extends to the barrier layer 108, but the invention is not limited thereto, The extension depth of the pair of source/drain 120 can be adjusted according to the characteristics required by the actual product. For example, the source/drain pair 120 may also extend through the barrier layer 108 and into the channel layer 106 .

Although it is described herein that the source/drain electrodes 120 and the gate electrodes 118 are formed in different steps, the invention is not limited thereto. For example, before forming the gate electrode 118, a notch for the source/drain electrode 120 may be formed first, and then the source/drain electrode 120 and the gate electrode may be simultaneously formed by a deposition process and a patterning process electrode 118. Also, the formation of the source/drain electrodes 120 and the gate electrode 118 may independently comprise the same or different processes and materials. In addition, the shapes of the source/drain electrodes 120 and the gate electrodes 118 are not limited to the vertical sidewalls in the drawings, and may also be inclined sidewalls or have other topography.

As shown in FIG. 6 , the semiconductor device 10 includes a channel layer 106 disposed on the substrate 100 , a barrier layer 108 disposed on the channel layer 106 , and a nitride layer 110 disposed on the barrier layer 108 . In some embodiments, barrier layer 108 has a maximum thickness W1 ranging from about 10 nanometers to about 60 nanometers. Compared with general high electron mobility transistors, the semiconductor device 10 has a thicker barrier layer 108, and thus can significantly reduce the on-resistance (R _on ). In addition, the above-mentioned nitride layer 110 can withstand the high electric field of the surface state instead of the channel layer 116 , thereby avoiding the electromagnetic scattering problem of the semiconductor device 10 .

The semiconductor device 10 also includes a compound semiconductor layer 116 having an upper portion 116a and a lower portion 116b , wherein the lower portion 116b passes through the nitride layer 110 and a portion of the barrier layer 108 . In addition, the semiconductor device 10 also includes a spacer layer 114 compliantly disposed on the lower portion 116 b of the compound semiconductor layer 116 and extending to the nitride layer 110 . The spacer layer 114 can prevent the dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10 , thereby avoiding the increase of on-resistance and the problem of electromagnetic scattering of the device, thereby improving the performance of the semiconductor device 10 .

The semiconductor device 10 further includes a gate electrode 118 disposed on the compound semiconductor layer 116, and a pair of source/drain electrodes 120 disposed on both sides of the gate electrode 118, the source/drain electrodes 120 extending through through the spacer layer 114 , the nitride layer 110 and at least a portion of the barrier layer 108 . The barrier layer 108 has a reduced thickness W2 (see FIG. 5 ) below the gate electrode 118 , which helps to increase the switching voltage (V _th ) of the semiconductor device 10 . In other words, under the same switching voltage, the compound semiconductor layer 116 can have a smaller dopant concentration, which reduces the influence of thermal diffusion of the dopant to other components, which also helps to reduce the electromagnetic scattering problem of the device. In some embodiments, this reduced thickness W2 ranges from about 5 nanometers to about 15 nanometers.

In some embodiments, the semiconductor device 10 further includes a buffer layer 104 between the substrate 100 and the channel 106 , and the buffer layer 104 can relieve the strain of the channel layer 106 subsequently formed above the buffer layer 104 to prevent defects is formed in the channel layer 106 above.

To sum up, the semiconductor device according to the embodiment of the present invention includes the nitride layer disposed on the barrier layer, and the nitride layer can eliminate the electromagnetic dispersion problem of the semiconductor device. In this way, the deadlock of three-way trade-off between on-resistance (R _on ), switching voltage (V _th ), and electromagnetic scattering can be resolved.

The features of several embodiments of the present invention are briefly described above, so that those skilled in the art can more easily understand the present invention. Anyone with ordinary knowledge in the art should understand that this specification can easily be used as a basis for modification or design of other structures or processes to achieve the same purpose and/or obtain the same advantages of the embodiments of the present invention. Any person with ordinary knowledge in the technical field can also understand that the structures or processes equivalent to the above do not depart from the spirit and protection scope of the present invention, and can be modified without departing from the spirit and scope of the present invention. Substitution and Retouch.

Claims (22)

1. A semiconductor device, characterized in that the device comprises: a channel layer disposed on a substrate; a barrier layer, disposed on the channel layer; a nitride layer disposed on the barrier layer; a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a portion of the barrier layer; a spacer layer conformably disposed on a portion of the barrier layer and extending onto the nitride layer; a gate electrode disposed on the compound semiconductor layer; and a pair of source/drain electrodes disposed on both sides of the gate electrode, wherein the pair of source/drain electrodes extend through the spacer layer, the nitride layer and at least a portion of the barrier Floor. 2. The semiconductor device of claim 1, wherein the nitride layer comprises gallium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, indium gallium nitride, or any combination thereof . 3 . The semiconductor device of claim 1 , wherein the thickness of the nitride layer ranges from 1 nm to 20 nm. 4 . 4. The semiconductor device according to claim 1, wherein the spacer layer has a larger energy gap than the compound semiconductor layer and the nitride layer. 5. The semiconductor device of claim 4, wherein the spacer layer comprises aluminum nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or any combination thereof. 6 . The semiconductor device of claim 1 , wherein the thickness of the spacer layer ranges from 1 nm to 7 nm. 7 . 7 . The semiconductor device of claim 1 , wherein the pair of source/drain electrodes passes through the barrier layer and extends to the channel layer. 8 . 8 . The semiconductor device of claim 1 , wherein the barrier layer has a maximum thickness, wherein the maximum thickness ranges from 10 nanometers to 60 nanometers. 9 . 9 . The semiconductor device of claim 8 , wherein the barrier layer has a thickness below the gate electrode, and the thickness ranges from 5 nanometers to 15 nanometers. 10 . 10. The semiconductor device of claim 1, further comprising a buffer layer located between the substrate and the channel layer. 11 . The semiconductor device of claim 1 , wherein an upper portion and a lower portion of the compound semiconductor layer have different doping concentrations. 12 . 12. A method of manufacturing a semiconductor device, wherein the method comprises: forming a channel layer on a substrate; forming a barrier layer over the channel layer; forming a nitride layer over the barrier layer; etching the nitride layer and the barrier layer to form a notch, wherein the notch passes through the nitride layer and a portion of the barrier layer; conformally forming a spacer layer on the nitride layer and in the recess; forming a compound semiconductor layer on the spacer layer, the compound semiconductor layer has an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer fills the recess; forming a gate electrode over the compound semiconductor layer; and A pair of source/drain electrodes are formed on both sides of the gate electrode, wherein the pair of source/drain electrodes extend through the spacer layer, the nitride layer and at least a portion of the barrier layer . 13. The method for manufacturing a semiconductor device according to claim 12, wherein the nitride layer comprises gallium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, indium gallium nitride, or any combination. 14. The method for manufacturing a semiconductor device according to claim 12, wherein the thickness of the nitride layer ranges from 1 nanometer to 20 nanometers. 15. The method of claim 12, wherein the spacer layer has a larger energy gap than the compound semiconductor layer and the nitride layer. 16. The method of claim 15, wherein the spacer layer comprises aluminum nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or any combination thereof. 17 . The method for manufacturing a semiconductor device according to claim 12 , wherein the thickness of the spacer layer ranges from 1 nm to 7 nm. 18 . 18 . The method of claim 12 , wherein the pair of source/drain electrodes passes through the barrier layer and extends to the channel layer. 19 . 19 . The method of claim 12 , wherein the barrier layer has a maximum thickness, wherein the maximum thickness ranges from 10 nanometers to 60 nanometers. 20 . 20 . The method of claim 19 , wherein the barrier layer has a thickness below the gate electrode, and the thickness ranges from 5 nm to 15 nm. 21 . 21. The method of claim 12, further comprising forming a buffer layer between the substrate and the channel layer. 22. The method of manufacturing a semiconductor device according to claim 12, wherein an upper portion and a lower portion of the compound semiconductor layer have different doping concentrations.

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