CN111668112A - Semiconductor packaging method - Google Patents

Abstract

The application provides a semiconductor packaging method. The semiconductor packaging method comprises the steps that a plurality of mounting areas and blank areas are divided on a carrier plate, the blank areas are located between at least two adjacent mounting areas, a plurality of chips to be packaged are mounted in the mounting areas, and elastic isolation pieces are arranged in the blank areas; the front surfaces of the chips to be packaged face the carrier plate; and forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the plurality of chips to be encapsulated and the elastic separator.

Description

Semiconductor packaging method

technical field

The present application relates to the technical field of semiconductors, and in particular, to a semiconductor packaging method.

Background technique

Common semiconductor packaging technology, such as chip packaging technology, mainly includes the following process: first, the front side of the bare chip is bonded to the carrier board by tape, and then hot-pressed and plastic-sealed, then the carrier board is peeled off, and the front side of the bare chip is re-wiring process. , forming a re-wiring structure, and encapsulating it.

However, after thermocompression molding, the molded product after molding is prone to warpage, especially in the panel-level packaging process, the warpage phenomenon is more likely to occur, making it difficult to position the die accurately in the subsequent rewiring process. position, which greatly affects the re-wiring process, and even makes the re-wiring process difficult to carry out.

SUMMARY OF THE INVENTION

One aspect of the present application provides a semiconductor packaging method, comprising:

A plurality of mounting areas and blank areas are divided on the carrier board, the blank areas are located between at least two adjacent mounting areas, a plurality of chips to be packaged are mounted on the multiple mounting areas, and The elastic spacer is arranged in the blank area; wherein, the front surfaces of the plurality of chips to be packaged face the carrier board;

An encapsulation layer is formed, the encapsulation layer covers the carrier board, and the encapsulation layer is used to encapsulate the plurality of chips to be packaged and the elastic spacer.

Optionally, the material of the elastic spacer includes silicone rubber.

Optionally, the thickness of the elastic spacer is smaller than the thickness of the encapsulation layer.

Optionally, the thickness D1 of the elastic spacer and the thickness D of the encapsulation layer satisfy: 0.4D<D1<0.9D.

Optionally, the thickness D1 of the elastic spacer and the thickness D of the encapsulation layer satisfy: D1=2/3D.

Optionally, the thickness D1 of the elastic spacer satisfies: 400 μm≤D1≤800 μm.

Optionally, the elastic spacer includes a strip-shaped spacer extending in one direction; or,

The elastic spacer includes a plurality of spacers.

Optionally, when the elastic spacer includes a plurality of spacers, the elastic spacer includes a first spacer extending along the width direction of the carrier plate and a second spacer extending along the length direction of the support plate. The first isolation part and the second isolation part of the elastic spacer are cross-connected, and the length of the first isolation part is the same as the width of the carrier plate, and the length of the second isolation part is the same as that of the carrier board. The boards are the same length.

Optionally, when the elastic spacer includes multiple isolation parts, at least two of the multiple isolation parts are cross-connected, and at least one isolation part deviates from the width direction of the carrier board and deviates from the carrier board. Extends in the direction of the length direction.

Optionally, the manufacturing method of the elastic spacer is:

Thermoforming elastic bare board;

The elastic bare board is trimmed, and the trimmed area corresponds to the mounting area on the carrier board.

Optionally, after forming the encapsulation layer, the method includes:

peeling off the carrier to expose the front surfaces of the plurality of chips to be packaged;

A redistribution structure is formed on the front surface of the chip, and the redistribution structure is used to lead out the bonding pads on the front surface of the chip.

Optionally, after forming the encapsulation layer and before peeling off the carrier board, the method includes mounting a support plate on a first surface of the encapsulation layer away from the carrier board;

After forming a redistribution structure on the front side of the chip, the method includes peeling off the support plate.

In the above-mentioned semiconductor packaging method provided by the embodiments of the present application, through the arrangement of elastic spacers, elastic spacers are provided in the large-area panel formed by the encapsulation layer that encapsulates the mounting area and the blank area, so that the entire larger area is provided with elastic spacers. The large-area panel has good elasticity, thereby reducing the warpage of the encapsulation layer and the entire plastic-encapsulated product, ensuring the success rate of packaging and the yield of the product.

Description of drawings

FIG. 1( a ) is a schematic structural diagram of a bare chip in the prior art when it is subjected to a force of a molding resin material.

Figure 1(b) is a schematic structural diagram of the warpage of the molded product after thermocompression and plastic sealing.

FIG. 2 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.

3(a)-3(g) are process flow diagrams of a semiconductor packaging method according to an exemplary embodiment of the present disclosure.

FIG. 4( a ) is a schematic diagram of a front structure of an elastic bare board according to an exemplary embodiment of the present disclosure.

FIG. 4( b ) is a schematic diagram of the fabrication of an elastic spacer according to an exemplary embodiment of the present disclosure.

FIG. 4( c ) is a schematic diagram of a front structure of a carrier board according to an exemplary embodiment of the present disclosure.

FIG. 4(d) is a schematic diagram of the front structure of the carrier plate and the elastic spacer according to an exemplary embodiment of the present disclosure.

FIG. 4(e) is a schematic diagram of the fabrication of an elastic spacer according to another exemplary embodiment of the present disclosure.

FIG. 5 is a schematic structural diagram of a semiconductor package structure with a support plate provided according to an exemplary embodiment of the present disclosure.

FIG. 6 is a schematic diagram of disposing a protective layer on a wafer surface and dicing the wafer according to an exemplary embodiment of the present disclosure.

FIG. 7 is a schematic structural diagram of a semiconductor package structure provided with an opening in a protective layer according to an exemplary embodiment of the present disclosure.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention belongs. Words like "a" or "an" used in the specification and claims of this application also do not denote a quantitative limitation, but rather denote the presence of at least one. "Plurality" means two or more. Words like "include" or "include" mean that the elements or items appearing before "including" or "including" cover the elements or items listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Words like "upper" and/or "lower" are for convenience of description and are not limited to one position or one spatial orientation. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

In the packaging process, after the front side of the chip is mounted on the carrier board, when the back side of the chip is encapsulated, it is usually necessary to form an encapsulation layer by high pressure and high temperature molding (ie, hot compression molding). The molded product after compression molding is prone to warpage, which makes the chip deviate from the predetermined bonding position and affects the later wiring process. Please refer to FIG. 1( a ) and FIG. 1( b ), the inventor(s) found through research that for panel-level packaging, in the thermoforming process, due to the The difference between the thermal expansion coefficients, in the process of heating and cooling, the expansion and contraction of the carrier plate and the encapsulation material are different; and the encapsulation material that is formed, that is, the encapsulation layer 204, is rapidly heated at room temperature during the hot pressing process. During the rapid heating up to the hot pressing temperature, and in the subsequent cooling process, a large amount of force F (as shown in Figure 1(a)) is accumulated inside the material, causing the molded product to warp ( As shown in Figure 1(b)). Due to the warpage phenomenon, it is difficult to locate the precise position of the chip 201 in the carrier board 200 in the subsequent wiring process, which greatly affects the wiring process and even makes the wiring process difficult. In particular, in a large-scale carrier, due to the large size of the carrier, even a slight warpage of the carrier will cause the chips 201 in the outer and surrounding parts of the carrier 200 to be far away from the center relative to before molding. Position changes for larger sizes. Therefore, in the large-scale carrier board packaging process, solving the warpage problem of molding has become one of the keys to the entire process. The warpage problem even limits the enlarged development of the carrier board size and becomes a technical barrier in large-size carrier board packaging.

In order to solve the above problems in the panel level packaging process, the present application provides a semiconductor packaging method. During the packaging process, a plurality of mounting areas and blank areas are divided on the carrier board, the blank areas are located between at least two adjacent mounting areas, and multiple chips to be packaged are mounted on the multiple mounting areas. The packaging area is installed, and elastic spacers are arranged in the blank area; wherein, the front surfaces of the plurality of chips to be packaged face the carrier board; the chips to be packaged are packaged on the carrier board to form an encapsulation layer, that is, a package layer. The encapsulation layer covers the carrier board and encapsulates the plurality of chips to be packaged and the elastic spacer. In the above-mentioned embodiments of the present disclosure, through the provision of elastic spacers, elastic spacers are provided in the larger-area panel formed by the encapsulation layer that encapsulates the mounting area and the blank area, so that the entire larger-area panel can be provided with elastic spacers. It has good elasticity, thereby reducing the warpage of the encapsulation layer and the entire plastic encapsulation product, ensuring the positioning of the bare chip, and ensuring the success rate of packaging and product yield.

As shown in FIG. 2, FIG. 3(a)-FIG. 3(g), FIG. 4(a)-FIG. 4(e), FIG. 5, FIG. 6 and FIG. 7, the present disclosure provides a semiconductor packaging method and semiconductor package structure.

FIG. 2 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in FIG. 2, the semiconductor packaging method includes the following steps 101 and 102:

In step 101, a plurality of mounting areas and blank areas are divided on the carrier board, the blank areas are located between at least two adjacent mounting areas, and multiple chips to be packaged are mounted on the multiple mounting areas A mounting area is provided, and an elastic spacer is arranged in the blank area; wherein, the front surfaces of the plurality of chips to be packaged face the carrier board.

In one embodiment, the shape of the carrier board 200 may include: a circle, a rectangle or other shapes, and the shape of the carrier board 200 in this embodiment is a rectangle. The carrier plate 200 may be a large-sized stainless steel plate, a polymer substrate, or the like. The front side of the chip to be packaged 201 faces the carrier board 200 .

As shown in FIG. 3( a ), the carrier board 200 is divided into four mounting areas 2001 and blank areas 2002 . The blank area 2002 includes a part extending laterally and another part extending longitudinally, and the partial blank area extending laterally and the partial blank area extending longitudinally together divide the carrier board 200 into four mounting areas.

As shown in FIG. 3( b ), the elastic spacer 300 is placed on the blank area 2002 on the carrier board 200 . The elastic spacer 300 includes a first spacer 302 extending along the width direction of the carrier board 200 (ie, longitudinally extending) and The second isolation portion 301 extends along the length direction of the carrier board 200 (ie, extends laterally). Wherein, the first isolation portion 302 and the second isolation portion 301 of the elastic spacer are cross-connected. Thus, the elastic spacer 300 divides the area on the carrier board 200 into four small areas (ie, the mounting area 2001 ) by the first spacer 302 and the second spacer 301 .

The length of the first isolation portion 302 and the width of the carrier board 200 may be approximately the same, and the length of the second isolation portion 301 may be approximately the same as the length of the carrier board 200 . In this way, the elastic spacer 300 can divide the large area on the carrier board 200 into 4 small areas (ie, placement areas) that are independent of each other.

The widths of the first isolation portion 302 and the second isolation portion 301 of the elastic isolation member 300 can be adjusted according to different requirements. In some embodiments, the widths of the first isolation portion 302 and the second isolation portion 301 of the elastic isolation member 300 are both less than 25 mm.

As shown in FIGS. 3( c ) and 3 ( d ), in one embodiment, an adhesive layer 203 is provided on the carrier board 200 to attach the chips 201 to be packaged (a plurality of chips to be packaged) are attached Mounting area 2001 mounted on carrier board 200 . Correspondingly, the elastic spacer 300 is also disposed on the blank area 2002 formed by the two adjacent mounting areas 2001 on the carrier board 200 through the adhesive layer 203 . The chip to be packaged 201 and the elastic spacer 300 are disposed on the carrier board 200 through the adhesive layer 203 so as to be more firmly attached to the carrier board.

The adhesive layer 203 can be made of an easily peelable material, so as to separate the carrier board 200 and the chip to be packaged 201 encapsulated on the back side, for example, a thermal separation material that can lose its adhesiveness by heating can be used.

In some optional embodiments, the adhesive layer 203 may adopt a two-layer structure, a thermal separation material layer and a chip attach layer. The thermal separation material layer is pasted on the carrier board 200 and loses its viscosity when heated, so that it can be removed from the carrier board. 200 is peeled off, and the chip attach layer adopts an adhesive material layer, which can be used to stick the chip 201 to be packaged. After the chip 201 to be packaged is peeled off from the carrier board 200 , the chip attach layer on the chip 201 can be removed by chemical cleaning. In one embodiment, the adhesive layer 203 may be formed on the carrier board 200 by means of lamination, printing or the like.

In one embodiment, as shown in FIG. 3( e ), the carrier board 200 is pre-set with a sticking position for the chip 201 to be packaged. After the adhesive layer 203 is formed, the front side of the chip 201 to be packaged is pasted toward the carrier board 200 . at a predetermined position B of the carrier plate 200 . In one embodiment, before the adhesive layer 203 is formed, the adhesive position of the chip to be packaged can be pre-marked on the carrier board 200 by means of laser, mechanical drawing, photolithography, etc., and at the same time, the chip to be packaged 201 is also provided with The alignment mark is aimed for alignment with the pasting position on the carrier board 200 when pasting. It can be understood that, in one packaging process, there may be multiple chips 201 to be packaged, that is, multiple chips 201 to be packaged are mounted on the carrier board 200 at the same time for packaging, and after the packaging is completed, they are cut into multiple packages. A package body can include one or more chips to be packaged, and the positions of the multiple chips to be packaged can be freely set according to the needs of the actual product.

Correspondingly, in the actual processing process, the placement position of the elastic spacer 300 may be pre-marked on the carrier board 200 by using laser, mechanical engraving, photolithography, or the like. At the same time, the elastic spacer 300 is also provided with an alignment mark, so as to be aligned with the placement position on the carrier board 200 when placed.

In step 102, an encapsulation layer is formed, the encapsulation layer covers the carrier board, and the encapsulation layer is used to encapsulate the plurality of chips to be packaged and the elastic spacer.

The encapsulation layer 204 can be formed by laminating epoxy resin film or ABF (Ajinomoto buildup film), or by performing injection molding, compression molding or transfer molding on epoxy resin compounds. Transfer molding).

In some embodiments, for the exposed carrier 200 with the adhesive layer 203 formed thereon, the encapsulation layer 204 is formed on the backside of the chip 201 to be packaged and the exposed adhesive layer 203 . In addition, the encapsulation layer covers the blank area corresponding to the elastic spacer 300 and the mounting area where the chip to be packaged 201 is mounted. In order to reconfigure a flat panel structure, after the carrier board 200 is peeled off, rewiring and packaging can be continued on the reconfigured flat panel structure. Specifically, as shown in FIG. 3( f ), the encapsulation layer 204 covers the backside of the chip 201 to be encapsulated, the elastic spacer 300 and the entire area on the exposed adhesive layer 203 . In this way, elastic spacers are provided in the large-area panel formed by the encapsulation layer encapsulating the mounting area and the blank area, so that the entire large-area panel has good elasticity, thereby reducing the encapsulation layer and the entire panel. The degree of warpage of the molded product.

The encapsulation layer 204 includes a first surface 2041 opposite to the carrier 200 . The first surface 2041 is substantially flat and parallel to the surface of the carrier board 200 . The thickness of the encapsulation layer 204 can be reduced by grinding or polishing the first surface 2041,

In one embodiment, the thickness of the elastic spacer 300 is smaller than the thickness of the encapsulation layer 204 . The inventor(s) found through a large number of experiments that when the thickness of the elastic spacer 300 is too thin, the elasticity of the overall panel will be small, and the effect of eliminating warpage is not good. However, when the thickness of the elastic spacer 300 is too thick, the thickness of the encapsulation layer above the surface of the elastic spacer 300 will be too thin, which is not enough to connect the small units of each mounting area together, and it is easy to split the entire large panel into individual small units. unit. The inventor(s) found that, in some embodiments, when the thickness D1 of the elastic spacer 300 and the thickness D of the encapsulation layer 204 satisfy 0.4D<D1<0.9D, the warpage of the overall panel can be well eliminated, At the same time, it can also ensure that the panels are well connected and integrated, which facilitates subsequent operations on the entire panel.

For example, in an optional embodiment, the thickness D1 of the elastic spacer 300 and the thickness D of the encapsulation layer 204 satisfy D1=2/3D. Taking the thickness D of the encapsulation layer as 900 μm as an example, the thickness D1 of the elastic spacer 300 may be 600 μm. Accordingly, the encapsulation layer thickness D2 above the surface of the elastic spacer 300 is 300 μm. At this time, since there is an encapsulation layer with a thickness D2 of 300 μm above the surface of the elastic spacer 300 , the encapsulation layer with a thickness D2 of 300 μm can connect the entire panel into one body, so that the panel can be integrated into one body for subsequent steps (such as transmitted, etc.). At the same time, the elasticity provided by the elastic spacer 300 with a certain thickness enables the entire panel to have a certain degree of elasticity, thereby reducing or even eliminating the warpage of the panel.

In some optional embodiments, taking the thickness D of the encapsulation layer as 900 μm as an example, the inventor(s) found that the thickness D1 of the elastic spacer 300 satisfies 400 μm≤D1≤800 μm, which can eliminate the warpage of the overall panel and All aspects of making the panel connection into one are well guaranteed. When the thickness of the elastic spacer is less than 400μm, the elasticity of the overall panel will not be enough to eliminate the warping phenomenon; when the thickness of the elastic spacer is greater than 800μm, the thickness of the encapsulation layer above the surface of the elastic spacer will be too thin, which is easy to Splitting the entire large panel into small units is not conducive to subsequent operations on the panel.

As shown in FIG. 3( g ), after forming the encapsulation layer 204 in step 102 , the method includes peeling off the carrier to expose the front surfaces of the plurality of chips 201 to be encapsulated.

The carrier plate 200 can be directly mechanically peeled off. If the adhesive layer 203 between the carrier 200 and the front side of the chip 201 to be packaged has a thermal separation material, the thermal separation material on the adhesive layer 203 can be heated to reduce the viscosity after being heated, and then peel off. carrier board 200 . After the carrier board 200 is peeled off, the lower surface of the encapsulation layer 203 facing the carrier board 200 and the front surface of the chip 201 to be packaged are exposed. After peeling off the carrier board 200 , a flat plate structure including the chip 201 to be packaged and the encapsulation layer 204 encapsulating the back of the chip 201 to be packaged is obtained. On the above-mentioned flat plate structure formed, rewiring and the like can be performed according to the actual situation.

In some optional embodiments, the material used for the elastic spacer 300 includes silicone rubber. Silicone rubber material has a small Young's modulus and good elasticity. In addition, the heat resistance of the silicone rubber is very good, so that the elastic separator with the silicone rubber will not be affected in the process of forming the encapsulation layer by hot pressing. Of course, in some other embodiments, the elastic isolation member may also be an elastic structural member formed of other elastic materials or an elastic structural member comprising other materials.

Before placing the elastic spacer 300 on the blank area 2002 on the carrier board 200 , the elastic spacer 300 may be fabricated in a manner similar to the manner in which the encapsulation layer 204 is formed. A similar or the same thermoforming device can be used to prepare a blank elastic bare board 303 with corresponding thermocompression parameters. After the elastic bare board 303 is cured, the elastic bare board 303 is cut into a desired shape. Specifically, the manufacturing method of the elastic spacer 300 is as follows:

Hot-press forming the elastic bare board 303, as shown in FIG. 4(a);

The elastic bare board 303 is trimmed, and the trimmed area corresponds to the mounting area 2001 on the carrier board 200 .

Taking the mounting area 2001 as the four shown in FIG. 3( a ) and FIG. 3( b ) as an example, as shown in FIG. That is, there are four blank areas 304 in FIG. 4( b ), and the blank areas 304 correspond to the mounting area 2001 on the carrier board 200 , so that the elastic spacer 300 is used to divide the plastic sealing area of the entire carrier board 200 into four Small placement area 2001.

Further, the shape of the elastic spacer 300 and its layout on the whole carrier board 200 can be designed according to the specific size of the carrier board 200 and the specific partition arrangement of the carrier board 200 . For example, the elastic spacer 300 may be a strip-shaped structure extending in one direction (ie, may be a strip-shaped spacer extending in one direction). Of course, the elastic spacer 300 may also be a structural member composed of two or more spacers. In some embodiments, the elastic spacer 300 may include more structural members formed by crossing spacers extending in different directions. For example, as shown in FIGS. 4( c ) and 4 ( d ), the carrier plate 200 is larger or needs to be divided When there are six mounting areas as shown in FIG. 4( c ), the elastic spacers 300 can be correspondingly arranged as shown in FIG. 4( d ) including a second spacer 301 extending laterally and two first Isolation part 302 . Correspondingly, the elastic spacer 300 shown in 4(d) can be manufactured with reference to FIG. 4(e) in combination with FIG. 4(a). For the manufacturing method thereof, reference may be made to the relevant descriptions of the embodiments shown in 4(a) and 4(b) above, which will not be repeated here. In other embodiments, the elastic spacer includes a plurality of spacers. At least two of the plurality of isolation portions are cross-connected, and at least one of the isolation portions extends in a direction deviating from the width direction of the carrier plate and deviating from the length direction of the carrier plate. This application does not limit this, and can be set according to a specific application environment.

Further, optionally, after the above step 102 and before peeling off the carrier board 200 , the packaging method further includes mounting a support board 205 on the first surface 2041 of the encapsulation layer 204 away from the carrier board.

The support plate is mounted on at least part of the first surface of the encapsulation layer. As shown in FIG. 5 , in one embodiment, the support plate 205 is mounted on the first surface 2041 of the encapsulation layer 204 , and the support plate 205 covers the entire area of the first surface 2041 of the encapsulation layer 204 .

The material strength of the support plate 205 is greater than that of the encapsulation layer 204, so that the support plate 205 can effectively improve and ensure the mechanical strength of the encapsulation structure during the encapsulation process, effectively suppress the adverse effects caused by the deformation of each structure, thereby improving the product packaging. Effect.

Correspondingly, in this embodiment, the carrier board 200 may be peeled off after the support board 205 is mounted to expose the front surfaces of the plurality of chips 201 to be packaged.

In some embodiments, before step 101 , that is, before the chip to be packaged is mounted on the carrier, a protective layer may be formed on the front surface of the chip to be packaged. The protective layer can be formed on the front surface of the semiconductor wafer before cutting the semiconductor wafer into a plurality of chips to be packaged, and then the semiconductor wafer is cut to obtain chips to be packaged with the protective layer formed on the front surface. Of course, it can be understood that, if the process allows, after the semiconductor wafer is cut into chips to be packaged, a protective layer can be formed on the front side of each chip to be packaged, which is selected according to the actual situation.

As shown in FIG. 6 , a protective layer 202 is formed on the front surface of the semiconductor wafer 100 , that is, the surface corresponding to the front surface of the chip 201 to be packaged, and then the semiconductor wafer 100 on which the protective layer 202 is formed is cut along the dicing lane to obtain A plurality of chips to be packaged 201 formed with protective layers. The chip 201 to be packaged with the protective layer 202 formed on the front side can also be mounted on the carrier board 200 through the adhesive layer 203 .

The protective layer 202 is made of insulating materials, such as polyimide, epoxy resin, ABF (Ajinomoto buildup film), and PBO (Polybenzoxazole). Optionally, the material of the protective layer is selected to be insulating and capable of adapting to chemical cleaning, grinding and the like. The protective layer may be formed on the semiconductor wafer by means of lamination, coating, printing, or the like.

When the encapsulation layer 204 is used for encapsulation, since the encapsulation layer needs high pressure molding during molding, the encapsulation material easily penetrates between the carrier board 200 and the chip to be packaged 201 during the process. By forming a protective layer 202 outside the chip 201 to be packaged, the protective layer 202 can prevent the encapsulation material from penetrating into the surface of the chip 201 to be encapsulated, and even if the encapsulating material penetrates, after peeling off from the carrier, it can also be chemically Alternatively, the surface of the protective layer 202 can be directly processed by grinding without directly contacting the front surface of the chip 201 to be packaged, so that the circuit structure on the front surface of the chip 201 to be packaged cannot be damaged.

Further, in the embodiment in which the protective layer 202 is formed on the front surface of the chip 201 to be packaged, after the carrier board 200 is peeled off, the protective layer 202 is correspondingly exposed.

In the embodiment in which the protective layer 202 is formed on the front surface of the chip 201 to be packaged, the carrier board 200 can also be directly mechanically peeled off. If the adhesive layer 203 between the carrier plate 200 and the protective layer 202 has a thermal separation material, the thermal separation material on the adhesive layer 203 can be heated to reduce the viscosity after being heated, and then the carrier plate 200 can be peeled off. . After the carrier board 200 is peeled off, the lower surface of the encapsulation layer 203 and the protective layer 202 facing the carrier board 200 are exposed. After peeling off the carrier board 200 , a flat plate structure including the chip to be packaged 201 , a protective layer 202 covering the front side of the chip to be packaged 201 , and an encapsulation layer 204 encapsulating the back side of the chip to be packaged 201 is obtained. On the above-mentioned flat plate structure formed, rewiring and the like can be performed according to the actual situation.

In the embodiment of the present disclosure, after the carrier board 200 is peeled off, the surfaces of the protective layer 202 and the encapsulation layer 204 are exposed. At this time, the chip attach layer in the adhesive layer 203 also exists on the surfaces of the protective layer 202 and the encapsulation layer 204 , and when chemically removed, the protective layer 202 can also protect the surface of the chip to be encapsulated from damage; after the adhesive layer is completely removed, if the encapsulation material has penetrated before, chemical cleaning or grinding can be used to make the surface Flatness is beneficial for subsequent wiring; and if there is no protective layer, the surface of the chip to be packaged cannot be treated by chemical methods or grinding methods, so as not to damage the circuit on the front side of the chip to be packaged.

Further, as shown in FIG. 7 , in the embodiment in which the protective layer 202 is formed on the front side of the chip 201 to be packaged, the support plate 205 is not provided on the encapsulation layer 204 as an example for illustration. The embodiment in which the support plate 205 is provided on the layer 204 is also applicable. After peeling off the carrier board 200 , protective layer openings 2021 may be formed on the protective layer 202 at positions corresponding to the bonding pads of the plurality of chips to be packaged 201 , and each protective layer opening 2021 is at least corresponding to the chips to be packaged. The bonding pads of the chip 201 or the lines drawn from the bonding pads are exposed, so that the bonding pads on the front side of the chip 201 to be packaged or the lines drawn from the bonding pads are exposed from the protective layer opening 2021 . If the protective layer material is a laser reactive material, laser patterning can be used to form one protective layer opening 2021 at a time; if the protective layer material is a photosensitive material, photolithography patterning can be used to form multiple openings at a time The opening method of the protective layer opening 2021 . The shape of the protective layer opening 2021 can be round, and of course can also be other shapes such as oval, square, line and so on.

Further, after the protective layer opening 2021 is formed, rewiring may be performed on the protective layer 202 of the chip 201 to be packaged, that is, a rewiring structure is formed.

In this embodiment, the front side of the chip to be packaged 201 has solder pads for the internal circuits of the chip, and these solder pads can be drawn out by re-wiring on the front side of the chip to be packaged 201 . The redistribution structure may include a first redistribution layer formed on the protective layer 202 and the exposed encapsulation layer 204 and electrically connected to the pads of the chip 201 through the protective layer opening 2021 .

The redistribution structure may further include a front encapsulation layer formed on the first redistribution layer and the exposed protective layer 202 and the encapsulation layer 204, and the front encapsulation layer has an opening. Conductive bumps electrically connected to the first redistribution layer are provided in the opening to lead out the bonding pads on the front side of the chip 201 .

Further, in one embodiment, repeated rewiring can be performed on the front side of the chip 201 , for example, a second rewiring layer or more rewiring layers can be formed outside the front surface encapsulation layer in the same way to realize multi-layer products. Rewire.

It should be noted that, when the to-be-packaged chip 201 is packaged, re-wiring may be performed on the front surface of the to-be-packaged chip 201 after peeling off the carrier board 200 to form a re-wiring structure. Of course, before the chip to be packaged 201 is mounted on the carrier board 200 , rewiring can also be performed on the front surface of the chip to be packaged 201 to form a rewiring structure. The redistribution structure may also include one or more redistribution layers. Furthermore, in the embodiment in which the front surface of the chip to be packaged 201 is provided with a protective layer or has no protective layer, rewiring can be performed before the chip to be packaged 201 is mounted on the carrier board. For specific operations related to rewiring, reference may be made to the above related descriptions, which will not be repeated here.

Further, it should be noted that when multiple chips 201 to be packaged are packaged together, after the packaging is completed, the entire package structure can be cut into multiple packages by laser or mechanical cutting to form a package structure with a single chip.

In this application, the apparatus embodiments and the method embodiments may complement each other without conflict.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the present application. within the scope of protection.

Claims (12)

1. A semiconductor packaging method, comprising:

dividing a plurality of mounting areas and a blank area on a carrier plate, wherein the blank area is positioned between at least two adjacent mounting areas, mounting a plurality of chips to be packaged in the mounting areas, and arranging an elastic isolation piece in the blank area; the front surfaces of the chips to be packaged face the carrier plate;

and forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and is used for encapsulating the plurality of chips to be encapsulated and the elastic separator.

2. The semiconductor packaging method of claim 1, wherein the material of the elastomeric isolator comprises silicone rubber.

3. The semiconductor packaging method of claim 1, wherein a thickness of the elastomeric separator is less than a thickness of the encapsulation layer.

4. The semiconductor packaging method according to claim 3, wherein a thickness D1 of the elastic separator and a thickness D of the encapsulation layer satisfy: 0.4D < D1 < 0.9D.

5. The semiconductor packaging method according to claim 4, wherein a thickness D1 of the elastic separator and a thickness D of the encapsulation layer satisfy: d1 ═ 2/3D.

6. The semiconductor packaging method according to claim 3, wherein a thickness D1 of the elastic spacer satisfies: d1 is more than or equal to 400 mu m and less than or equal to 800 mu m.

7. The semiconductor packaging method according to claim 1, wherein the elastic spacer includes a bar-shaped spacer portion extending in one direction; or the like, or, alternatively,

the elastomeric isolator includes a plurality of isolators.

8. The semiconductor packaging method according to claim 7, wherein when the elastic spacer includes a plurality of spacers, the elastic spacer includes a first spacer extending along a width direction of the carrier board and a second spacer extending along a length direction of the carrier board, the first spacer and the second spacer of the elastic spacer are cross-connected, and a length of the first spacer is the same as a width of the carrier board and a length of the second spacer is the same as a length of the carrier board.

9. The semiconductor packaging method of claim 7, wherein when the elastic isolator comprises a plurality of isolation portions, at least two of the isolation portions are cross-connected, and at least one isolation portion extends in a direction that is offset from a width direction of the carrier board and offset from a length direction of the carrier board.

10. The semiconductor packaging method of claim 1, wherein the method of making the elastomeric isolator comprises:

hot-pressing to form an elastic bare board;

and cutting the elastic bare board, wherein the cut area corresponds to the mounting area on the carrier board.

11. The semiconductor packaging method of any one of claims 1-10, wherein after forming the encapsulation layer, the method comprises:

stripping the carrier plate to expose the front surfaces of the chips to be packaged;

and forming a rewiring structure on the front surface of the chip, wherein the rewiring structure is used for leading out the welding pad on the front surface of the chip.

12. The method of claim 11, wherein after the forming the encapsulation layer and before the peeling the carrier, the method comprises attaching a support plate to a first surface of the encapsulation layer remote from the carrier;

after forming a rewiring structure on the front side of the chip, the method includes peeling off the support plate.

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