CN111668098A - Semiconductor packaging method - Google Patents
Semiconductor packaging method Download PDFInfo
- Publication number
- CN111668098A CN111668098A CN201910177319.4A CN201910177319A CN111668098A CN 111668098 A CN111668098 A CN 111668098A CN 201910177319 A CN201910177319 A CN 201910177319A CN 111668098 A CN111668098 A CN 111668098A
- Authority
- CN
- China
- Prior art keywords
- chip
- packaged
- layer
- front surface
- semiconductor packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000010410 layer Substances 0.000 claims abstract description 197
- 238000012545 processing Methods 0.000 claims abstract description 25
- 239000012790 adhesive layer Substances 0.000 claims abstract description 24
- 238000002161 passivation Methods 0.000 claims description 48
- 238000005538 encapsulation Methods 0.000 claims description 31
- 239000008393 encapsulating agent Substances 0.000 claims description 14
- 238000007789 sealing Methods 0.000 claims description 14
- 238000009832 plasma treatment Methods 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 12
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 description 11
- 230000002441 reversible effect Effects 0.000 description 10
- 238000012858 packaging process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The application provides a semiconductor packaging method. The semiconductor packaging method comprises the steps of processing the front surface of a chip to be packaged, and increasing the roughness of the front surface of the chip to be packaged; the chip to be packaged is attached to a carrier plate through an adhesive layer, and the front surface of the chip to be packaged faces the carrier plate; and packaging the chip to be packaged on the carrier plate to form a first packaging layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the front surface of the chip is bonded on a substrate wafer through an adhesive tape, wafer-level plastic package is carried out, the substrate wafer is peeled off, then re-wiring is carried out on the front surface of the chip, a re-wiring layer is formed, and packaging is carried out. However, the inventors found that the chip is easily moved during the packaging process, which adversely affects the chip package and thus the yield of the product.
Disclosure of Invention
One aspect of the present application provides a semiconductor packaging method, including: processing the front surface of the chip to be packaged, and increasing the roughness of the front surface of the chip to be packaged;
the chip to be packaged is attached to a carrier plate through an adhesive layer, and the front surface of the chip to be packaged faces the carrier plate;
and packaging the chip to be packaged on the carrier plate to form a first packaging layer.
Optionally, the processing the front surface of the chip to be packaged includes performing plasma processing on the front surface of the chip to be packaged.
Optionally, before the chip to be packaged is packaged on the carrier, the method includes:
and processing the back surface of the chip to be packaged, and increasing the roughness of the back surface of the chip to be packaged.
Optionally, the processing the back surface of the chip to be packaged includes performing plasma processing on the back surface of the chip to be packaged.
Optionally, when the front side or the back side of the chip to be packaged is subjected to plasma processing, oxygen is supplied to the plasma processing space.
Optionally, when the front side or the back side of the chip to be packaged is subjected to plasma treatment, the electric power used is 200W to 400W.
Optionally, the duration of performing plasma treatment on the front side or the back side of the chip to be packaged is 30S to 120S.
Optionally, the mounting of the chip to be packaged on the carrier through the bonding layer includes:
forming a bonding layer on the carrier plate;
and sticking the front surface of the chip to be packaged on the bonding layer.
Optionally, after forming the first encapsulation layer, the method includes:
stripping the carrier plate to expose the front surface of the chip to be packaged;
and re-wiring the front surface of the chip to be packaged.
Optionally, the rewiring on the front surface of the chip to be packaged includes:
forming a passivation layer on the front surface of the chip to be packaged and one side of the first packaging layer, which is positioned on the front surface of the chip to be packaged;
forming a passivation layer opening on the passivation layer, wherein the passivation layer opening is positioned at a welding pad of the chip to be packaged;
and forming a rewiring layer on the passivation layer, wherein the rewiring layer is electrically connected with the welding pad on the chip to be packaged through the opening of the passivation layer.
Optionally, a redistribution layer is formed on the passivation layer, and the method further includes: and forming a second packaging layer on the rewiring layer, and leading out a welding pad or a connection point of the rewiring layer through the conductive convex column.
Optionally, after the forming of the first encapsulation layer and before the peeling of the carrier plate, the method includes:
and forming a fixed sealing layer on the first surface of the first packaging layer far away from the carrier plate.
Optionally, after forming the second encapsulation layer, the method includes:
and stripping the sealing layer.
According to the semiconductor packaging method provided by the embodiment of the application, the contact area between the front surface of the chip and the bonding layer is increased by processing the front surface of the chip, so that the bonding force between the front surface of the chip and the bonding layer is increased, the chip is prevented from moving in the packaging process, the chip is particularly favorable for being prevented from moving due to the fact that the viscosity of the bonding layer is reduced in the packaging process, and the packaging success rate and the product yield are guaranteed.
Drawings
Fig. 1 is a flow chart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure;
2(a) -2 (k) are process flow diagrams of a method of semiconductor packaging according to an exemplary embodiment of the present disclosure;
fig. 3 is a schematic diagram of a front structure of a carrier according to an exemplary embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a semiconductor package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
In the packaging process, after the front surface of the chip to be packaged is attached to the carrier plate through the bonding layer, the back surface of the chip to be packaged is packaged to form a packaging layer. The inventor(s) further researches and discovers that during the process of encapsulating the encapsulation layer material, the viscosity of the bonding layer is reduced due to the temperature rise, and further during the hot press molding process, the pressure of the molding material on the die is large, so that the chip is easy to move, the subsequent packaging of the chip is affected, and the yield of products is affected.
According to various embodiments of the present disclosure, a semiconductor packaging method is provided. In the packaging process, the front side of a chip to be packaged is processed, and then the processed chip to be packaged is attached to the carrier plate through the bonding layer, wherein the front side of the chip to be packaged faces the carrier plate, and the back side of the chip to be packaged faces upwards, namely faces outwards relative to the carrier plate; and forming a first packaging layer to cover the chip to be packaged and the carrier plate. And after the encapsulation is finished, peeling off the carrier plate, namely removing the carrier plate to expose the front surface of the chip to be encapsulated and the first encapsulation layer. This above-mentioned embodiment of this disclosure, through handling the front of treating the encapsulation chip, increase treat after the positive roughness of encapsulation chip, will treat that comparatively crude front subsides of encapsulation chip locate the tie coat, thereby the subsides are adorned on the support plate, later when treating again and form first envelope on the encapsulation chip, make treat that the encapsulation chip can with the more firm combination of tie coat, thereby firmly fix on the support plate, avoid producing relative displacement between encapsulation in-process chip and tie coat, especially can avoid because the tie coat moves at the chip that its viscosity descends and lead to when the temperature risees, and can avoid treating the removal of encapsulation chip at first envelope hot briquetting's in-process, thereby guarantee the success rate of encapsulation and the yield of product.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. Please refer to fig. 1, and also refer to fig. 2(a) to fig. 4 as necessary. As shown in fig. 1, the semiconductor packaging method includes the following steps 101-103. Wherein:
in step 101, the front surface of the chip to be packaged is processed, and the roughness of the front surface of the chip to be packaged is increased.
In an embodiment, the to-be-packaged chips are formed by thinning and cutting a semiconductor wafer, each semiconductor wafer can form a plurality of to-be-packaged chips, cutting channels are formed among the to-be-packaged chips, and each semiconductor wafer is thinned and cut to form a plurality of chips. The front surface of the chip to be packaged is composed of conductive electrodes which are led out from a circuit inside the chip to the surface of the chip, and welding pads are prepared on the conductive electrodes.
In this embodiment, as shown in fig. 2(a), the front surface of the semiconductor wafer 100 is processed corresponding to the front surface 2011 of the chip 201 to be packaged, so as to increase the roughness of the front surface 201 of the chip to be packaged. The front surfaces of the chips to be packaged may be processed before the semiconductor wafer 100 is cut into the chips 201 to be packaged, the surfaces of the semiconductor wafer 100 where the front surfaces of the chips to be packaged are located may be processed, and then the semiconductor wafer 100 is cut, so as to obtain a plurality of chips to be packaged with rough front surfaces. Referring to fig. 2(c), after the front surface of the semiconductor wafer 100, i.e., the front surface corresponding to the chip 201 to be packaged, is processed, the semiconductor wafer 100 is cut along the dicing streets, so as to obtain a plurality of chips 201 to be packaged, the front surfaces of which are processed. It can be understood that, when the process allows, the front surface of the chip to be packaged may be processed on the front surface of each chip to be packaged after the semiconductor wafer is cut into the chips to be packaged, which is specifically selected according to the actual situation.
In some embodiments, processing the front side of the chip to be packaged includes plasma processing the front side of the chip to be packaged.
Specifically, the inventors(s) have found, through a great deal of experiments, that in some embodiments, when the front surface of the chip to be packaged is subjected to plasma treatment, oxygen or a gas combination of oxygen and other gases is supplied to the plasma treatment space, and the roughness of the front surface of the chip to be packaged obtained through treatment is better, so that the chip to be packaged can be more firmly bonded to the adhesive layer.
The inventor(s) have found through a great deal of experiments that when the front surface of the chip to be packaged is subjected to plasma treatment, the electric power used is 200-400W, and the roughness of the front surface of the chip to be packaged obtained through the treatment is better.
The inventor (S) have found through a large number of experiments that the time for performing plasma treatment on the front surface of the chip to be packaged is 30S to 120S, and the roughness of the front surface of the chip to be packaged obtained through the treatment is good.
The front face of the chip to be packaged is subjected to plasma treatment by adopting the process conditions, and the obtained roughness of the chip to be packaged can well ensure the contact area between the front face of the chip to be packaged and other structures, so that the adhesive force between the front face of the chip to be packaged and other structures is increased, the packaging quality is ensured, and the stability of a packaged product in the using process is favorably ensured.
Further, in some optional embodiments, please refer to fig. 2(b), the reverse side of the chip to be packaged (i.e., the reverse side of the chip to be packaged) may also be subjected to plasma treatment, i.e., the roughness of the reverse side of the chip to be packaged is increased, so as to increase the roughness of the reverse side of the chip, so that the adhesion between the reverse side of the chip and the packaging layer disposed thereon is increased, and the chip is not easily separated during the use process, thereby increasing the service life of the chip. Similarly, before the semiconductor wafer 100 is cut into a plurality of chips 201 to be packaged, the surface of the semiconductor wafer 100 where the reverse surfaces of the chips to be packaged are located is processed, and then the semiconductor wafer 100 is cut, so as to obtain a plurality of chips to be packaged with rough reverse surfaces. The processing of the back side of the chip to be packaged can be performed simultaneously with or simultaneously with the processing of the front side of the chip to be packaged.
And the processing of the reverse side of the chip to be packaged comprises the plasma processing of the reverse side of the chip to be packaged. And the process conditions adopted when the back surface of the chip to be packaged is subjected to plasma treatment can be the same as the process conditions adopted when the front surface of the chip to be packaged is subjected to plasma treatment. Of course, the process conditions of the two may also be different, which is not limited in this application and may be set according to the specific application environment.
It should be noted that, the front side or the back side of the chip to be packaged is subjected to plasma treatment, and impurities on the surface of the chip to be packaged can be removed, so that the chip to be packaged, the bonding layer and other structures cannot be affected by the impurities, and bonding can be performed more closely.
It should be noted that, for convenience of drawing, in fig. 2(c) and subsequent figures, the roughness of the surface (including at least one of the front surface and the back surface) of the chip to be packaged after being processed is not shown, but in the embodiments of the present application, it should be understood that the surface of the chip to be packaged is rough after being processed, and is especially rough compared to the surface before being processed.
In step 102, the chip to be packaged is attached to a carrier through an adhesive layer, and the front surface of the chip to be packaged faces the carrier.
As shown in fig. 2(e), the processed chip 201 to be packaged (a plurality of chips to be packaged are shown in the figure) and the carrier board 200 are connected by the adhesive layer 203, and the front surface of the chip 201 to be packaged directly contacts with the adhesive layer 203.
In an embodiment, the shape of the carrier 200 may include: circular, rectangular, or other shapes, and the shape of the carrier plate 200 is not limited by the present disclosure. The carrier 200 may be a small-sized wafer substrate, or may be a larger-sized carrier, such as a stainless steel plate, a polymer substrate, etc.
As shown in fig. 2(c), in an embodiment, an adhesive layer 203 is first disposed on the carrier 200 for adhering the processed chip 201 to be packaged. And the adhesive layer 203 may be made of a material that is easily peeled off so as to peel off the carrier board 200 and the chip 201 to be packaged that is packaged on the back side, for example, a thermal release material that can be heated to lose its adhesiveness. In one embodiment, the adhesive layer 203 may be formed on the carrier 200 by lamination, printing, or the like. Of course, if the process allows, an adhesive layer may be disposed on the front surface of the processed chip 201 to be packaged, and the front surface of the chip 201 to be packaged, on which the adhesive layer is disposed, may be attached to the carrier plate toward the carrier plate. The present application is not limited to this, and may be set according to a specific application environment.
In an embodiment, as shown in fig. 3, a bonding position of the chip 201 to be packaged is preset on the carrier 200, and after the adhesive layer 203 is formed, the front surface of the chip 201 to be packaged is bonded at a predetermined position a of the carrier 200 toward the carrier 200. In an embodiment, before the adhesive layer 203 is formed, a bonding position of the chip to be packaged may be identified in advance on the carrier 200 by using laser, mechanical patterning, photolithography, and the like, and the chip 201 to be packaged is also provided with an alignment mark to align with the bonding position on the carrier 200 during bonding. It should be noted that the adhesive layer is generally transparent so as to be able to clearly see the alignment mark provided on the chip 201 to be packaged, and to be able to accurately attach the chip 201 to be packaged at the predetermined position a. It can be understood that, in one packaging process, a plurality of chips 201 to be packaged may be provided, that is, a plurality of chips 201 to be packaged are simultaneously mounted on the carrier 200, packaged, and cut into a plurality of packages after the packaging is completed; one package may include one or more chips, and the positions of the chips may be freely set according to the needs of an actual product.
In step 103, the chip to be packaged is packaged on the carrier to form a first package layer.
A first encapsulating layer 204 is formed on the back surface of the chip 201 to be packaged and the exposed carrier 200. The first encapsulating layer 204 is used to completely encapsulate the exposed carrier 200 and the chip 201 to be packaged. In some embodiments, for the exposed carrier 200 with the adhesive layer 203 thereon, the first encapsulating layer 204 is formed on the back surface of the chip 201 to be packaged and the exposed adhesive layer 203, and the first encapsulating layer 204 is used to completely encapsulate the adhesive layer 203 and the chip 201 to be packaged. As shown in fig. 2 (f). The first encapsulating layer 204 is used to completely encapsulate the adhesive layer 203 disposed on the carrier 200 and the chip 201 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 200 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure.
In an embodiment, the first encapsulation layer 204 may be formed by laminating an epoxy resin film or abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound. The first encapsulant layer 204 includes a first surface 2041 opposite to the carrier 200, and is substantially flat and parallel or substantially parallel to the surface of the first carrier 200. The thickness of the first encapsulant layer 204 may be reduced by grinding or polishing the first surface 2041, and in an embodiment, the thickness of the first encapsulant layer 204 may be reduced to the back side of the chip 201 to be packaged.
In the encapsulation with the first encapsulating layer 204, since the first encapsulating layer needs to be heat-press-molded at the time of molding, the adhesive layer is lowered in viscosity by heat in this process. By processing the front surface of the chip 201 to be packaged according to the embodiment of the disclosure, the front surface of the chip 201 to be packaged and the adhesive layer 203 are bonded more firmly, so that the chip 201 to be packaged can be firmly fixed on a carrier plate (for example, a predetermined position of the carrier plate), and the chip 201 to be packaged does not move in the process of thermocompression molding. In addition, for the chip to be packaged whose reverse side is also processed, the bonding between the chip to be packaged and the first encapsulating layer is also tighter (i.e. the interface bonding force between the chip to be packaged formed by the inorganic material and the first encapsulating layer formed by the organic material becomes stronger), so that the chip 201 to be packaged is firmly embedded in the encapsulating layer (including the encapsulating layer of the first encapsulating layer) and is not easily separated from the encapsulating layer in the using process of the semiconductor product, thereby prolonging the service life of the chip.
It should be noted that, for the embodiment that needs to process the back surface of the chip 201 to be packaged, it is only necessary to process the back surface of the chip 201 to be packaged before performing step 103.
Further, optionally, after step 103, the packaging method further includes forming a seal layer 205 on a first surface of the first encapsulation layer away from the carrier.
The sealing layer is at least formed on at least partial area of the first surface of the first packaging layer. As shown in fig. 2(g), in an embodiment, a sealing layer is formed on the first surface 2041 of the first sealing layer 204, and the sealing layer 205 is shown covering the entire area of the first surface 2041 of the first sealing layer 204.
In some embodiments, the seal may be formed by Spraying (Spraying), Printing (Printing), Coating (Coating), and the like. The material strength of the sealing layer is greater than that of the first sealing layer, so that the sealing layer can effectively improve and guarantee the mechanical strength of the packaging structure in the packaging process, and the adverse effect caused by the deformation of each structure is effectively inhibited, thereby improving the packaging effect of the product.
Further, in an embodiment, after the forming of the encapsulating layer, the packaging method further includes peeling off the carrier to expose the front surface of the chip 201 to be packaged.
In one embodiment, as shown in fig. 2(h), the carrier 200 can be peeled off directly and mechanically. If the adhesive layer 203 between the carrier board 200 and the chip 201 has a thermal separation material, the thermal separation material on the adhesive layer 203 may be heated to reduce its viscosity after being heated, so as to peel off the carrier board 200. After the carrier 200 is peeled off, the lower surface of the first encapsulant layer 204 facing the carrier 200 and the front surface of the chip 201 are exposed. After the carrier 200 is peeled off, a flat structure including the chip 201 to be packaged and the first encapsulation layer 204 encapsulating the back surface of the chip 201 to be packaged is obtained.
In the embodiment without the encapsulating layer, after step S103, the carrier is peeled off to expose the front surface of the chip 201 to be packaged and the lower surface of the first encapsulating layer. The specific stripping method can be referred to the above description, and is not repeated herein.
Further, a rewiring layer is formed on the exposed front surface of the chip 201 to be packaged.
In this embodiment, the front surface of the chip 201 to be packaged has pads of the internal circuit of the chip, and the pads can be led out by re-wiring on the front surface of the chip 201 to be packaged.
The formed flat plate structure may be subjected to rewiring or the like according to actual conditions.
For example, in some embodiments, the rewiring may be performed directly on the planar structure described above.
In other embodiments, the passivation layer may be disposed on the flat plate structure, and the redistribution layer may be disposed on the passivation layer.
Specifically, after the carrier 200 is peeled off, a passivation layer 202 may be first formed on the front surface of the chip to be packaged 201 and a side of the first encapsulation layer on the front surface of the chip to be packaged (i.e., a lower surface of the first encapsulation layer).
The passivation layer 202 may be formed by Screen-printing (Screen-printing), spraying (spraying-coating), laminating (plating), or the like, using polyimide or polymer materials. Alternatively, the material of the passivation layer 202 may be cured using high temperature or ultraviolet rays.
Further, a passivation layer opening 2021 is formed on the passivation layer 202, and the passivation layer opening 2021 is located at a pad of the chip to be packaged. So that the pads on the front surface of the chip 201 to be packaged or the lines led out from the pads are exposed from the passivation layer opening 2021. If the passivation layer material is a laser reactive material, the openings may be opened by laser patterning one passivation opening 2021 at a time. If the passivation layer material is a photosensitive material, a plurality of passivation layer openings 2021 may be formed at a time by photolithography patterning.
The passivation layer opening 2021 may be circular in shape, but may be other shapes such as oval, square, linear, etc. In an alternative embodiment, as shown in fig. 2(i), a plurality of passivation layer openings 2021 are formed on the passivation layer 202, and the bonding pads on the chip are exposed from the passivation layer openings 2021.
In the embodiment of the disclosure, the passivation layer opening 2021 is formed on the passivation layer 202, so that the pad position on the front surface of the chip can be accurately positioned through the passivation layer opening 2021, and the problem of positioning deviation of the pad position of the chip is not worried about.
Further, a rewiring layer is formed on the passivation layer, and the rewiring layer is electrically connected with the welding pad on the chip to be packaged through the passivation layer opening.
In some embodiments, the rerouting layer includes a first rerouting layer 206. As shown in fig. 2(i), the first redistribution layer 206 is formed on the surface of the passivation layer 202, and is made of a conductive material, such as copper, nickel, gold, or other metal. The first redistribution layer 206 includes a connection portion 2061 filled in the passivation layer opening 2021 and a patterned wire 2062 formed on the lower surface of the passivation layer opening 2021, the connection portion 2061 is electrically connected to a pad on the surface of the chip 201 to be packaged, and the patterned wire 2062 is electrically connected to the connection portion 2061.
In one embodiment, after forming a first redistribution layer on the passivation layer, a second encapsulation layer 207 is formed on the first redistribution layer, and a pad or a connection point of the first redistribution layer is led out through the first conductive pillar 208. In one embodiment, as also shown in fig. 2(i), after the first redistribution layer 206 is formed, it is encapsulated with the second encapsulation layer 207. After the packaging is completed, the pads on the first redistribution layer 206 are extracted from the surface of the second encapsulation layer 207 through the first conductive posts 208 (e.g., metal posts or protruding pads).
Specifically, in an embodiment, the first conductive pillar 208 is formed on the patterned circuit of the first redistribution layer 206 by photolithography and electroplating, and then the second encapsulation layer 207 is formed. In another embodiment, a second encapsulation layer is formed on the first redistribution layer; forming an opening on the second encapsulation layer at a position corresponding to a pad or a connection point of the first redistribution layer, where the opening may be a first opening for convenience of description; a first conductive stud 208 is formed within the first opening. Of course, the first opening may not be filled, so that the bonding pad or the connection point of the first redistribution layer of the completed package is exposed from the first opening.
The shape of the first conductive stud 208 is preferably circular, but may be other shapes such as rectangle, square, etc., and the conductive stud 208 is electrically connected to the first redistribution layer.
In one embodiment, the second encapsulant layer 207 may be formed by Lamination (plating), Molding (Molding) or Printing (Printing), and preferably an epoxy compound is used. The second encapsulant layer 207 covers the first redistribution layer 206, and the first redistribution layer 206 is exposed from the surface of the second encapsulant layer 207 through the first conductive posts 208. When the first conductive posts 208 are formed first and then the second encapsulant layer 207 is formed for encapsulation, the second encapsulant layer 207 may cover all exposed surfaces of the first encapsulant layer 204, the passivation layer 202, and the first redistribution layer 206, and then be thinned to the surfaces of the first conductive posts 208.
Further, after forming the redistribution layer, the packaging method further includes peeling off the sealing layer 205. As shown in fig. 2 (j). The sealing layer 205 may be mechanically peeled off directly or by other methods, which is not limited in this application and may be set according to a specific application environment.
In an embodiment, in the case that a plurality of chips 201 to be packaged are packaged together, after the packaging of the first redistribution layer is completed, the whole package structure is cut into a plurality of packages by laser or mechanical cutting, as shown in fig. 2(k), and the structure diagram of the formed package is shown in fig. 4.
Further, in an optional embodiment, the redistribution layer further includes a second redistribution layer. Namely, the front side of the at least one chip to be packaged is subjected to a rewiring process to complete the packaging.
Specifically, a second redistribution layer (not shown) may be formed on the second encapsulation layer, and the second redistribution layer may be electrically connected to a pad or a connection point of the first redistribution layer through the first conductive pillar. And then, forming a third encapsulating layer on the second rewiring layer, wherein a second opening corresponding to the welding pad or the connecting point of the second rewiring layer is formed in the third encapsulating layer, and then a second conductive convex column capable of being electrically connected with the welding pad or the connecting point of the second rewiring layer is arranged in the second opening, so that the welding pad or the connecting point of the second rewiring layer is led out through the second conductive convex column. In this way, a multi-layer package structure can be realized.
Of course, after the second redistribution layer is formed on the second encapsulation layer, a second conductive pillar may also be formed on a pad or a connection point of the second redistribution layer; and forming a third encapsulating layer on the second rewiring layer and the exposed second encapsulating layer, and exposing the second conductive convex column.
The forming manner of the second redistribution layer is similar to that of the first redistribution layer, and specific details may be referred to the above description of the first redistribution layer, which is not repeated herein.
Fig. 4 is a schematic structural diagram of a chip package structure obtained by the semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 4 (optionally, in conjunction with fig. 2(i), 2(j) and 2 (k)), the semiconductor package structure includes:
a first encapsulation layer 204 provided with an inwardly concave cavity;
the chip 201 is arranged in the cavity, and the back surface of the chip 201 faces to the bottom of the cavity;
the passivation layer 202 is arranged on the front surface of the chip 201, a passivation layer opening 2021 is formed on the passivation layer 202, and the passivation layer opening 2021 is located at a position corresponding to a pad on the front surface of the chip;
and the rewiring structure is formed on the front surface of the chip 201 and is used for leading out the welding pad on the front surface of the chip.
In some embodiments, the front side of the chip is treated to form a rougher surface. For example, the front side of the chip may be plasma treated. In other embodiments, both the front and back sides of the chip are treated to form a rougher surface. Wherein the front and back surfaces of the chip may be plasma treated.
Further, in some embodiments, the rewiring structure includes:
a redistribution layer including a first redistribution layer 206, wherein the first redistribution layer 206 is formed on the passivation layer 202 and electrically connected to the pad of the chip 201 through the passivation layer opening 2021;
the second encapsulant layer 207 is formed on the redistribution layer 202 and the exposed passivation layer 202, and has an opening, and a conductive pillar 208 electrically connected to the redistribution layer is disposed in the opening 2071 of the second encapsulant layer 207.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (13)
1. A semiconductor packaging method, comprising:
processing the front surface of the chip to be packaged, and increasing the roughness of the front surface of the chip to be packaged;
the chip to be packaged is attached to a carrier plate through an adhesive layer, and the front surface of the chip to be packaged faces the carrier plate;
and packaging the chip to be packaged on the carrier plate to form a first packaging layer.
2. The semiconductor packaging method according to claim 1, wherein processing the front surface of the chip to be packaged comprises performing plasma processing on the front surface of the chip to be packaged.
3. The semiconductor packaging method of claim 1, wherein before the chip to be packaged is packaged over the carrier, the method comprises:
and processing the back surface of the chip to be packaged, and increasing the roughness of the back surface of the chip to be packaged.
4. The semiconductor packaging method according to claim 3, wherein processing the back surface of the chip to be packaged includes performing plasma processing on the back surface of the chip to be packaged.
5. The semiconductor packaging method according to claim 2 or 4, wherein oxygen gas is supplied to the plasma processing space when the front surface or the back surface of the chip to be packaged is subjected to plasma processing.
6. The semiconductor packaging method according to claim 2 or 4, wherein an electric power of 200W to 400W is used when plasma treatment is performed on the front surface or the back surface of the chip to be packaged.
7. The semiconductor packaging method according to claim 2 or 4, wherein the plasma treatment is performed on the front surface or the back surface of the chip to be packaged for a period of time of 30S to 120S.
8. The semiconductor packaging method of claim 1, wherein the step of attaching the chip to be packaged to the carrier through the adhesive layer comprises:
forming a bonding layer on the carrier plate;
and sticking the front surface of the chip to be packaged on the bonding layer.
9. The semiconductor packaging method of claim 1, wherein after forming the first encapsulation layer, the method comprises:
stripping the carrier plate to expose the front surface of the chip to be packaged;
and re-wiring the front surface of the chip to be packaged.
10. The semiconductor packaging method of claim 9, wherein the rewiring on the front side of the chip to be packaged comprises:
forming a passivation layer on the front surface of the chip to be packaged and one side of the first packaging layer, which is positioned on the front surface of the chip to be packaged;
forming a passivation layer opening on the passivation layer, wherein the passivation layer opening is positioned at a welding pad of the chip to be packaged;
and forming a rewiring layer on the passivation layer, wherein the rewiring layer is electrically connected with the welding pad on the chip to be packaged through the opening of the passivation layer.
11. The semiconductor packaging method of claim 10, wherein a re-wiring layer is formed on the passivation layer, the method further comprising: and forming a second packaging layer on the rewiring layer, and leading out a welding pad or a connection point of the rewiring layer through the conductive convex column.
12. The semiconductor packaging method according to claim 11, wherein after the forming of the first encapsulant layer and before the peeling of the carrier sheet, the method comprises:
and forming a fixed sealing layer on the first surface of the first packaging layer far away from the carrier plate.
13. The semiconductor packaging method of claim 12, wherein after forming the second encapsulant layer, the method comprises:
and stripping the sealing layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910177319.4A CN111668098A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910177319.4A CN111668098A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111668098A true CN111668098A (en) | 2020-09-15 |
Family
ID=72382077
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910177319.4A Pending CN111668098A (en) | 2019-03-08 | 2019-03-08 | Semiconductor packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111668098A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060128069A1 (en) * | 2004-12-10 | 2006-06-15 | Phoenix Precision Technology Corporation | Package structure with embedded chip and method for fabricating the same |
| US20060263936A1 (en) * | 2005-05-09 | 2006-11-23 | Phoenix Precision Technology Corporation | Surface roughening method for embedded semiconductor chip structure |
| TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
| US20100224983A1 (en) * | 2009-03-03 | 2010-09-09 | Min-Lung Huang | Semiconductor package structure and manufacturing method thereof |
| CN101866901A (en) * | 2009-04-09 | 2010-10-20 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
-
2019
- 2019-03-08 CN CN201910177319.4A patent/CN111668098A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060128069A1 (en) * | 2004-12-10 | 2006-06-15 | Phoenix Precision Technology Corporation | Package structure with embedded chip and method for fabricating the same |
| US20060263936A1 (en) * | 2005-05-09 | 2006-11-23 | Phoenix Precision Technology Corporation | Surface roughening method for embedded semiconductor chip structure |
| TW200924086A (en) * | 2007-11-16 | 2009-06-01 | Fupo Electronics Corp | Roughened structure for rearranged bonding pad and its manufacturing method |
| US20100224983A1 (en) * | 2009-03-03 | 2010-09-09 | Min-Lung Huang | Semiconductor package structure and manufacturing method thereof |
| CN101866901A (en) * | 2009-04-09 | 2010-10-20 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208014673U (en) | Chip package structure | |
| TWI756311B (en) | Chip packaging method and packaging structure | |
| TW201820565A (en) | Method of packaging chip and chip package structure | |
| CN210607192U (en) | Panel assembly, wafer package and chip package | |
| KR20020018103A (en) | A semiconductor deⅴice and a method of manufacturing the same | |
| US12211818B2 (en) | Manufacturing method of semiconductor package using jig | |
| US20100244229A1 (en) | Semiconductor package fabrication process and semiconductor package | |
| CN111668108B (en) | Semiconductor packaging method | |
| CN111916359B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668098A (en) | Semiconductor packaging method | |
| CN111952190B (en) | Semiconductor packaging method | |
| CN112117250B (en) | Chip packaging structure and manufacturing method thereof | |
| CN111668116A (en) | Semiconductor packaging method | |
| CN111668122B (en) | Semiconductor packaging method | |
| CN211017006U (en) | Panel assembly, wafer package and chip package | |
| CN111668111B (en) | Semiconductor packaging method | |
| CN111668105A (en) | Semiconductor packaging method | |
| CN113725097A (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111599694B (en) | Semiconductor packaging method | |
| JP7459576B2 (en) | Panel and manufacturing method thereof, panel manufacturing member and manufacturing method thereof, and semiconductor chip | |
| CN111668123B (en) | Semiconductor packaging method | |
| CN111668118B (en) | Semiconductor packaging method | |
| CN114613684B (en) | Semiconductor packaging method | |
| CN114975132B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668115A (en) | Semiconductor packaging method and semiconductor packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |