CN111654288A - A two-stage full dynamic comparator for SAR ADC and its working method - Google Patents

Abstract

The present invention relates to a two-stage full dynamic comparator for SAR ADC and its working method. The comparator includes two voltage input terminals of the first stage dynamic preamplifier with current source as the two voltage input terminals of the comparator, and the two output terminals of the first stage dynamic preamplifier with current source are subjected to the second stage dynamic bias type preamplifier. It is connected with the two input terminals of the SA dynamic latch, the two output terminals of the SA dynamic latch are used as the two output terminals of the comparator, and the clock signal terminals of the three modules are connected as the first clock signal terminal CLKC of the comparator, and the first clock signal terminal CLKC of the comparator is connected. The two-stage dynamic bias type pre-amplifier also includes a second clock signal terminal as the second clock signal terminal CLKCB of the comparator, and the input of CLKC and CLKCB is a pair of inverting clock signals. The preamplifier also includes two bias voltage inputs. The invention does not need to consider static power consumption, reduces the influence brought by the offset, reduces the input noise, and uses a two-stage dynamic pre-amplifier to improve the gain and linearity.

Description

A two-stage full dynamic comparator for SAR ADC and its working method

technical field

The present invention relates to a two-stage full dynamic comparator for SAR ADC and its working method.

Background technique

With the continuous development of science and technology, the Internet of Things gradually appears in people's field of vision and becomes more and more important. The Internet of Things is a network that can extend vertically and horizontally based on the Internet. The world has gone through the industrial era, the PC Internet era, the mobile Internet of Things era, and the current Internet of Things era. It can be seen that the Internet of Things has become the mainstream of today's society. The rapid development of the Internet of Things will give birth to the progress of many emerging industries. Taking China as an example, the country is vigorously promoting the integration of industrialization and informatization. The Internet of Things is the basic node of smart home, smart transportation, smart medical care, and smart logistics. Industries such as smart agriculture will develop rapidly.

As a device that can convert non-electrical signals in nature into electrical signals, sensors are the source of information for the entire Internet of Things system and one of the most critical technologies in the Internet of Things system. It is the focus of foreign research and development, and the scale of its market needs is on the order of trillions. The development of wearable smart devices (such as smart watches, smart phones, and smart homes) requires sensors to be small and light, that is, to have a series of features such as small size, low power consumption, and high performance. The same requirements apply to analog-to-digital converters, so ADCs with power consumption as low as milliwatts or even nanowatts meet the needs of modern smart devices.

Common ADCs on the market today include flash ADCs, pipelined ADCs, oversampling (Σ-Δ), and successive approximation (Successive Approximation Register) ADCs with different characteristics and uses. Among them, the resolution of Σ-Δ ADC can reach 16-24 bits, but the power consumption is high. The resolution of flash ADC is less than 10 bits, but the sampling rate is required to be very fast, while the sampling rate of SAR ADC is medium and low speed, and the resolution is average. It is about 12 bits and has low power consumption. It has become a commonly used ADC structure in wearable smart devices and medical fields. Therefore, the market application of the product determines that the SAR ADC is currently tending to the development direction of low power consumption and high precision. Therefore, low-power, high-resolution, and high-linearity comparators have extremely important research significance.

The SAR ADC consists of three main modules, namely DAC, comparator and SAR logic module. The power consumption and accuracy of the comparator determine the overall performance. Compared with the static comparator, the power consumption of the dynamic comparator is relatively low, and its two working states (comparison state and reset state) determine that the dynamic comparator is suitable for use in smart homes. However, the current dynamic comparator uses the method of static pre-amplification and dynamic latch. Because of the existence of the dynamic latch, it is also called a dynamic comparator, but the static power consumption of the pre-amplifier still cannot be reduced. The gain of the upper pre-amplifier is insufficient, resulting in an increase in the equivalent input noise, which greatly affects the overall power consumption and accuracy of the ADC, resulting in performance degradation. In order to solve the above deficiencies of dynamic comparators, researchers have devoted themselves to the study of full dynamic comparators with low power consumption, high resolution and high linearity.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a two-stage full dynamic comparator for SAR ADC and its working method, without considering static power consumption, reducing the influence of offset, reducing input noise, and using a two-stage dynamic preamplifier Increase gain and linearity.

In order to achieve the above purpose, the technical solution of the present invention is: a two-stage full dynamic comparator for SAR ADC, comprising a first-stage dynamic pre-amplifier with current source, a second-stage dynamic bias type pre-amplifier and an SA dynamic lock. register, the two voltage input terminals of the first stage dynamic preamplifier with current source are used as the two voltage input terminals of the comparator, the two output terminals of the first stage dynamic preamplifier with current source and the second stage dynamic bias preamplifier The two input terminals are connected, the two output terminals of the second-stage dynamic biasing pre-amplifier are connected with the two input terminals of the SA dynamic latch, and the two output terminals of the SA dynamic latch are used as the two output terminals of the comparator. The clock signal terminal of the dynamic pre-amplifier with current source, the first clock signal terminal of the second-stage dynamic bias type pre-amplifier, and the clock signal terminal of the SA dynamic latch are connected to the first clock signal terminal CLKC as a comparator. The second clock signal terminal of the two-stage dynamic bias type pre-amplifier is used as the second clock signal terminal CLKCB of the comparator, and a pair of inverted clock signals input by the first clock signal terminal CLKC and the second clock signal terminal CLKCB, the The first-stage dynamic preamplifier with current source also includes two bias voltage input terminals.

In an embodiment of the present invention, the first-stage dynamic preamplifier with current source includes transistors M1, M2, M3, M4, M5, M6, M7 and capacitors C1 and C2. The source of M1 and the source of M2 are connected to each other. It is connected to the drain of M4 and the drain of M5 in parallel. M1 and M2 are used as differential input transistors. The gate of M1 and the gate of M2 are used as the two voltage input terminals of the first-stage dynamic preamplifier with current source. The source of M4 The pole is connected to the drain of M3, the source of M3 is connected to the power supply potential, the gate of M3 and the gate of M4 are used as the two bias voltage input terminals of the first-stage dynamic preamplifier with current source, the drain of M1, the gate of M2 The drains of M1 and M7 are respectively connected to the drains of M6 and M7, and are respectively used as the two output terminals of the first stage dynamic preamplifier with current source. The drains of M1 and M6 are also connected to the upper plate of C1, The gate of M10 of the second-stage dynamic bias pre-amplifier is connected, the drain of M2 and the drain of M7 are also connected to the upper plate of C2 and the gate of M11 of the second-stage dynamic bias pre-amplifier , the source of M5, the source of M6, and the source of M7 are all connected to the ground potential, and the gate of M5, the gate of M6, and the gate of M7 serve as the clock signal terminals of the first-stage dynamic preamplifier with current source.

In an embodiment of the present invention, the second-stage dynamic bias type pre-amplifier includes transistors M8, M9, M10, M11, M12, M13 and capacitors C3, C4, and C5. The source of M8 and the source of M9 are in phase Connected to the power supply potential, the gate of M8, the gate of M9, and the gate of M12 serve as the second clock signal terminal of the second-stage dynamic biasing pre-amplifier, the drain of M8, the drain of M9 and the drain of M10 are respectively The drain electrode and the drain electrode of M11 are connected, and they are respectively used as the two output terminals of the second-stage dynamic bias type pre-amplifier. The drain electrode of M8 and the drain electrode of M9 are also connected to the upper plate of C3 and the upper plate of C4 respectively. The gate of M10 and the gate of M11 are respectively connected with the drain of M2 and the drain of M1 of the first-stage dynamic pre-amplifier with current source, and are respectively used as two input terminals of the second-stage dynamic bias type pre-amplifier, The source of M10, the source of M11 are connected to the drain of M12, the source of M12, the drain of M13, the upper plate of C5 are connected, the lower plate of C3, the lower plate of C4, the lower plate of C5, the lower plate of M13 The source is connected to the ground potential, and the gate of M13 is used as the first clock signal terminal of the second-stage dynamic bias type pre-amplifier.

In an embodiment of the present invention, the SA dynamic latch includes transistors M14, M15, M16, M17, M18, M19, M20, M21, the source of M14 and the source of M15 are connected to the power supply potential, and the source of M14 The gate, the gate of M19, the drain of M17, the drain of M20, and the drain of M21 are connected to each other, and serve as the first output terminal of the SA dynamic latch, the gate of M15, the gate of M20, the gate of M16 The drain, the drain of M18, and the drain of M19 are connected to each other, and serve as the second output terminal of the SA dynamic latch. The drain of M14 and the drain of M15 are respectively connected to the source of M16 and the source of M17. The gate of M16 and the gate of M17 are respectively connected with the drain of M9 and the drain of M8 of the second-stage dynamic bias type pre-amplifier, and serve as the two input terminals of the SA dynamic latch and the source of M18 respectively. , the source of M19, the source of M20, and the source of M21 are connected to the ground potential, and the gate of M18 and the gate of M21 serve as the clock signal terminals of the SA dynamic latch.

The present invention also provides a working method based on the above-mentioned two-stage full dynamic comparator for SAR ADC, which is implemented as follows:

Under the clock signal of a given frequency, the comparator compares the analog input signals input from the two voltage input terminals, and outputs the comparison result; the clock signal input by the first clock signal terminal CLKC of the comparator is low level, and the first clock signal of the comparator When the clock signal input by the second clock signal terminal CLKCB is at a high level, the comparator is in a comparison state, otherwise the comparator is in a reset state;

When the comparator is in the reset state, M5 in the first-stage dynamic preamplifier with current source is turned on, the source voltage of M1 and M2 are directly pulled to ground potential, transistors M6 and M7 are turned on, and capacitors C1 and C2 The upper plate is pulled to the ground potential, the first-stage dynamic pre-amplifier with current source does not work, the output signals of the two output terminals of the first-stage dynamic pre-amplifier with current source are zero potential, and the second-stage dynamic bias type pre-amplifier In the middle, M8 and M9 are turned on, M12 is turned off, and at the same time, the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential, M18 and M21 in the SA dynamic latch are turned on, M19 and M20 are turned off, and SA The output signals of the two output terminals of the dynamic latch are at zero potential, and at the same time, M14 and M15 are turned on, and the source voltages of M15 and M16 are pulled to the power supply potential;

When the comparator is in the comparison state, M1 and M2 in the first-stage dynamic pre-amplifier with current source are turned on at the same time. Since the comparator has a voltage difference between the input voltages of the two voltage input terminals, the leakage currents of M1 and M2 are different, resulting in M1 , M2 drain potential rises at different speeds, and the drain potential of the MOS transistor with a larger overdrive voltage rises faster, so the instantaneous potentials of the output signals output by the two output terminals of the first-stage dynamic preamplifier with current source are different; set the gate of M1 The pole input voltage is greater than the gate input voltage of M2. In the second-stage dynamic bias pre-amplifier, since the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential when the comparator is in the reset state, Combined with the precondition that the output potential rise time of the two output terminals of the first-stage dynamic pre-amplifier with current source is different, M10 reaches the conduction condition before M11, and the output potential of the first output terminal of the second-stage dynamic bias type pre-amplifier is first. When the power supply potential drops, the output potential of the second output terminal of the second-stage dynamic bias type pre-amplifier drops after that. Therefore, in the SA dynamic latch, M17 reaches the conduction condition before M16, and the first output terminal of the SA dynamic latch The output potential rises first, and the output potential of the second output terminal of the SA dynamic latch rises later. Once the output potential of the first output terminal of the SA dynamic latch rises to the potential where M19 is turned on, M19 is turned on and the SA dynamic latch is turned on. The output potential of the two output terminals is pulled to the ground potential, so the two output terminals of the comparator output the correct comparison result;

To sum up, when the gate input voltage of M1 is greater than the gate input voltage of M2, the output voltage of the first output terminal of the comparator is greater than the output voltage of the second output terminal of the comparator, and the comparison result is correct. On the contrary, when the gate input voltage of M1 is less than When the gate input voltage of M2 is used, the same is true.

Compared with the prior art, the present invention has the following beneficial effects: a two-stage full dynamic comparator suitable for high-resolution high-linearity SAR ADC of the present invention ignores the static power consumption generated by the traditional comparator, adopts dynamic power consumption, The energy consumption of the comparator is greatly reduced, and the second-stage pre-amplifier is used to increase the gain of the amplifier. The overall structure increases the linearity and the anti-interference to the change of the common mode level, and reduces the equivalent input noise; Various performance parameters of the comparator, such as system power consumption, linearity, accuracy, and input noise, were analyzed, and a two-stage full-dynamic comparator with high linearity, high precision, and low input noise suitable for SAR ADC was realized. The invention has great application prospects in low-power high-precision ADCs, especially SAR ADCs.

Description of drawings

Fig. 1 is the overall block diagram of the two-stage full dynamic comparator.

Figure 2 is a block diagram of a two-level full dynamic comparator system.

Fig. 3 is the circuit diagram of the first stage dynamic pre-amplifier with current source.

Fig. 4 is the circuit diagram of the second-stage dynamic biasing pre-amplifier.

Figure 5 is a circuit diagram of the SA dynamic latch.

Detailed ways

The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings.

The present invention provides a two-stage full dynamic comparator for SAR ADC, comprising a first-stage dynamic preamplifier with current source, a second-stage dynamic bias type preamplifier and SA dynamic latch, the first stage with current The two voltage input terminals of the source dynamic preamplifier are used as the two voltage input terminals of the comparator. The two output terminals of the first stage dynamic preamplifier with current source are connected with the two input terminals of the second stage dynamic bias type preamplifier. The second stage The two outputs of the dynamic bias preamplifier are connected to the two inputs of the SA dynamic latch. The two outputs of the SA dynamic latch are used as the two outputs of the comparator. The first stage has a clock of the current source dynamic preamplifier. The signal terminal, the first clock signal terminal of the second-stage dynamic bias type pre-amplifier, and the clock signal terminal of the SA dynamic latch are connected to the first clock signal terminal CLKC as the comparator, and the second-stage dynamic bias type pre-amplifier is connected to the first clock signal terminal CLKC of the comparator. The second clock signal terminal of the comparator is used as the second clock signal terminal CLKCB of the comparator, and a pair of inverted clock signals input by the first clock signal terminal CLKC and the second clock signal terminal CLKCB, the first stage with current source dynamic pre- The amplifier also includes two bias voltage inputs.

The first-stage dynamic preamplifier with current source includes transistors M1, M2, M3, M4, M5, M6, M7 and capacitors C1 and C2. The source of M1 and the source of M2 are connected and connected to the drain of M4, The drain of M5, M1 and M2 are used as differential input pair tubes, the gate of M1 and the gate of M2 are used as the two voltage input terminals of the first stage dynamic preamplifier with current source, the source of M4 is connected to the drain of M3, The source of M3 is connected to the power supply potential, the gate of M3 and the gate of M4 are used as two bias voltage input terminals of the first-stage dynamic preamplifier with current source, the drain of M1 and the drain of M2 are respectively connected with the drain of M6 pole and the drain of M7 are connected and used as the two output terminals of the first-stage dynamic preamplifier with current source, the drain of M1, the drain of M6, the upper plate of C1 and the second-stage dynamic bias preamplifier The gate of M10 is connected to the gate of M2, the drain of M2, the drain of M7, and the upper plate of C2 are connected to the gate of M11 of the second-stage dynamic bias pre-amplifier, the source of M5, the source of M6 , the source of M7, the lower plate of C1, and the lower plate of C2 are all connected to the ground potential, and the gate of M5, the gate of M6, and the gate of M7 are used as the clock signal of the first stage dynamic preamplifier with current source end.

The second-stage dynamic bias type pre-amplifier includes transistors M8, M9, M10, M11, M12, M13 and capacitors C3, C4, C5, the source of M8 and the source of M9 are connected to the power supply potential, and the gate of M8 The gate of M9, the gate of M12 are used as the second clock signal terminal of the second-stage dynamic bias type pre-amplifier, the drain of M8 and the drain of M9 are respectively connected to the drain of M10 and the drain of M11, They are respectively used as the two output terminals of the second-stage dynamic biasing pre-amplifier. The drain of M8 and the drain of M9 are also connected to the upper plate of C3 and the upper plate of C4 respectively, and the gate of M10 and the gate of M11. The electrodes are respectively connected with the drain of M2 and the drain of M1 of the first-stage dynamic pre-amplifier with current source, and are respectively used as the two input terminals of the second-stage dynamic bias pre-amplifier, the source of M10 and the source of M11. The pole is connected to the drain of M12, the source of M12, the drain of M13, and the upper plate of C5 are connected, the lower plate of C3, the lower plate of C4, the lower plate of C5, and the source of M13 are connected to the ground potential, The gate of M13 serves as the first clock signal terminal of the second-stage dynamic biasing pre-amplifier.

The SA dynamic latch includes transistors M14, M15, M16, M17, M18, M19, M20, M21, the source of M14 and the source of M15 are connected to the power supply potential, the gate of M14, the gate of M19, The drain of M17, the drain of M20, and the drain of M21 are connected to each other and serve as the first output terminal of the SA dynamic latch. The gate of M15, the gate of M20, the drain of M16, the drain of M18, The drain of M19 is connected to the second output terminal of the SA dynamic latch, the drain of M14 and the drain of M15 are connected to the source of M16 and the source of M17 respectively, the gate of M16 and the gate of M17 The terminals are respectively connected with the drain of M9 and the drain of M8 of the second-stage dynamic bias type pre-amplifier, and are respectively used as the two input terminals of the SA dynamic latch, the source of M18, the source of M19, the source of M20 The source and the source of M21 are connected to the ground potential, and the gate of M18 and the gate of M21 serve as the clock signal terminals of the SA dynamic latch.

The present invention also provides a working method based on the above-mentioned two-stage full dynamic comparator for SAR ADC, which is implemented as follows:

Under the clock signal of a given frequency, the comparator compares the analog input signals input from the two voltage input terminals, and outputs the comparison result; the clock signal input by the first clock signal terminal CLKC of the comparator is low level, and the first clock signal of the comparator When the clock signal input by the second clock signal terminal CLKCB is at a high level, the comparator is in a comparison state, otherwise the comparator is in a reset state;

When the comparator is in the reset state, M5 in the first-stage dynamic preamplifier with current source is turned on, the source voltage of M1 and M2 are directly pulled to ground potential, transistors M6 and M7 are turned on, and capacitors C1 and C2 The upper plate is pulled to the ground potential, the first-stage dynamic pre-amplifier with current source does not work, the output signals of the two output terminals of the first-stage dynamic pre-amplifier with current source are zero potential, and the second-stage dynamic bias type pre-amplifier In the middle, M8 and M9 are turned on, M12 is turned off, and at the same time, the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential, M18 and M21 in the SA dynamic latch are turned on, M19 and M20 are turned off, and SA The output signals of the two output terminals of the dynamic latch are at zero potential, and at the same time, M14 and M15 are turned on, and the source voltages of M15 and M16 are pulled to the power supply potential;

When the comparator is in the comparison state, M1 and M2 in the first-stage dynamic pre-amplifier with current source are turned on at the same time. Since the comparator has a voltage difference between the input voltages of the two voltage input terminals, the leakage currents of M1 and M2 are different, resulting in M1 , M2 drain potential rises at different speeds, and the drain potential of the MOS transistor with a larger overdrive voltage rises faster, so the instantaneous potentials of the output signals output by the two output terminals of the first-stage dynamic preamplifier with current source are different; set the gate of M1 The pole input voltage is greater than the gate input voltage of M2. In the second-stage dynamic bias pre-amplifier, since the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential when the comparator is in the reset state, Combined with the precondition that the output potential rise time of the two output terminals of the first-stage dynamic pre-amplifier with current source is different, M10 reaches the conduction condition before M11, and the output potential of the first output terminal of the second-stage dynamic bias type pre-amplifier is first. When the power supply potential drops, the output potential of the second output terminal of the second-stage dynamic bias type pre-amplifier drops after that. Therefore, in the SA dynamic latch, M17 reaches the conduction condition before M16, and the first output terminal of the SA dynamic latch The output potential rises first, and the output potential of the second output terminal of the SA dynamic latch rises later. Once the output potential of the first output terminal of the SA dynamic latch rises to the potential where M19 is turned on, M19 is turned on and the SA dynamic latch is turned on. The output potential of the two output terminals is pulled to the ground potential, so the two output terminals of the comparator output the correct comparison result;

To sum up, when the gate input voltage of M1 is greater than the gate input voltage of M2, the output voltage of the first output terminal of the comparator is greater than the output voltage of the second output terminal of the comparator, and the comparison result is correct. On the contrary, when the gate input voltage of M1 is less than When the gate input voltage of M2 is used, the same is true.

The following is the specific implementation process of the present invention.

In order to eliminate the static power consumption of the SAR ADC comparator, increase the gain, and reduce the input noise and the dependence on the common mode level, the present invention proposes a high resolution and high linearity two-stage full dynamic comparator as shown in Figure 1 . The fully dynamic comparator 1 (Comparator) includes two input voltages 2 (V ₊ , V ₋ ) of the comparator, a pair of inverted clock signals 3 (CLKC, CLKCB) and a pair of output signals 4 (OUTP, OUTN) . The system block diagram is shown in Figure 2, which includes three parts, the first stage with current source dynamic pre-amplifier 5 (1 ^st Pre-Amp), the second stage dynamic bias type pre-amplifier 6 (2 ^nd Pre-Amp) And SA dynamic latch 7 (SA-latch), wherein the input signal 2 is connected with the first stage preamplifier 5, and the output signal 4 is connected with the SA dynamic latch 7. In addition, the first clock input signal CLKC is connected with the first-stage pre-amplifier 5, the second-stage pre-amplifier 6, and the SA dynamic latch 7, and the inverting input signal CLKCB of CLKC is connected with the second-stage pre-amplifier 6, A pair of output signals 8 (on1, op1) of the first-stage pre-amplifier 5 is connected to it as the input end of the second-stage pre-amplifier 6, and similarly a pair of output signals 9 (on2, op2) of the second-stage pre-amplifier 6 As the input terminal of the SA dynamic latch 7 is connected to it, two bias voltages 10 (V _BIAS1 , V _BIAS2 ) act on the first stage preamplifier 5 and are connected to it.

The specific structure of the first-stage dynamic preamplifier 5 with current source is shown in FIG. 3 , which is composed of transistors M1, M2, M3, M4, M5, M6, M7 and capacitors C1 and C2. Among them, the sources of M1 and M2 are connected to the drains of M4 and M5, which are used as differential input pairs, and the gates are connected to the comparator input signal 2. V _BIAS2 acts on the gate of M4, whose source is connected to the drain of M3. V _BIAS1 acts on the gate of M3, the source of M3 is connected to the power supply potential, it is always in the saturation region as a current source, and the change of _{V DS} has little effect on the leakage current ID of the circuit, so when the common mode level changes, This minimizes the effect of dynamic offset on the linearity of the entire comparator, thereby increasing noise immunity. The drains of M1 and M2 are connected to the drains of M6 and M7, and are respectively used as the output signal 8 (on1, op1) of the first stage to be connected to the upper plates of capacitors C1 and C2, and the sources of M5, M6 and M7 All are connected to the ground potential, and the gates of M5, M6, and M7 are connected and controlled by the first clock signal CLKC.

The leakage current expression of the known MOS tube in the saturation region is as follows:

为晶体管的宽长比，V_GS-V_TH为过驱动电压，V_DS为漏源电压。处在饱和区的MOS管漏电流计算如式(1)所示，漏电流的大小与漏源电压V_DS有关，V_DS的变化会导致处在饱和区的MOS管漏电流的大小发生变化。因此当比较器的输入共模电平发生变化时，对比较器线性度影响很大。为了减小漏源电压V_DS变化带来的影响，引入了电流源管M3实现一个cascode结构，利用cascode结构的屏蔽特性，使得比较器输入共模电压的变化给M3的V_DS带来的影响最小化，实现M3的漏电流几乎不变，因此提高了比较器的线性度。where is μ _p carrier mobility, C _ox is the gate oxide capacitance,

is the aspect ratio of the transistor, V _GS -V _TH is the overdrive voltage, and V _DS is the drain-source voltage. The leakage current of the MOS tube in the saturation region is calculated as shown in formula (1). The magnitude of the leakage current is related to the drain-source voltage V _DS . The change of V _DS will cause the leakage current of the MOS tube in the saturation region to change. Therefore, when the input common mode level of the comparator changes, the linearity of the comparator is greatly affected. In order to reduce the influence of the change of the drain-source voltage V _DS , the current source tube M3 is introduced to realize a cascode structure, and the shielding characteristics of the cascode structure are used to make the change of the input common mode voltage of the comparator affect the V _DS of M3. Minimized, the leakage current of M3 is almost constant, thus improving the linearity of the comparator.

The specific structure of the second-stage dynamic bias type pre-amplifier 6 is shown in FIG. 4 , which is composed of transistors M8, M9, M10, M11, M12, M13 and capacitors C3, C4, and C5. The output signal 8 (on1, op1) of the first stage is connected to the gates of the differential input pair transistors M11 and M10 as the input of the second stage. The drains of M8 and M10 are connected and connected to the upper plate of the capacitor C4. Similarly, the drains of M9 and M11 are connected and connected to the upper plate of the capacitor C4. The two also serve as the second-level output signal 9 (on2, op2). The M8, M9 sources are connected to the power supply potential. Input pair tube M10, the source terminal of M11 is connected to the drain terminal of M12, the source terminal of M12 is connected to the drain terminal of M13 and connected to the upper plate of the capacitor C5 together, the source terminal of M13 is connected to the ground, M12, M13 are used as switches The tube controls the working state of this stage of the circuit. The second clock signal CLKCB acts on the gates of M8, M9 and M12, and the first clock signal CLKC acts on the gate of M13.

值有关，其值越高，等效输入噪声越小。在比较状态，CLKCB为高电平，电容C3进行放电，提升输入对管M10,M11的源端电压V_S，从而减小过驱动电压，减小漏电流，使得

值提高，减小等效输入噪声。The equivalent input noise of the comparator is the same as

value, the higher the value, the smaller the equivalent input noise. In the comparison state, CLKCB is at a high level, the capacitor C3 is discharged, and the source voltage V _S of the input pair transistors M10 and M11 is increased, thereby reducing the overdrive voltage and leakage current, so that the

Increase the value to reduce the equivalent input noise.

The specific structure of the SA dynamic latch 7 is shown in Figure 5, which is composed of M14, M15, M16, M17, M18, M19, M20, and M21. The second-stage output signal 9 (on2, op2) is connected to the gates of M17 and M16 as input signals respectively, and the sources of M16 and M17 are connected to the drains of M14 and M15 respectively. In order to form a positive feedback latch, the gates of M14 and M19 are connected to the drains of M17, M20, and M21. Due to the symmetry of the circuit, the gates of M15 and M20 are also connected to the drains of M16, M18, and M19, respectively. As output signal 4 (OUTP, OUTN). The sources of M18 to M20 are connected to the ground, and the sources of M14 and M15 are connected to the power supply voltage. The clock signal CLKC controls the gates of M18 and M21 to turn them on and off. When CLKC is low, the circuit compares, and the result is stored by the latch.

Under the clock signal of a given frequency, the comparator compares the two analog input signals and outputs a normal comparison result. When CLKC is low, it is in the comparison state when CLKCB is high, and vice versa. In the reset state, M5 in the first-stage pre-amplifier 5 is turned on, the source voltages of M1 and M2 are directly pulled to the ground potential, the first-stage circuit does not work, and the first-stage output signal 8 (on1, op1) is zero. potential. In the second-stage preamplifier 6, M8 and M9 are turned on, M12 is turned off, and at the same time, M8 and M9 are turned on, and the second-stage output signal 9 (on2, op2) is pulled to the power supply potential. In the SA dynamic latch 7, M18 and M21 are turned on, M19 and M20 are turned off, the output signal 4 (OUTP, OUTN) is zero potential, while M14 and M15 are turned on, and the source voltages of M15 and M16 are pulled to the power supply potential.

In the comparison state, M1 and M2 in the first stage pre-amplifier 5 are turned on at the same time. Due to the voltage difference between the input terminal voltages 2 (V ₊ , V _- ), the leakage currents on both sides are different, resulting in different speed of the drain terminal potential rise. , the potential of the drain terminal of the MOS transistor with a larger overdrive voltage rises faster, so the instantaneous potential of the first-stage output signal 8 (on1, op1) is different, and the rise time of the potential of op1 is less than the rise time of the on1 potential (ie V ₊ > V _- ) Take an example to illustrate. In the second-stage pre-amplifier 6, since the output signal 9 (on2, op2) is pulled to the power supply potential in the reset state, combined with the precondition that the first-stage output potential rise time is different, M10 reaches the conduction condition before M11, The on2 potential first drops from the power supply potential, and then the op2 potential drops. In the SA dynamic latch 7, the potential of on2 falls fast, so M17 reaches the conduction condition earlier than M16, the potential of OUTP rises first, and then the potential of OUTN rises. Once OUTP rises to the potential where M19 is turned on, M19 is turned on to pull OUTN to ground potential, so the comparator output signal 4 (OUTP, OUTN) outputs the correct comparison result.

To sum up, when V ₊ > V _- , the comparator outputs OUTP > OUTN, and the comparison result is correct. On the contrary, when V _- > V ₊ , the work analysis process of the comparator is the same as above.

In one clock cycle, the comparator performs a comparison, a reset phase, and outputs the comparison result, and the result is correct. The research shows that the first stage adopts the preamplifier with current source and the second stage adopts the dynamic bias type preamplifier, which has a good effect on reducing the input noise of the circuit, increasing the common mode level anti-interference, and improving the In addition, the full dynamic mode does not need to consider static power consumption, which greatly reduces the power consumption compared with the traditional comparator. Using a two-stage structure also increases the gain of the preamplifier.

The above are the preferred embodiments of the present invention, all changes made according to the technical solutions of the present invention, when the resulting functional effects do not exceed the scope of the technical solutions of the present invention, belong to the protection scope of the present invention.

Claims (5)

1. a two-stage full dynamic comparator for SAR ADC, is characterized in that, comprises the first-stage dynamic pre-amplifier with current source, the second-stage dynamic bias type pre-amplifier and the SA dynamic latch, the first stage The two voltage input terminals of the dynamic preamplifier with current source are used as the two voltage input terminals of the comparator. The two output terminals of the first stage dynamic preamplifier with current source are connected with the two input terminals of the second stage dynamic bias type preamplifier. The two output terminals of the two-stage dynamic biasing pre-amplifier are connected with the two input terminals of the SA dynamic latch. The two output terminals of the SA dynamic latch are used as the two output terminals of the comparator. The first-stage dynamic pre-amplifier with current source The clock signal terminal of the second-stage dynamic bias type pre-amplifier and the clock signal terminal of the SA dynamic latch are connected to the first clock signal terminal CLKC as a comparator, and the second-stage dynamic bias type The second clock signal terminal of the pre-amplifier is used as the second clock signal terminal CLKCB of the comparator, and a pair of inverted clock signals input by the first clock signal terminal CLKC and the second clock signal terminal CLKCB, the first stage has a current source The dynamic preamplifier also includes two bias voltage inputs. 2. The two-stage full dynamic comparator for SAR ADC according to claim 1, wherein the first-stage dynamic pre-amplifier with current source comprises transistors M1, M2, M3, M4, M5, M6, M7 and capacitors C1, C2, the source of M1, the source of M2 are connected and connected to the drain of M4, the drain of M5, M1, M2 are used as differential input pair tubes, the gate of M1, the gate of M2 As the two voltage input terminals of the first-stage dynamic preamplifier with current source, the source of M4 is connected to the drain of M3, the source of M3 is connected to the power supply potential, the gate of M3 and the gate of M4 are used as the first-stage belt The two bias voltage input terminals of the current source dynamic pre-amplifier, the drain of M1 and the drain of M2 are respectively connected to the drain of M6 and the drain of M7, and they are respectively used as two of the first-stage dynamic pre-amplifier with current source. Output terminal, the drain of M1, the drain of M6, and the upper plate of C1 are connected to the gate of M10 of the second-stage dynamic bias pre-amplifier, the drain of M2, the drain of M7, and the upper plate of C2 It is connected to the gate of M11 of the second-stage dynamic bias type pre-amplifier, the source of M5, the source of M6, the source of M7, the lower plate of C1, and the lower plate of C2 are all connected to the ground potential, The gate of M5, the gate of M6, and the gate of M7 serve as the clock signal terminals of the first stage dynamic preamplifier with current source. 3. The two-stage full dynamic comparator for SAR ADC according to claim 2, wherein the second-stage dynamic bias type pre-amplifier comprises transistors M8, M9, M10, M11, M12, M13 and capacitors C3, C4, C5, the source of M8 and the source of M9 are connected to the power supply potential, and the gate of M8, the gate of M9, and the gate of M12 are used as the second stage dynamic bias type pre-amplifier. Two clock signal terminals, the drain of M8 and the drain of M9 are respectively connected with the drain of M10 and the drain of M11, and are respectively used as two output terminals of the second-stage dynamic bias type pre-amplifier, the drain of M8, the drain of M9 The drain of M10 is also connected to the upper plate of C3 and the upper plate of C4 respectively. The gate of M10 and the gate of M11 are respectively connected with the drain of M2 and the drain of M1 of the first stage dynamic preamplifier with current source. connected and used as the two input terminals of the second-stage dynamic biasing pre-amplifier respectively, the source of M10 and the source of M11 are connected to the drain of M12, the source of M12, the drain of M13, and the upper plate of C5 are connected, and C3 The lower plate of C4, the lower plate of C5, and the source of M13 are connected to the ground potential, and the gate of M13 serves as the first clock signal terminal of the second-stage dynamic bias type pre-amplifier. 4. A two-stage full dynamic comparator for SAR ADC according to claim 3, wherein the SA dynamic latch comprises transistors M14, M15, M16, M17, M18, M19, M20, M21, the source of M14 and the source of M15 are connected to the power supply potential, the gate of M14, the gate of M19, the drain of M17, the drain of M20 and the drain of M21 are connected to each other, and are dynamically latched as SA The gate of M15, the gate of M20, the drain of M16, the drain of M18 and the drain of M19 are connected to the first output terminal of the SA dynamic latch, and serve as the second output terminal of the SA dynamic latch, and the drain of M14 The pole and the drain of M15 are respectively connected to the source of M16 and the source of M17, the gate of M16 and the gate of M17 are respectively connected to the drain of M9 and the drain of M8 of the second-stage dynamic bias type pre-amplifier. connected to the two input terminals of the SA dynamic latch, respectively, the source of M18, the source of M19, the source of M20, and the source of M21 are connected to the ground potential, and the gate of M18 and the gate of M21 are used as The clock signal terminal of the SA dynamic latch. 5. a kind of working method based on a kind of two-stage full dynamic comparator for SAR ADC according to claim 4, is characterized in that, realizes as follows: Under the clock signal of a given frequency, the comparator compares the analog input signals input from the two voltage input terminals, and outputs the comparison result; the clock signal input by the first clock signal terminal CLKC of the comparator is low level, and the first clock signal of the comparator When the clock signal input by the second clock signal terminal CLKCB is at a high level, the comparator is in a comparison state, otherwise the comparator is in a reset state; When the comparator is in the reset state, M5 in the first-stage dynamic preamplifier with current source is turned on, the source voltage of M1 and M2 are directly pulled to ground potential, transistors M6 and M7 are turned on, and capacitors C1 and C2 The upper plate is pulled to the ground potential, the first-stage dynamic pre-amplifier with current source does not work, the output signals of the two output terminals of the first-stage dynamic pre-amplifier with current source are zero potential, and the second-stage dynamic bias type pre-amplifier In the middle, M8 and M9 are turned on, M12 is turned off, and at the same time, the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential, M18 and M21 in the SA dynamic latch are turned on, M19 and M20 are turned off, and SA The output signals of the two output terminals of the dynamic latch are at zero potential, and at the same time, M14 and M15 are turned on, and the source voltages of M15 and M16 are pulled to the power supply potential; When the comparator is in the comparison state, M1 and M2 in the first-stage dynamic pre-amplifier with current source are turned on at the same time. Since the comparator has a voltage difference between the input voltages of the two voltage input terminals, the leakage currents of M1 and M2 are different, resulting in M1 , M2 drain potential rises at different speeds, and the drain potential of the MOS transistor with a larger overdrive voltage rises faster, so the instantaneous potentials of the output signals output by the two output terminals of the first-stage dynamic preamplifier with current source are different; set the gate of M1 The pole input voltage is greater than the gate input voltage of M2. In the second-stage dynamic bias pre-amplifier, since the output signals of the two output terminals of the second-stage dynamic bias pre-amplifier are pulled to the power supply potential when the comparator is in the reset state, Combined with the precondition that the output potential rise time of the two output terminals of the first-stage dynamic pre-amplifier with current source is different, M10 reaches the conduction condition before M11, and the output potential of the first output terminal of the second-stage dynamic bias type pre-amplifier is first. When the power supply potential drops, the output potential of the second output terminal of the second-stage dynamic bias type pre-amplifier drops after that. Therefore, in the SA dynamic latch, M17 reaches the conduction condition before M16, and the first output terminal of the SA dynamic latch The output potential rises first, and the output potential of the second output terminal of the SA dynamic latch rises later. Once the output potential of the first output terminal of the SA dynamic latch rises to the potential where M19 is turned on, M19 is turned on and the SA dynamic latch is turned on. The output potential of the two output terminals is pulled to the ground potential, so the two output terminals of the comparator output the correct comparison result; To sum up, when the gate input voltage of M1 is greater than the gate input voltage of M2, the output voltage of the first output terminal of the comparator is greater than the output voltage of the second output terminal of the comparator, and the comparison result is correct. On the contrary, when the gate input voltage of M1 is less than The same is true when the gate input voltage of M2 is used.

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