CN111653526A - SiP 3-dimensional packaging and processing method of high-power hybrid semiconductor integrated circuit - Google Patents
SiP 3-dimensional packaging and processing method of high-power hybrid semiconductor integrated circuit Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
The invention provides a SiP (system in Package) 3-dimensional packaging and processing method of a high-power hybrid semiconductor integrated circuit module, which realizes the heat dissipation and shielding requirements of a high-power semiconductor; secondly, the chips with complex and high cost are not required to be developed and produced specially, but more functions can be quickly, flexibly and integrally formed in a limited space at low cost, the product development is quick, the upgrade iteration is faster than the Moore's law, and the chip processing limit is higher than the chip processing limit; in particular, the integration of heterogeneous chip integration, resistance, capacitance and inductance which can not be realized or is difficult to realize by the traditional integrated circuit manufacturing and packaging process can be easily realized.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit packaging, and particularly relates to a SiP 3 dimensional packaging and processing method of a high-power hybrid semiconductor integrated circuit module.
Background
The current semiconductor integrated circuit mainly carries out 2-dimensional plane packaging on a single frame or a single packaging substrate, and is difficult to carry out polycrystal circle packaging or complex function multi-element multi-wafer system packaging due to the limitation of the area of the frame; even in the currently developed wafer-level 3 d package, more wafers can be integrated by placing the wafers on the silicon-based interposer and stacking the silicon-based interposers to improve the space utilization. However, the silicon-based interposer and the silicon-based interposer are complicated in process and high in manufacturing cost, and can be manufactured only by wafer manufacturers generally, and the number of global wafer manufacturers is limited, so that the silicon-based interposer and the silicon-based interposer are weak in supply capacity, high in price and not easy to obtain. Meanwhile, the silicon-based carrier plates are connected, the stacking manufacturing process is complex, the cost is high, and the silicon-based carrier plates are not used unless products with extremely high cost bearing capacity are used at a high end, so that the selectivity and the popularization of the packaging process for product research and development are influenced. And the wafer level 3-dimensional packaging can only integrate wafers, if a resistor and a capacitor are integrated at the same time, the inductance elements and the heat productivity during working are large, the wiring generated on the silicon-based adapter plate is difficult to support large current, and the high-power semiconductor wafer which needs to be connected by thick metal wire bonding has the disadvantages of low cost and difficult or even impossible process, so that the realization of more product functions and the flexibility and flexibility of development are limited, and the packaging for the SiP system has great limitation.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a novel SiP 3 dimensional packaging and processing method of a high-power hybrid semiconductor integrated circuit module, so that the SiP 3 dimensional packaging supporting a high-power semiconductor integrated circuit can be manufactured and provided, and the requirements of heat dissipation and shielding of a high-power semiconductor can be supported; secondly, the existing mature packaging substrate process can be utilized, the chips and the silicon-based switching carrier plates with complex and high cost are not required to be specially researched and produced, more functions can be quickly, flexibly and inexpensively integrated in a limited space, the Moore's law is surpassed, and the chip processing procedure and the supply limit of a wafer manufacturing factory are surpassed; particularly, the integration of heterogeneous chips, high-power semiconductor wafers, resistors, capacitors and inductors which cannot be or are difficult to realize by the traditional integrated circuit manufacturing and packaging process can be easily realized;
in a first aspect, the SiP 3-dimensional packaging of the high-power hybrid semiconductor integrated circuit comprises at least 2 layers or more than 2 layers of non-silicon packaging substrates, wherein except for the bottommost layer and the topmost layer of packaging substrates, the packaging substrates can be aluminum-based packaging substrates, copper-based packaging substrates, ceramic-based packaging substrates and epoxy resin-based packaging substrates, other middle layers are epoxy resin-based packaging substrates;
pins are arranged on the bottom packaging substrate, and the pins can be in the form of bonding pads supporting a surface mount technology, metal flat pins or metal vertical pins supporting a plug-in technology;
preferably, the high-power heating element or the wafer is placed on the topmost or bottommost packaging substrate;
preferably, a wafer or other noncircular elements are fixed on each layer of packaging substrate, and the wafer or other noncircular elements can be fixed on one surface or the upper surface and the lower surface of the packaging substrate;
preferably, the wafer on the package substrate is connected with the package substrate through a metal wire bonding process or connected through a copper wire attached to the package substrate, and the other non-wafer elements are connected with each other or the wafer through the copper wire attached to the package substrate;
preferably, the package substrates are connected through metal conductive pins or metal pads to perform the electrical connection and fixing function between the package substrates;
preferably, for products without electromagnetic shielding or accelerated heat dissipation requirements, the package exterior is molded with an EMC epoxy molding compound for structural reinforcement and insulation, thermal conduction, moisture protection, oxidation resistance, and internal component assist fixation.
Preferably, for products with electromagnetic shielding or accelerated heat dissipation requirements, a metal cover can be sleeved outside the module, the metal cover is connected with the bottommost packaging substrate, and a metal layer can be manufactured on the bottom surface of the bottommost packaging substrate to form a near-closed space together with the metal cover
Preferably, for products encased in a metal casing, the module is encapsulated in the metal casing interior by an EMC epoxy molding compound for structural reinforcement and insulation, heat conduction, moisture protection, oxidation resistance and internal component assist attachment.
Preferably, if a metal cover is provided, the metal cover is provided with metal holes, and the number of the metal holes is one or more than one.
In a second aspect, the processing method of SiP 3 dimensional package of the high power hybrid semiconductor integrated circuit module comprises the following steps:
manufacturing at least 2 layers or more than 2 layers of non-silicon material packaging substrates according to requirements, wherein except that the bottommost layer and the topmost layer of packaging substrates can be an aluminum-based packaging substrate, a copper-based packaging substrate, a ceramic-based packaging substrate and an epoxy resin-based packaging substrate, other middle layers are epoxy resin-based packaging substrates;
and arranging pins on the bottommost packaging substrate, wherein the pins can be in the form of bonding pads supporting a chip mounting process, metal flat pins or metal vertical pins supporting a plug-in process.
Preferably, the high power heating element or wafer is placed on the topmost or bottommost package substrate.
Preferably, a wafer or other noncircular elements are fixed on each layer of packaging substrate, and the wafer or other noncircular elements can be fixed on one surface or the upper surface and the lower surface of the packaging substrate;
preferably, the wafer is connected with the packaging substrate through a metal wire bonding process or connected through a copper circuit attached to the packaging substrate on the packaging substrate, and other non-wafer elements are connected with each other or the wafer through the copper circuit attached to the packaging substrate;
preferably, the package substrates are connected through metal conductive pins or metal pads to perform the electrical connection and fixing function between the package substrates;
preferably, for products without electromagnetic shielding or accelerated heat dissipation requirements, the package exterior is molded with an EMC epoxy molding compound for structural reinforcement and insulation, thermal conduction, moisture protection, oxidation resistance, and internal component assist attachment.
Preferably, for products with electromagnetic shielding or accelerated heat dissipation requirements, a metal cover can be sleeved outside the module, the metal cover is connected with the bottommost packaging substrate, and a metal layer can be manufactured on the bottom surface of the bottommost packaging substrate to form a near-closed space together with the metal cover.
Preferably, for products encased in a metal casing, the module is encapsulated in the metal casing interior by an EMC epoxy molding compound for structural reinforcement and insulation, heat conduction, moisture protection, oxidation resistance and internal component assist attachment.
Preferably, if a metal cover is provided, the size of the aperture and the number of the metal holes on the metal cover are precisely designed according to electromagnetic shielding requirements and molding process requirements on the metal cover so as to support the EMC epoxy molding process and electromagnetic shielding requirements.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
Fig. 1 is a schematic structural cross-sectional view of a SiP 3-dimensional package of a high-power hybrid semiconductor integrated circuit module according to an embodiment of the present invention.
Fig. 2 is an external perspective view of a SiP 3-dimensional package of a high power hybrid semiconductor integrated circuit module according to an embodiment of the present invention.
Fig. 3 is an external top view of a SiP 3-dimensional package of a high power hybrid semiconductor integrated circuit module according to an embodiment of the present invention.
Fig. 4 is a bottom external bottom view of a SiP 3-dimensional package of a high power hybrid semiconductor integrated circuit module according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an internal package substrate and an attachment element of a SiP 3 d package of a high power hybrid semiconductor integrated circuit module according to an embodiment of the invention.
Note that:
1, 8-metal cover 2-EMC epoxy mold sealing resin 3, 14-bonding metal wire
4-intermediate epoxy resin package substrate 5-device or wafer on package substrate
6, 16-metal conductive pin, conductive post 7, 9, 12-bottom packaging substrate
10-metal vias 11-package pin layout 13-package substrate 15-wafer
17, 19-component 18-package substrate metal routing
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby. It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The first embodiment is as follows:
a SiP 3 dimensional package of high power hybrid semiconductor integrated circuit module, see figure 1, includes at least 2 or more than 2 layers of non-silicon material package substrates, wherein except for the bottommost layer and the topmost layer package substrates, which can be aluminum-based package substrates, copper-based package substrates, ceramic-based package substrates, epoxy resin-based package substrates, other middle layers are epoxy resin-based package substrates;
on the bottom package substrate, there are disposed pins, which may be in the form of pads supporting the die attach process, metal flat pins, or metal vertical pins supporting the package attach process, as shown in fig. 4.
Fixing a wafer or other non-wafer elements on each layer of packaging substrate, wherein the wafer or other non-wafer elements can be fixed on one surface or both of the upper and lower surfaces of the packaging substrate, and refer to fig. 1 and 5;
the wafer on the package substrate is connected with the package substrate through a metal wire bonding process or connected through a copper circuit attached to the package substrate, and other non-wafer elements are connected with each other or with the wafer through the copper circuit attached to the package substrate, referring to fig. 1 and 5;
the package substrates are connected through metal conductive pins or metal pads to perform the electrical connection and fixing function between the package substrates, refer to fig. 1;
preferably, the high power heating element or wafer is placed on the topmost or bottommost package substrate, see fig. 1, 5.
Preferably, for products without electromagnetic shielding or accelerated heat dissipation requirements, the package exterior is molded with EMC epoxy molding compound for structural reinforcement and insulation, thermal conduction, moisture protection, oxidation resistance and internal component assist fixation, see fig. 1.
Preferably, for a product with electromagnetic shielding or accelerated heat dissipation requirements, a metal cover may be sleeved outside the module, the metal cover is connected with the bottommost package substrate, and a metal layer may be fabricated on the bottom surface of the bottommost package substrate to form a near-closed space together with the metal cover, as shown in fig. 1.
Preferably, for a product encased in a metal casing, the module is encapsulated by an EMC epoxy molding compound for structural reinforcement and insulation, heat conduction, moisture protection, oxidation resistance and internal component assist fixation in the metal casing interior space, see fig. 1.
Specifically, if there is a metal cover, the size and number of the metal holes on the metal cover are precisely designed according to the electromagnetic shielding requirement and the molding process requirement on the metal cover to support the EMC epoxy molding process and electromagnetic shielding requirement, refer to fig. 2;
thus, the SiP 3 dimensional package supporting the high-power hybrid semiconductor integrated circuit module can realize the heat dissipation and shielding requirements of the high-power semiconductor; secondly, complex and high-cost chips are not required to be developed and produced specially, mature substrate packaging processes or wafers are utilized, more functions can be rapidly, flexibly and at low cost integrated in a limited space, and rapid development, upgrading and iteration of products are realized, exceeding Moore's law and exceeding the limit of chip manufacturing procedures; particularly, the integration of heterogeneous chips, high-power large-current heating wafers, resistors, capacitors and inductors which cannot be realized or are difficult to realize by the traditional integrated circuit manufacturing and packaging process can be easily realized.
Example two:
a processing method for SiP 3 dimensional packaging of a high-power hybrid semiconductor integrated circuit comprises the following steps:
manufacturing at least 2 or more than 2 layers of non-silicon packaging substrates, wherein except for the bottommost layer and the topmost layer of packaging substrates, the packaging substrates can be aluminum-based packaging substrates, copper-based packaging substrates, ceramic-based packaging substrates and epoxy resin-based packaging substrates, and the other middle layers are epoxy resin-based packaging substrates;
and arranging pins on the bottommost packaging substrate, wherein the pins can be in the form of bonding pads supporting a chip mounting process, metal flat pins or metal vertical pins supporting a plug-in process.
Preferably, the high power heating element or wafer is placed on the topmost or bottommost package substrate.
Preferably, a wafer or other noncircular elements are fixed on each layer of packaging substrate, and the wafer or other noncircular elements can be fixed on one surface or the upper surface and the lower surface of the packaging substrate;
preferably, the wafer is connected with the packaging substrate through a metal wire bonding process or connected through a copper circuit attached to the packaging substrate on the packaging substrate, and other non-wafer elements are connected with each other or the wafer through the copper circuit attached to the packaging substrate;
preferably, the package substrates are connected through metal conductive pins or metal pads to perform the electrical connection and fixing function between the package substrates;
preferably, for products without electromagnetic shielding or accelerated heat dissipation requirements, the package exterior is molded with an EMC epoxy molding compound for structural reinforcement and insulation, thermal conduction, moisture protection, oxidation resistance, and internal component assist fixation.
Preferably, for products with electromagnetic shielding or accelerated heat dissipation requirements, a metal cover can be sleeved outside the module, the metal cover is connected with the bottommost packaging substrate, and a metal layer can be manufactured on the bottom surface of the bottommost packaging substrate to form a near-closed space together with the metal cover.
Preferably, for the product encased in the metal casing, the module is encapsulated by an EMC epoxy molding compound in the interior space of the metal casing for structural reinforcement and insulation, heat conduction, moisture protection, oxidation resistance and additional fixation of internal components.
Preferably, if a metal cover is provided, the size and the number of the metal holes on the metal cover are accurately designed according to the electromagnetic shielding requirement and the molding sealing process requirement on the metal cover so as to support the EMC epoxy molding sealing process and the electromagnetic shielding requirement;
for the sake of brief description, the method provided by the embodiment of the present invention may refer to the corresponding contents in the foregoing product embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (10)
1. A SiP (system in Package) 3-dimensional package of a high-power hybrid semiconductor integrated circuit module,
the 3-dimensional package comprises at least 2 layers or more than 2 layers of non-silicon packaging substrates, wherein except for the bottommost layer and the topmost layer of packaging substrates, the packaging substrates can be aluminum-based packaging substrates, copper-based packaging substrates, ceramic-based packaging substrates and epoxy resin-based packaging substrates, other middle layers are epoxy resin-based packaging substrates;
a metal cover can be sleeved outside the module, the metal cover is connected with the bottommost packaging substrate, and a metal layer can be manufactured on the bottom surface of the bottommost packaging substrate and forms a near-closed metal space together with the metal cover.
2. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
the packaging substrates are fixedly connected through metal conductive pins or metal pads.
3. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
pins are arranged on the bottom packaging substrate, and the pins can be in the form of bonding pads supporting a chip mounting process, metal flat pins or metal vertical pins supporting a plug-in process.
4. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
each layer of packaging substrate is provided with a fixed wafer or other noncircular elements, and one surface or the upper surface and the lower surface of the packaging substrate can be fixed with the wafer or other noncircular elements.
5. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 4,
the wafer on the packaging substrate is connected with the packaging substrate through a metal wire bonding process or connected through a copper circuit attached to the packaging substrate, and other non-wafer elements are connected with each other or the wafer through the copper circuit attached to the packaging substrate.
6. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
the module is encapsulated by EMC epoxy molding compound in the inner space of the metal cover for structure strengthening, insulation, heat conduction, moisture resistance, oxidation resistance and auxiliary fixation of internal components.
7. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
if a metal cover is provided, the number of the holes on the metal cover is 1 or more than one.
8. The SiP 3-dimensional package of high power hybrid semiconductor integrated circuit module according to claim 1,
the wafer or the component with high power and large heat generation is placed on the bottommost layer or the topmost layer of the packaging substrate.
9. A SiP 3 dimensional packaging processing method of a high-power hybrid semiconductor integrated circuit module is characterized by comprising the following steps: manufacturing at least 2 or more than 2 layers of non-silicon packaging substrates, wherein except for the bottommost layer and the topmost layer of packaging substrates, the packaging substrates can be aluminum-based packaging substrates, copper-based packaging substrates, ceramic-based packaging substrates and epoxy resin-based packaging substrates, and the other middle layers are epoxy resin-based packaging substrates;
fixing a wafer or other noncircular elements on each layer of packaging substrate, wherein the wafer or other noncircular elements can be fixed on one surface or the upper surface and the lower surface of the packaging substrate; the wafer on the packaging substrate is connected with the packaging substrate through a metal wire bonding process or connected through a copper circuit attached to the packaging substrate; other non-wafer elements are connected with each other or the wafer through copper circuits attached to the packaging substrate;
the packaging substrates are connected through metal conductive pins or metal pads to play a role in electrically connecting and fixing the packaging substrates;
arranging pins on the bottom packaging substrate, wherein the pins can be in the form of a bonding pad supporting a surface mount technology, a metal flat pin or a metal vertical pin supporting a plug-in technology; the high-power heating element or wafer is placed on the topmost or bottommost packaging substrate to facilitate heat dissipation.
10. The SiP 3-dimensional packaging processing method of high power hybrid semiconductor integrated circuit module according to claim 9, comprising the steps of:
the EMC epoxy molding material is used for molding and encapsulating to perform structural reinforcement, insulation, heat conduction, moisture resistance, oxidation resistance and auxiliary fixation of internal components; for products with electromagnetic shielding or accelerated heat dissipation requirements, a metal cover can be sleeved outside the module, the metal cover is connected with the bottom-most packaging substrate, and a metal layer and the metal cover can be manufactured on the bottom surface of the bottom-most packaging substrate to form a nearly closed space; the module is molded and encapsulated in the inner space of the metal cover through EMC epoxy molding material for structure strengthening, insulation, heat conduction, moisture resistance, oxidation resistance and auxiliary fixation of internal components; if the metal cover is provided, the size of the aperture and the number of the metal holes on the metal cover are designed accurately according to electromagnetic shielding requirements and mold sealing process requirements, so that the EMC epoxy mold sealing process and electromagnetic shielding requirements are supported.
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Application publication date: 20200911 |