CN111653301A - A Wide Voltage SRAM Sensitive Amplifier - Google Patents

Abstract

The invention provides a wide-voltage SRAM sense amplifier, which belongs to the technical field of special integrated circuit design. The sense amplifier includes: a polarity storage unit, a polarity switching unit, a main circuit of the sense amplifier, and a data output unit; wherein, the polarity switching unit and the main circuit of the sense amplifier form a single-ended sense amplifier, and only one read bit line is needed, and the in-position When the line voltage is not discharged, the offset polarity is detected and stored. The polarity switching unit controls one input terminal of the main circuit of the sense amplifier to connect to the bit line signal and the other input terminal to connect to the working voltage according to the offset polarity. No additional reference is required. It avoids the design complexity caused by the reference voltage generation circuit, improves the reliability of the design, and reduces the bit line swing required for detection by half, thereby improving the performance and energy efficiency of the SRAM.

Description

A Wide Voltage SRAM Sensitive Amplifier

technical field

The invention relates to the technical field of special integrated circuit design, in particular to a wide voltage SRAM sense amplifier.

Background technique

With the rapid popularization of consumer electronics such as smartphones, the demand for high-performance and low-power system on chip (SoC) continues to rise, and near-threshold wide-voltage designs are the best choice for high-performance and low-power designs . As an important component of SoC, wide-voltage Static Random Access Memory (SRAM) has become a research hotspot in the industry, and Sense Amplifier (SA) determines the speed, power consumption and stability of SRAM, so it needs careful attention. design. The design difficulties of wide voltage sense amplifiers mainly include: (1) Under low voltage, single-ended read structure memory cells appear, and traditional differential sense amplifiers are incompatible with them; (2) In order to ensure the detection yield, SA timing control needs to set aside enough margin, resulting in excessive bit line swing and increased power consumption.

In order to adapt to the changeable memory cell structure, a general single-ended sense amplifier needs to be designed. The conventional single-ended sense amplifier needs to provide an additional reference voltage, and requires a larger bit line voltage swing than the differential sense amplifier, which not only increases the The complexity of the design also reduces the performance and energy efficiency of the SRAM. Southeast University's 2016 master thesis "Research and Implementation of Wide-Voltage SRAM Sensitive Amplifier" proposed a pseudo-differential sense amplifier with reference voltage self-selection suitable for wide-voltage SRAM. The circuit is based on the calibration principle of compensation voltage. Offset polarity of the sense amplifier, select different reference voltages connected to the sense amplifier, so as to realize the compensation of the offset voltage of the sense amplifier. However, this solution requires a complex reference voltage generation circuit, and different reference voltages need to be configured according to different working voltages, which greatly increases the design complexity. At the same time, the reference voltage generation circuit has poor resistance to process deviations. There are certain risks. Therefore, a more concise and efficient method for compensating the offset of the single-ended sense amplifier needs to be designed to improve the reliability of the circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a wide-voltage SRAM sense amplifier in order to overcome the deficiencies of the prior art. The sense amplifier includes: a polarity storage unit, a polarity switching unit, a main body circuit of the sense amplifier, and a data output unit; wherein , The polarity switching unit and the main circuit of the sense amplifier form a single-ended sense amplifier. Only one read bit line is needed to detect and store the offset polarity when the bit line voltage is not discharged. The polarity switching unit controls the sense amplifier according to the offset polarity. One input terminal of the main circuit is connected to the bit line signal, and the other input terminal is connected to the working voltage, so there is no need to provide additional reference voltage, thus avoiding the design complexity brought by the reference voltage generating circuit, improving the reliability of the design, and at the same time The bit line swing required for detection is halved, improving SRAM performance and energy efficiency.

In order to solve the above-mentioned technical problems, the present invention proposes the following technical solutions:

A wide-voltage SRAM sense amplifier proposed by the present invention includes a polarity storage unit, a polarity switching unit, a main circuit of the sense amplifier, and a data output unit. Among them, the polarity switching unit and the main circuit of the sense amplifier form a single-ended sense amplifier circuit structure, and only one read bit line is required.

The first input end of the main circuit of the sense amplifier is connected to the positive voltage signal, the second input end is connected to the negative electrode voltage signal, the third input end is connected to the precharge signal, the fourth input end is connected to the sense amplifier enable signal, and the first output The terminal outputs a detection positive value signal, and the second output terminal outputs a detection negative value signal.

The positive voltage signal is provided by the first output terminal of the polarity switching unit, and the negative voltage signal is provided by the second output terminal of the polarity switching unit.

Further, the first input end of the polarity switching unit is connected to the bit line signal, the second input end is connected to the positive bias flag signal, and the third input end is connected to the negative bias flag signal.

Furthermore, the positive bias flag signal is provided by the first output terminal of the polarity storage unit, and the negative bias flag signal is provided by the second output terminal of the polarity memory unit.

Furthermore, both the first input terminal and the second input terminal of the polarity storage unit are connected to the polarity storage signal, the third input terminal is connected to the detection positive value signal, and the fourth input terminal is connected to the detection negative value signal.

Further, the first input terminal of the data output unit is connected to the detection positive value signal, the second input terminal is connected to the detection negative value signal, the third input terminal is connected to the positive bias flag signal, and the output terminal of the data output unit outputs data. output signal.

The polar memory unit includes: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor.

Further, the source of the first PMOS tube and the source of the second PMOS tube are connected to the working voltage; the gate of the first PMOS tube and the drain of the second PMOS tube, the gate of the second NMOS tube, the third NMOS tube The drain of the tube and the source of the fourth NMOS tube are connected to the positive bias flag signal; the drain of the first PMOS tube is connected to the gate of the second PMOS tube, the source of the first NMOS tube, and the drain of the second NMOS tube The gate electrode and the gate of the third NMOS tube are connected to the negative bias flag signal; the gate of the first NMOS tube and the gate of the fourth NMOS tube are connected to the polarity storage signal; the source of the second NMOS tube and the third NMOS tube are connected to the polarity storage signal; The sources of the tubes are all grounded; the drain of the first NMOS tube is connected to detect positive signals; the drain of the fourth NMOS tube is connected to detect negative signals.

The polarity switching unit includes: a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate.

Further, the input end of the first transmission gate and the input end of the fourth transmission gate are both connected to the working voltage, the input end of the second transmission gate and the input end of the third transmission gate are both connected to the bit line signal; the output end of the first transmission gate The output terminal of the second transmission gate is connected to the positive voltage signal, the output terminal of the third transmission gate and the output terminal of the fourth transmission gate are both connected to the negative voltage signal; the positive control terminal of the first transmission gate is connected to the positive bias flag signal, The negative control end of the first transmission gate is connected to the reverse bias flag signal; the positive control end of the second transmission gate is connected to the reverse bias flag signal, and the negative control end of the second transmission gate is connected to the positive bias flag signal; The positive control terminal is connected to the positive bias flag signal, the negative control terminal of the third transmission gate is connected to the reverse bias flag signal; the positive control terminal of the fourth transmission gate is connected to the reverse bias flag signal, and the negative control terminal of the fourth transmission gate is connected to the positive Bias flag signal.

The main circuit of the sense amplifier includes: the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the fifth NMOS tube, the sixth NMOS tube, and the seventh NMOS tube , a first inverter, a fifth transmission gate, and a sixth transmission gate.

Further, the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the working voltage; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and the gate of the fifth PMOS tube is precharged Signal; the drain of the third PMOS tube and the source of the fifth PMOS tube, the drain of the seventh PMOS tube, the gate of the eighth PMOS tube, the drain of the fifth NMOS tube, the gate of the sixth NMOS tube, The output terminals of the fifth transmission gate are all connected to detect positive signals; the drain of the fourth PMOS tube and the drain of the fifth PMOS tube, the gate of the seventh PMOS tube, the drain of the eighth PMOS tube, and the fifth NMOS tube The gate of the sixth NMOS tube, the drain of the sixth NMOS tube, and the output end of the sixth transmission gate are all connected to the detection inverse signal; the source of the sixth PMOS tube is connected to the working voltage, and the gate of the sixth PMOS tube is connected to the first inverter. The output terminal of the fifth transmission gate, the positive control terminal of the fifth transmission gate, and the positive control terminal of the sixth transmission gate are connected to the same point; the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube and the source of the eighth PMOS tube At the same point; the source of the fifth NMOS transistor is connected to the same point as the source of the sixth NMOS transistor and the drain of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the input end of the first inverter and the drain of the seventh NMOS transistor. The negative control terminal of the fifth transmission gate and the negative control terminal of the sixth transmission gate are connected to the enable signal of the sense amplifier; the source of the seventh NMOS transistor is grounded; the input terminal of the fifth transmission gate is connected to the positive voltage signal; The input terminal is connected to the negative voltage signal.

A fifth transmission gate and a sixth transmission gate are respectively conducted between the internal node of the main circuit of the sense amplifier and the first input end and the second input end, and a sixth PMOS tube is also configured at the working power supply end to control the conduction of the working power supply. Therefore, the input signal voltage of the main circuit of the sense amplifier can be transmitted to the internal node regardless of the level without threshold loss, so as to adapt to the low-voltage working environment.

The data output unit includes: a first NAND gate, a second NAND gate, and a first data selector.

Further, the first input terminal of the first NAND gate is connected to the input detection positive signal, and the second input terminal of the first NAND gate is connected with the output terminal of the second NAND gate and the second input terminal of the first data selector. at the same point; the output end of the first NAND gate is connected to the same point with the first input end of the second NAND gate and the first input end of the first data selector; the second input end of the second NAND gate is connected The input detection inverse value signal; the data control terminal of the first data selector is connected to the positive bias flag signal, and the output terminal of the first data selector is connected to the data output signal.

In a wide-voltage SRAM pseudo-differential sense amplifier proposed by the present invention, the working state of the main circuit of the sense amplifier when detecting the positive and negative polarities of the offset voltage is the polarity detection mode; the working state of the main circuit of the sense amplifier in the SRAM read operation for normal working mode.

In the polarity detection mode, the polarity switching unit realizes that the positive voltage signal is connected to the working voltage, the negative voltage signal is connected to the bit line signal, or the positive voltage signal is connected to the bit line signal according to the positive bias flag signal and the negative bias flag signal. The bit line signal and the negative voltage signal are connected to the working voltage. In the polarity detection mode, the SRAM does not perform read and write operations, so the bit line signal remains high, and the main circuit of the sense amplifier detects the positive and negative polarity of its own offset voltage. When the polarity storage signal changes from a low level When converted to a high level, the polarity detection results, that is, the detection of the positive value signal and the detection of the negative value signal, are stored in the polarity storage unit.

In the normal working mode, the polarity storage unit firstly configures the positive bias flag signal and the negative bias flag signal according to the detection results in the polarity detection mode, that is, detects the positive value signal and detects the negative value signal, and then configures the positive bias flag signal and the negative bias flag signal respectively. According to the positive bias flag signal and the negative bias flag signal, the polarity switching unit realizes that the positive voltage signal is connected to the working voltage, the negative voltage signal is connected to the bit line signal, or the positive voltage signal is connected to the bit line signal and the negative voltage. The voltage signal is connected to the working voltage; in the normal working mode, the SRAM memory array starts to work, and the discharge of the bit line signal is determined by the data stored in the current access memory cell. Regardless of whether the bit line signal voltage is discharged, there is no need to provide an additional reference voltage. can get the correct data output signal.

In the normal working mode, the bit line is not discharged during SRAM read operation, and the detection of the bit line voltage includes:

Case 1: When the offset polarity is positive, the positive bias flag signal is high level, the negative bias flag signal is low level, and the polarity switching unit realizes that the positive voltage signal is connected to the working voltage and the negative voltage signal is connected Bit line signal, so the input voltage difference of the main circuit of the sense amplifier is zero; the polarity detection result is determined by the offset polarity, that is, the detection positive signal is low level, the detection negative signal is high level, and the output data signal is high level.

Case 2: When the offset polarity is negative, the positive bias flag signal is low level, the negative bias flag signal is high level, and the polarity switching unit realizes that the positive polarity voltage signal is connected to the bit line signal, and the negative polarity voltage signal is connected to the bit line signal. Therefore, the input voltage difference of the main circuit of the sense amplifier is zero; the polarity detection result is determined by the offset polarity, that is, the detection positive signal is high level, the detection negative signal is low level, and the output data signal is high level.

In the normal working mode, the bit line is discharged to the first low level during the SRAM read operation, and the detection of the bit line voltage includes:

Case 3: When the offset polarity is positive, the positive bias flag signal is high level, the negative bias flag signal is low level, the positive voltage signal is connected to the working voltage, and the negative voltage signal is connected to the bit line signal is the first A low level, so the input voltage difference of the main circuit of the sense amplifier is the voltage difference between the working voltage and the first low level; the polarity detection result is: the detected positive value signal is high level, and the detected negative value signal is low level , The output data signal is low level.

Case 4: When the offset polarity is negative, the positive bias flag signal is low level, the negative bias flag signal is high level, the positive polarity voltage signal access bit line signal is the first low level, the negative polarity voltage signal Connect to the working voltage, so the input voltage difference of the main circuit of the sense amplifier is the voltage difference between the working voltage and the first low level; the polarity detection result is: the detection positive signal is a low level, and the detection negative signal is a high level , The output data signal is low level.

Further, in order to ensure the correctness of detection, the maximum value of the first low level is VDD-6σ, where VDD is the working voltage, and σ is the standard deviation of the distribution of the offset voltage determined by probabilistic means; when the bit line is discharged to the first low level In the case of the voltage level, in order to meet the discharge time of the storage array, the swing of the bit line is only VDD-6σ. Compared with the prior art, the required swing of the bit line is reduced by half, thereby improving the performance and energy efficiency of the SRAM.

The wide-voltage SRAM sense amplifier proposed by the present invention includes two working modes, namely, a polarity detection mode and a normal working mode. After each power-on of the SRAM, first work in the polarity detection mode to detect the polarity of the offset voltage, switch the polarity of the input signal of the sense amplifier according to the detection result, and then enter the normal working mode until the power is turned off.

Among them, the specific working steps of the polarity detection mode are as follows:

Step A1: The precharge signal is converted from a low level to a high level. In the polarity detection mode, the SRAM memory array does not work, that is, the bit line signal is not discharged and remains at a high level; at this time, the positive voltage signal and the negative voltage signal Both are working power supply voltages, so the input voltage difference of the main circuit of the sense amplifier is zero;

Step A2: When the enable signal of the sense amplifier is converted from a low level to a high level, the offset polarity of the main circuit of the sense amplifier is detected: if the offset polarity is positive, the detection positive signal is set to a low level, and the detection The negative value signal is set to high level; if the offset polarity is negative, the detection positive value signal is set to high level, and the detection negative value signal is set to low level;

Step A3: The polarity storage signal is converted from a low level to a high level, and the detection result of the offset polarity is written into the polarity storage unit: if the offset polarity is positive, the positive bias flag signal is set to a high level, The negative bias flag signal is set to low level; if the offset polarity is negative, the positive bias flag signal is set to low level, and the negative bias flag signal is set to high level;

Step A4: The polarity storage signal is converted from a high level to a low level, and the detection result of the offset polarity is latched inside the polarity storage unit; at this time, the transmission gate in the polarity switching unit is controlled according to the detection result; Set the flag signal to high level and the negative bias flag signal to be low level, then the first transmission gate and the third transmission gate are turned on, the second transmission gate and the fourth transmission gate are turned off, and the positive voltage signal is connected to the working The power supply voltage and the negative voltage signal are connected to the bit line signal; if the positive bias flag signal is low and the negative bias flag signal is high, the first transmission gate and the third transmission gate are turned off, and the second transmission gate and the fourth transmission gate is turned on, the positive voltage signal is connected to the bit line signal, and the negative voltage signal is connected to the working voltage;

Step A5: The sense amplifier enable signal is converted from high level to low level, and the precharge signal is converted from high level to low level at the same time, the detection positive value signal and the detection negative value signal are charged to high level, the sense amplifier The main body circuit returns to the initial state.

The specific working steps of the normal working mode are as follows:

Step S1: The precharge signal is converted from a low level to a high level. In the normal working mode, the SRAM memory array starts to work, and the discharge of the bit line signal is determined by the data stored in the current access memory cell. The working voltage and the bit line signal potential According to the detection results in the polarity detection mode, the positive voltage signal or the negative voltage signal will be respectively input;

Step S2: the sense amplifier enable signal is converted from a low level to a high level, the bit line signal is detected, and the detection result is output from the data output unit;

Step S3: the enable signal of the sense amplifier is converted from high level to low level, and the precharge signal is converted from high level to low level at the same time, the detection positive value signal and the detection negative value signal are both charged to high level, and the sensitivity The main circuit of the amplifier is restored to its initial state.

Compared with the prior art, the wide voltage SRAM sense amplifier proposed by the present invention has the following benefits:

1. There is no need to design an additional reference voltage generating circuit, which reduces the complexity of the design and improves the reliability of the design.

2. It is suitable for application scenarios of various memory cells, and the required bit line swing is only half of the conventional single-ended sense amplifier, which improves the performance and energy efficiency of SRAM.

Description of drawings

1 is a circuit structure diagram of a wide voltage SRAM sense amplifier proposed by the present invention;

FIG. 2 is a working waveform diagram of a wide voltage SRAM sense amplifier circuit proposed by the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the embodiments.

Example 1. According to the circuit structure of a wide voltage SRAM sense amplifier proposed by the present invention shown in FIG. 1 , it can be seen that the sense amplifier includes: a polarity storage unit, a polarity switching unit, a main circuit of the sense amplifier, and a data output unit. Among them, the polarity switching unit and the main circuit of the sense amplifier form a single-ended sense amplifier circuit structure, and only one read bit line is required.

The wide voltage SRAM sense amplifier has five input terminals, wherein: the first input terminal and the second input terminal are connected to the polarity storage signal SAVE, the third input terminal is connected to the bit line signal BL, and the fourth input terminal is connected to the precharge The signal PRE and the fifth input terminal are connected to the sense amplifier enable signal SAE, and the wide voltage SRAM pseudo-differential sense amplifier takes the output data signal Q as the output.

Example 2. The polarity storage unit has four input terminals and two output terminals, the first input terminal and the second input terminal are connected to the polarity storage signal SAVE, the third input terminal is connected to the detection positive signal SD, and the fourth input terminal is connected to The negative value signal NSD is detected, the first output terminal takes the positive bias marker signal PB as the output, and the second output terminal takes the negative offset marker signal NB as the output.

The polar memory unit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4.

Further, the source of the first PMOS transistor P1 and the source of the second PMOS transistor P2 are connected to the working voltage; the gate of the first PMOS transistor P1 and the drain of the second PMOS transistor P2, and the gate of the second NMOS transistor N2 The anode, the drain of the third NMOS transistor N3, and the source of the fourth NMOS transistor N4 are all connected to the positive bias flag signal PB; the drain of the first PMOS transistor P1 is connected to the gate of the second PMOS transistor P2, the first NMOS transistor The source of N1, the drain of the second NMOS transistor N2, and the gate of the third NMOS transistor N3 are all connected to the negative bias flag signal NB; the gate of the first NMOS transistor N1 and the gate of the fourth NMOS transistor N4 are both connected The polarity storage signal SAVE; the source of the second NMOS transistor N2 and the source of the third NMOS transistor N3 are both grounded; the drain of the first NMOS transistor N1 is connected to the detection positive signal SD; the drain of the fourth NMOS transistor N4 is connected to The inverse signal NSD is detected.

The polarity storage unit is used for storing the detection result of the offset polarity of the main circuit of the sense amplifier. In conjunction with the waveforms of the polarity storage signal SAVE, the positive bias flag signal PB, the negative bias flag signal NB, the detection positive value signal SD and the detection negative value signal NSD under the polarity detection mode in FIG. working principle:

When the polarity storage signal SAVE is converted from low level to high level, the polarity storage unit starts to write the detection result of the offset polarity of the main circuit of the sense amplifier: if the offset polarity is positive, the positive bias flag signal PB is Set to high level, negative bias flag signal NB is set to low level; if offset polarity is negative, positive bias flag signal PB is set to low level, negative bias flag signal NB is set to high level level.

When the polarity storage signal SAVE is converted from a high level to a low level, the detection result of the offset polarity of the main circuit of the sense amplifier is latched inside the polarity storage unit.

Example 3. The polarity switching unit has three input terminals and two output terminals, the first input terminal is connected to the bit line signal BL, the second input terminal is connected to the positive bias flag signal PB, and the third input terminal is connected to the negative bias flag signal NB , the first output terminal takes the positive voltage signal VP as the output, and the second output terminal takes the negative voltage signal VN as the output.

The polarity switching unit includes: a first transmission gate TG_1, a second transmission gate TG_2, a third transmission gate TG_3, and a fourth transmission gate TG_4;

Further, the input end of the first transmission gate TG_1 and the input end of the fourth transmission gate TG_4 are both connected to the working voltage, and the input end of the second transmission gate TG_2 and the input end of the third transmission gate TG_3 are both connected to the bit line signal BL; The output terminal of the transmission gate TG_1 and the output terminal of the second transmission gate TG_2 are both connected to the positive voltage signal VP, and the output terminal of the third transmission gate TG_3 and the output terminal of the fourth transmission gate TG_4 are both connected to the negative voltage signal VN; the first transmission gate The positive control terminal of TG_1 is connected to the positive bias flag signal PB, the negative control terminal of TG_1 of the first transmission gate is connected to the reverse bias flag signal NB; the positive control terminal of the second transmission gate TG_2 is connected to the reverse bias flag signal NB, and the second transmission gate is connected to the reverse bias flag signal NB. The negative control end of the gate TG_2 is connected to the positive bias flag signal PB; the positive control end of the third transmission gate TG_3 is connected to the positive bias flag signal PB, and the negative control end of the third transmission gate TG_3 is connected to the reverse bias flag signal NB; The positive control terminal of the transmission gate TG_4 is connected to the reverse bias flag signal NB, and the negative control terminal of the fourth transmission gate TG_4 is connected to the positive bias flag signal PB.

The polarity switching unit switches the polarity of the input signal of the main circuit of the sense amplifier according to the offset polarity stored in the polarity storage unit. Combined with the waveforms of the polarity storage signal SAVE, the positive bias flag signal PB, and the negative bias flag signal NB in the polarity detection mode in FIG. 2, the working principle of the polarity switching unit is further explained:

If the positive bias flag signal PB is at a high level and the negative bias flag signal NB is at a low level, the first transmission gate TG_1 and the third transmission gate TG_3 are turned on, and the second transmission gate TG_2 and the fourth transmission gate TG_4 are turned off At this time, the positive voltage signal VP is connected to the working voltage, and the negative voltage signal VN is connected to the bit line signal BL; if the positive bias flag signal PB is low level and the negative bias flag signal NB is high level, then the first The first transmission gate TG_1 and the third transmission gate TG_3 are turned off, the second transmission gate TG_2 and the fourth transmission gate TG_4 are turned on, the positive voltage signal VP is connected to the bit line signal BL, and the negative voltage signal VN is connected to the working voltage.

Example 4. The main circuit of the sense amplifier has four input terminals and two output terminals. The first input terminal is connected to the positive voltage signal VP, the second input terminal is connected to the negative voltage signal VN, the third input terminal is connected to the precharge signal PRE, and the fourth input terminal is connected to the precharge signal PRE. The input end is connected to the sense amplifier enable signal SAE, the first output end takes the detection positive value signal SD as the output, and the second output end takes the detection negative value signal NSD as the output.

The main circuit of the sense amplifier includes: the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the seventh PMOS transistor P7, the eighth PMOS transistor P8, the fifth NMOS transistor N5, the sixth NMOS transistor N6, seventh NMOS transistor N7, first inverter INV_1, fifth transmission gate TG_5, sixth transmission gate TG_6.

Further, the source of the third PMOS transistor N3 and the source of the fourth PMOS transistor N4 are both connected to the working voltage; the gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4 and the gate of the fifth PMOS transistor P5 The electrodes are all connected to the precharge signal PRE; the drain of the third PMOS transistor P3 is connected to the source of the fifth PMOS transistor P5, the drain of the seventh PMOS transistor P7, the gate of the eighth PMOS transistor P8, and the drain of the fifth NMOS transistor N5. The drain, the gate of the sixth NMOS transistor N6, and the output end of the fifth transmission gate TG_5 are all connected to the detection positive signal SD; the drain of the fourth PMOS transistor P4 is connected to the drain of the fifth PMOS transistor P5 and the seventh PMOS transistor The gate of P7, the drain of the eighth PMOS transistor P8, the gate of the fifth NMOS transistor N5, the drain of the sixth NMOS transistor N6, and the output end of the sixth transmission gate TG_6 are all connected to the detection inverse signal NSD; The source of the PMOS transistor P6 is connected to the working voltage, and the gate of the sixth PMOS transistor P6 is connected to the output terminal of the first inverter INV_1, the positive control terminal of the fifth transmission gate TG_5, and the positive control terminal of the sixth transmission gate TG_6. The same point; the drain of the sixth PMOS transistor P6 is connected to the same point with the source of the seventh PMOS transistor P7 and the source of the eighth PMOS transistor P8; the source of the fifth NMOS transistor N5 is connected to the source of the sixth NMOS transistor N6 pole and the drain of the seventh NMOS transistor N7 are connected to the same point; the gate of the seventh NMOS transistor N7 is connected to the input terminal of the first inverter INV_1, the negative control terminal of the fifth transmission gate TG_5, and the input terminal of the sixth transmission gate TG_6. The negative control terminals are connected to the sense amplifier enable signal SAE; the source of the seventh NMOS transistor N7 is grounded; the input terminal of the fifth transmission gate TG_5 is connected to the positive voltage signal VP; the input terminal of the sixth transmission gate TG_6 is connected to the negative voltage signal VN.

The fifth transmission gate TG_5 and the sixth transmission gate TG_6 are respectively conducted between the internal node of the main circuit of the sense amplifier and the first input terminal and the second input terminal, and a sixth PMOS transistor P6 is also configured at the working power supply terminal for controlling The power supply is switched on and off, so that the input signal voltage of the main circuit of the sense amplifier can be transmitted to the internal node regardless of the level without threshold loss, so as to adapt to the low voltage working environment.

Example 5. The data output unit has three input terminals and one output terminal. The first input terminal is connected to the detection positive value signal SD, the second input terminal is connected to the detection negative value signal NSD, and the third input terminal is connected to the positive bias flag signal PB as input. , the output terminal takes the data output signal Q as the output.

The data output unit includes: a first NAND gate NAND_1, a second NAND gate NAND_2, and a first data selector MUX_1.

Further, the first input terminal of the first NAND gate NAND_1 is connected to the input detection positive signal SD, the second input terminal of the first NAND gate NAND_1 is connected to the output terminal of the second NAND gate NAND_2, the output terminal of the first data selector MUX_1 The second input terminal is connected to the same point; the output terminal of the first NAND gate NAND_1 is connected to the same point as the first input terminal of the second NAND gate NAND_2 and the first input terminal of the first data selector MUX_1; the second AND The second input terminal of the NOT gate NAND_2 is connected to the input detection inversion signal NSD; the data control terminal of the first data selector MUX_1 is connected to the positive bias flag signal SD, and the output terminal of the first data selector MUX_1 is connected to the data output signal Q.

Example 6. The wide-voltage SRAM sense amplifier proposed by the present invention includes two working modes, namely, a polarity detection mode and a normal working mode. After each power-on of the SRAM, first work in the polarity detection mode to detect the polarity of the offset voltage, switch the polarity of the input signal of the sense amplifier according to the detection result, and then enter the normal working mode until the power is turned off.

The working principle of the wide-voltage SRAM sense amplifier is described in detail with reference to the waveforms in different working modes shown in Figure 2.

Among them, the specific working steps of the polarity detection mode are as follows:

Step A1: The precharge signal PRE is converted from a low level to a high level. In the polarity detection mode, the SRAM memory array does not work, that is, the bit line signal BL is not discharged and remains at a high level; at this time, the positive voltage signals VP and The negative voltage signal VN is the working power supply voltage, so the input voltage difference of the main circuit of the sense amplifier is zero;

Step A2: When the sense amplifier enable signal SAE is converted from a low level to a high level, the offset polarity of the main circuit of the sense amplifier is detected: if the offset polarity is positive, the detection positive signal SD is set to a low level , the detection negative value signal NSD is set to high level; if the offset polarity is negative, the detection positive value signal SD is set to high level, and the detection negative value signal NSD is set to low level;

Step A3: The polarity storage signal SAVE is converted from a low level to a high level, and the detection result of the offset polarity is written into the polarity storage unit: if the offset polarity is positive, the positive bias flag signal PB is set to a high level. If it is flat, the negative bias flag signal NB is set to low level; if the offset polarity is negative, the positive bias flag signal PB is set to low level, and the negative bias flag signal NB is set to high level;

Step A4: The polarity storage signal SAVE is converted from high level to low level, and the detection result of the offset polarity is latched inside the polarity storage unit; at this time, the transmission gate in the polarity switching unit is controlled according to the detection result; When the bias flag signal PB is at a high level and the negative bias flag signal NB is at a low level, the first transmission gate TG_1 and the third transmission gate TG_3 are turned on, the second transmission gate TG_2 and the fourth transmission gate TG_4 are turned off, The positive voltage signal VP is connected to the working power supply voltage, and the negative voltage signal VN is connected to the bit line signal BL; if the positive bias flag signal PB is low level and the negative bias flag signal NB is high level, the first transmission gate TG_1 and the third transmission gate TG_3 are turned off, the second transmission gate TG_2 and the fourth transmission gate TG_4 are turned on, the positive voltage signal VP is connected to the bit line signal BL, and the negative voltage signal VN is connected to the working voltage;

Step A5: The sense amplifier enable signal SAE is converted from a high level to a low level, while the precharge signal PRE is converted from a high level to a low level, the detection positive signal SD and the detection negative signal NSD are charged to a high level flat, the main circuit of the sense amplifier returns to the initial state.

The specific working steps of the normal working mode are as follows:

In step S1, the precharge signal PRE is converted from a low level to a high level. In the normal working mode, the SRAM memory array starts to work, and the discharge condition of the bit line signal BL is determined by the data stored in the current access memory cell. The working voltage and the bit line The signal potential will be respectively transmitted to the positive voltage signal VP or the negative voltage signal VN according to the detection result in the polarity detection mode;

Step S2, the sense amplifier enable signal SAE is converted from a low level to a high level, the bit line signal BL is detected, and the detection result is output from the data output unit;

Step S3, the sense amplifier enable signal SAE is converted from a high level to a low level, and the precharge signal PRE is converted from a high level to a low level at the same time, and both the detection positive value signal SD and the detection negative value signal NSD are charged to a high level. level, the main circuit of the sense amplifier returns to the initial state.

Example 7. In the wide voltage SRAM sense amplifier proposed by the present invention, the working state of the main circuit of the sense amplifier when detecting the positive and negative polarity of the offset voltage is the polarity detection mode; the working state of the main circuit of the sense amplifier during the SRAM read operation is normal Operating mode.

In the polarity detection mode, the polarity switching unit realizes that the positive voltage signal VP is connected to the working voltage VDD and the negative voltage signal VN is connected to the bit line signal BL according to the positive bias flag signal PB and the negative bias flag signal NB. , or the positive voltage signal VP is connected to the bit line signal BL, and the negative voltage signal VN is connected to the working voltage VDD. In the polarity detection mode, the SRAM does not perform read and write operations, so the bit line signal BL remains high, and the main circuit of the sense amplifier detects the positive and negative polarity of its own offset voltage. When the polarity storage signal SAVE changes from low to low When the level is converted to a high level, the polarity detection results, that is, the detection positive value signal SD and the detection negative value signal NSD, are stored in the polarity storage unit.

In the normal working mode, the polarity storage unit firstly detects the positive bias signal PB and the negative bias flag signal NB according to the detection results in the polarity detection mode, that is, the detection positive signal SD and the negative detection signal NSD, respectively. The configuration is performed, and then the polarity switching unit realizes that the positive voltage signal VP is connected to the working voltage VDD, the negative voltage signal VN is connected to the bit line signal BL, or the positive voltage signal is connected to the bit line signal BL according to the positive bias flag signal PB and the negative bias flag signal NB. The negative voltage signal VP is connected to the bit line signal BL, and the negative voltage signal VN is connected to the working voltage VDD; in the normal working mode, the SRAM memory array starts to work, and the discharge of the bit line signal BL is determined by the data stored in the current access memory cell , no matter whether the voltage of the bit line signal BL is discharged or not, a correct data output signal can be obtained without additionally providing a reference voltage.

In this preferred embodiment, a conventional sense amplifier whose offset voltage Voffset is distributed in the range of (-6σ, 6σ) is taken as an example, where σ is the standard deviation of Voffset.

In the prior art, when the single-ended bit line voltage is detected, an additional reference voltage Vref needs to be provided at another differential input terminal. To ensure correct detection, the maximum value of Vref is VDD-6σ, where VDD is the working voltage; At this time, the discharge time of the storage array is required to meet the requirement that the swing of the bit line reaches VDD-12σ.

The present invention does not need to provide a reference voltage, and only needs the discharge time of the storage array to meet the requirement that the bit line swing reaches VDD-6σ. Therefore, compared with the prior art, the required bit line swing is reduced by half, thereby improving the performance of the SRAM and energy efficiency.

In the normal working mode, the bit line is not discharged during SRAM read operation, and the detection of the bit line voltage includes:

Case 1: The offset polarity of the sense amplifier is positive, the bit line is not discharged during the SRAM read operation, and remains at the working voltage VDD; at this time, the positive bias flag signal PB obtained in the polarity detection mode is high level, negative bias The flag signal NB is low level, the positive voltage signal VP is connected to the working voltage, and its voltage is VDD, and the negative voltage signal VN is connected to the bit line signal, and its voltage is VDD, so the input voltage difference of the sense amplifier is zero ; At this time, the detection result of the offset polarity is determined by the offset polarity of the sense amplifier, that is, the detection positive value signal SD is low level, the detection negative value signal NSD is high level, the data selector MUX_1 selects the first NAND gate The output of NAND_1 is used as the final output data signal Q, which is a high level.

Case 2: The offset polarity of the sense amplifier is negative, the bit line is not discharged during the SRAM read operation, and remains at the working voltage VDD; at this time, the positive bias flag signal PB obtained in the polarity detection mode is low level, negative bias The flag signal NB is high level, the positive voltage signal VP is connected to the bit line signal BL, and its voltage is VDD, and the negative voltage signal VN is connected to the working voltage, and its voltage is VDD, so the input voltage difference of the sense amplifier is 0 ; At this time, the detection result of the offset polarity is determined by the offset polarity of the sense amplifier, that is, the detection positive value signal SD is high level, the detection negative value signal NSD is low level, and the data selector MUX_1 selects the second NAND gate The output of NAND_2 is used as the final output data signal Q, which is a high level.

In normal working mode, the bit line is discharged to VDD-6σ during SRAM read operation, and the detection of the bit line voltage includes:

Case 3: The offset polarity of the sense amplifier is positive, and the bit line is discharged to VDD-6 σ during SRAM read operation; at this time, the positive bias flag signal PB obtained in the polarity detection mode is high, and the negative bias flag signal NB is low level, the positive voltage signal VP is connected to the working voltage, and its voltage is VDD, and the negative voltage signal VN is connected to the bit line signal BL, and its voltage is VDD-6σ. Therefore, the input voltage difference of the sense amplifier is 6σ. ; At this time, the detection result of the offset polarity is that the detection positive value signal SD is high level, the detection negative value signal NSD is low level, and the data selector MUX_1 selects the output of the first NAND gate NAND_1 as the final output data signal Q, which is low level.

Case 4: The offset polarity of the sense amplifier is negative, and the bit line is discharged to VDD-6 σ during SRAM read operation; at this time, the positive bias flag signal PB obtained in the polarity detection mode is low level, and the negative bias flag signal NB is high level, the positive voltage signal VP is connected to the bit line signal BL, and its voltage is VDD-6σ, and the negative voltage signal VN is connected to the working voltage, and its voltage is VDD. Therefore, the input voltage difference of the sense amplifier is - 6σ; at this time, the detection result of the offset polarity is that the detection positive value signal SD is low level, the detection negative value signal NSD is high level, the data selector MUX_1 selects the output of the second NAND gate NAND_2 as the final output data Signal Q is low level.

The above specific embodiments and examples are specific support for the technical idea of a wide-voltage SRAM sense amplifier proposed by the present invention, and cannot limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made still fall within the protection scope of the technical solutions of the present invention.

Claims (8)

1. A wide-voltage SRAM sense amplifier, comprising: a polarity storage unit, a polarity switching unit, a main body circuit of a sense amplifier, and a data output unit; wherein, the polarity switching unit and the main body circuit of the sense amplifier To form a single-ended sense amplifier circuit structure, only one read bit line is required; The first input end of the main circuit of the sense amplifier is connected to the positive voltage signal, the second input end is connected to the negative electrode voltage signal, the third input end is connected to the precharge signal, the fourth input end is connected to the sense amplifier enable signal, and the third input end is connected to the precharge signal. An output terminal outputs a detected positive value signal, and the second output terminal outputs a detected negative value signal; Wherein, the positive voltage signal is provided by the first output terminal of the polarity switching unit, and the negative voltage signal is provided by the second output terminal of the polarity switching unit; The first input end of the polarity switching unit is connected to the bit line signal, the second input end is connected to the positive bias flag signal, and the third input end is connected to the negative bias flag signal; The positive bias flag signal is provided by the first output end of the polarity storage unit, and the negative bias flag signal is provided by the second output end of the polarity memory unit; The first input terminal and the second input terminal of the polarity storage unit are both connected to the polarity storage signal, the third input terminal is connected to the detected positive value signal, and the fourth input terminal is connected to the detected negative value Signal; The first input terminal of the data output unit is connected to the detection positive value signal, the second input terminal is connected to the detection negative value signal, the third input terminal is connected to the positive bias flag signal, and the data The output terminal of the output unit outputs the data output signal; The working state of the main circuit of the sense amplifier when detecting the positive and negative polarities of the offset voltage is a polarity detection mode; in the polarity detection mode, the polarity switching unit is based on the positive bias flag signal and The negative bias flag signal realizes that the positive voltage signal is connected to the working voltage, the negative voltage signal is connected to the bit line signal, or the positive voltage signal is connected to the bit line signal and the negative voltage The signal is connected to the working voltage; in the polarity detection mode, the SRAM does not perform read and write operations, the bit line signal remains high, and the main circuit of the sense amplifier detects the positive and negative polarity of its own offset voltage. When the polarity storage signal is converted from a low level to a high level, the polarity detection results, that is, the detection positive value signal and the detection negative value signal, are stored in the polarity storage unit; The working state of the main circuit of the sense amplifier during the SRAM read operation is the normal working mode; in the normal working mode, the polarity storage unit firstly uses the polarity storage unit according to the detection result in the polarity detection mode, that is, the Detect the positive value signal and the detected negative value signal, respectively configure the positive bias flag signal and the negative bias flag signal, and then use the polarity switching unit according to the positive bias flag signal and the negative bias flag signal. The negative bias flag signal enables the positive voltage signal to be connected to the working voltage, the negative voltage signal to be connected to the bit line signal, or the positive voltage signal to be connected to the bit line signal and the negative voltage signal Access the working voltage; in the normal working mode, the SRAM memory array starts to work, and the discharge of the bit line signal is determined by the data stored in the current access memory cell. Regardless of whether the bit line signal voltage is discharged, no additional reference voltage is required. The correct data output signal can be obtained. 2. a kind of wide voltage SRAM sense amplifier according to claim 1, is characterized in that, In the normal working mode, the bit line is not discharged during the SRAM read operation, and the detection of the bit line voltage includes: Case 1: When the offset polarity is positive, the positive bias flag signal is high level, the negative bias flag signal is low level, and the polarity switching unit realizes the access operation of the positive polarity voltage signal The voltage and the negative voltage signal are connected to the bit line signal, so the input voltage difference of the main circuit of the sense amplifier is zero; the polarity detection result is determined by the offset polarity, that is, the detection positive signal is low level, the Detecting that the negative value signal is a high level, and the output data signal is a high level; Case 2: When the offset polarity is negative, the positive bias flag signal is low level, the negative bias flag signal is high level, and the polarity switching unit implements the positive polarity voltage signal access bit The line signal and the negative voltage signal are connected to the working voltage, so the input voltage difference of the main circuit of the sense amplifier is zero; the polarity detection result is determined by the offset polarity, that is, the detection positive signal is high level, the Detecting that the negative value signal is a low level, and the output data signal is a high level; In the normal working mode, the bit line is discharged to the first low level during the SRAM read operation, and the detection of the bit line voltage includes: Case 3: When the offset polarity is positive, the positive bias flag signal is high, the negative bias flag signal is low, the positive voltage signal is connected to the working voltage, and the negative voltage The signal access bit line signal is the first low level, so the input voltage difference of the main circuit of the sense amplifier is the voltage difference between the working voltage and the first low level; the polarity detection result is: the detected positive value signal is high level level, the detection inverse value signal is a low level, and the output data signal is a low level; Case 4: When the offset polarity is negative, the positive bias flag signal is low level, the negative bias flag signal is high level, and the positive voltage signal access bit line signal is the first low level The negative voltage signal is connected to the working voltage, so the input voltage difference of the main circuit of the sense amplifier is the voltage difference between the working voltage and the first low level; the polarity detection result is: the detected positive signal is a low voltage level, the detected inverse value signal is high level, and the output data signal is low level. 3. A wide-voltage SRAM sense amplifier according to claim 2, characterized in that, in order to ensure the correctness of detection, the value of the first low level is up to VDD-6σ, wherein VDD is the working voltage, and σ is the probability of adoption The standard deviation of the distribution of the offset voltage determined by the scientific method; when the bit line is discharged to the first low level, in order to meet the discharge time of the storage array, the bit line swing is only VDD-6σ. 4 . The wide voltage SRAM sense amplifier according to claim 1 , wherein the polarity storage unit comprises: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a Three NMOS tubes, the fourth NMOS tube; The source of the first PMOS tube and the source of the second PMOS tube are connected to the working voltage; the gate of the first PMOS tube and the drain of the second PMOS tube, the gate of the second NMOS tube, the third NMOS tube The drain of the tube and the source of the fourth NMOS tube are connected to the positive bias flag signal; the drain of the first PMOS tube is connected to the gate of the second PMOS tube, the source of the first NMOS tube, and the drain of the second NMOS tube The gate electrode and the gate of the third NMOS tube are connected to the negative bias flag signal; the gate of the first NMOS tube and the gate of the fourth NMOS tube are connected to the polarity storage signal; the source of the second NMOS tube and the third NMOS tube are connected to the polarity storage signal; The sources of the tubes are all grounded; the drain of the first NMOS tube is connected to detect positive signals; the drain of the fourth NMOS tube is connected to detect negative signals. 5. The wide-voltage SRAM sense amplifier according to claim 1, wherein the polarity switching unit comprises: a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; Wherein, the input end of the first transmission gate and the input end of the fourth transmission gate are both connected to the working voltage, the input end of the second transmission gate and the input end of the third transmission gate are both connected to the bit line signal; the output end of the first transmission gate The output terminal of the second transmission gate is connected to the positive voltage signal, the output terminal of the third transmission gate and the output terminal of the fourth transmission gate are both connected to the negative voltage signal; the positive control terminal of the first transmission gate is connected to the positive bias flag signal, The negative control end of the first transmission gate is connected to the reverse bias flag signal; the positive control end of the second transmission gate is connected to the reverse bias flag signal, and the negative control end of the second transmission gate is connected to the positive bias flag signal; The positive control terminal is connected to the positive bias flag signal, the negative control terminal of the third transmission gate is connected to the reverse bias flag signal; the positive control terminal of the fourth transmission gate is connected to the reverse bias flag signal, and the negative control terminal of the fourth transmission gate is connected to the positive Bias flag signal. 6. a wide voltage SRAM sense amplifier according to claim 5, is characterized in that, In the polarity detection mode, if the positive bias flag signal is high and the negative bias flag signal is low, the first transmission gate and the third transmission in the polarity switching unit The gate is turned on, the second transmission gate and the fourth transmission gate are turned off, the positive voltage signal is connected to the working voltage, and the negative voltage signal is connected to the bit line signal; In the polarity detection mode, if the positive bias flag signal is at a low level and the negative bias flag signal is at a high level, the first transmission gate and the third transmission in the polarity switching unit The gate is turned off, the second transmission gate and the fourth transmission gate are turned on, the positive voltage signal is connected to the bit line signal, and the negative voltage signal is connected to the operating voltage. 7 . The wide-voltage SRAM sense amplifier according to claim 1 , wherein the main circuit of the sense amplifier comprises: a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a Seven PMOS tube, eighth PMOS tube, fifth NMOS tube, sixth NMOS tube, seventh NMOS tube, first inverter, fifth transmission gate, sixth transmission gate; The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the working voltage; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and the gate of the fifth PMOS tube to be precharged Signal; the drain of the third PMOS tube and the source of the fifth PMOS tube, the drain of the seventh PMOS tube, the gate of the eighth PMOS tube, the drain of the fifth NMOS tube, the gate of the sixth NMOS tube, The output terminals of the fifth transmission gate are all connected to detect positive signals; the drain of the fourth PMOS tube and the drain of the fifth PMOS tube, the gate of the seventh PMOS tube, the drain of the eighth PMOS tube, and the fifth NMOS tube The gate of the sixth NMOS tube, the drain of the sixth NMOS tube, and the output end of the sixth transmission gate are all connected to the detection inversion signal; the source of the sixth PMOS tube is connected to the working voltage, and the gate of the sixth PMOS tube is connected to the first inverter. The output end of the fifth transmission gate, the positive control end of the fifth transmission gate, and the positive control end of the sixth transmission gate are connected to the same point; the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube and the source of the eighth PMOS tube At the same point; the source of the fifth NMOS transistor is connected to the same point as the source of the sixth NMOS transistor and the drain of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the input end of the first inverter and the drain of the seventh NMOS transistor. The negative control terminal of the fifth transmission gate and the negative control terminal of the sixth transmission gate are connected to the enable signal of the sense amplifier; the source of the seventh NMOS transistor is grounded; the input terminal of the fifth transmission gate is connected to the positive voltage signal; The input terminal is connected to the negative voltage signal. 8. The wide-voltage SRAM sense amplifier according to claim 1, wherein the data output unit comprises: a first NAND gate, a second NAND gate, and a first data selector; The first input terminal of the first NAND gate is connected to the input detection positive signal, and the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate and the second input terminal of the first data selector. at the same point; the output end of the first NAND gate is connected to the same point with the first input end of the second NAND gate and the first input end of the first data selector; the second input end of the second NAND gate is connected The input detection inverse value signal; the data control terminal of the first data selector is connected to the positive bias flag signal, and the output terminal of the first data selector is connected to the data output signal.

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