CN111653240A

CN111653240A - Pixel driving circuit and driving method thereof, display panel and driving method thereof

Info

Publication number: CN111653240A
Application number: CN202010620160.1A
Authority: CN
Inventors: 董甜
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-09-11

Abstract

The invention relates to the technical field of display, and provides a pixel driving circuit and a driving method thereof, a display panel and a driving method thereof, wherein the pixel driving circuit comprises: the circuit comprises a first input circuit, a second input circuit, a driving circuit, a detection circuit and a storage circuit. The first input circuit is connected with the data signal end, the first control signal end and the first node; the second input circuit is connected with the second control signal end, the sensing signal end and the first node; the driving circuit is connected with the first node, the first power end and the second node and is used for outputting driving current to the second node according to the voltage of the first node; the detection circuit is connected with the first node, the second node and the third control signal end and is used for responding to the signal of the third control signal end to communicate the first node and the second node; and a memory circuit connected between the first power source terminal and the first node. The pixel driving circuit can avoid display ghost caused by hysteresis of the driving transistor.

Description

Pixel driving circuit and driving method thereof, display panel and driving method thereof

Technical Field

The invention relates to the technical field of display, in particular to a pixel driving circuit and a driving method thereof, and a display panel and a driving method thereof.

Background

Each sub-pixel unit in the display panel comprises a pixel driving circuit for driving the light-emitting unit to emit light, and the threshold voltage of a driving transistor in the pixel driving circuit influences the driving current output by the pixel driving circuit. The display panel display is not uniform due to the difference of the threshold voltages of the driving transistors in different pixel driving circuits in the display panel.

In the related art, the threshold of the driving transistor in the pixel driving circuit is usually compensated by using an internal compensation technique and an external compensation technique. Compared with the internal compensation technology, the external compensation technology has a larger threshold compensation range, and meanwhile, the external compensation time is not limited by the line period, so the external compensation technology has better application potential in high frame frequency driving.

However, in the related art, the pixel driving circuit using external compensation may cause a display image sticking phenomenon of the display panel due to the hysteresis characteristic of the driving transistor.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present invention provides a pixel driving circuit and a driving method thereof, a display panel and a driving method thereof, wherein the pixel driving circuit can solve the display afterimage phenomenon of the display panel caused by hysteresis of a driving transistor.

Other features and advantages of the invention will be apparent from the following detailed description, or may be learned by practice of the invention.

According to an aspect of the present invention, there is provided a pixel driving circuit including: the circuit comprises a first input circuit, a second input circuit, a driving circuit, a detection circuit and a storage circuit. The first input circuit is connected with a data signal end, a first control signal end and a first node and is used for responding to a signal of the first control signal end to transmit a signal of the data signal end to the first node; the second input circuit is connected with a second control signal end, a sensing signal end and the first node and is used for responding to a signal of the second control signal end and transmitting a signal of the sensing signal end to the first node; the driving circuit is connected with the first node, a first power supply end and a second node and is used for outputting driving current to the second node according to the voltage of the first node; the detection circuit is connected with the first node, the second node and the third control signal end and is used for responding to the signal of the third control signal end to communicate the first node and the second node; the memory circuit is connected between the first power supply terminal and the first node.

In an exemplary embodiment of the present disclosure, the first input circuit includes a first transistor, a first pole of the first transistor is connected to the data signal terminal, a second pole of the first transistor is connected to the first node, and a gate of the first transistor is connected to the first control signal terminal. The second input circuit comprises a second transistor, wherein a first pole of the second transistor is connected with the sensing signal end, a second pole of the second transistor is connected with the first node, and a grid electrode of the second transistor is connected with the second control signal end. The driving circuit comprises a driving transistor, wherein a first pole of the driving transistor is connected with the first power supply end, a second pole of the driving transistor is connected with the second node, and a grid of the driving transistor is connected with the first node. The storage circuit comprises a storage capacitor connected between said first power supply terminal and said first node. The detection circuit comprises a third transistor, wherein the first pole of the third transistor is connected with the second node, the second pole of the third transistor is connected with the first node, and the grid of the third transistor is connected with the third control signal end.

In an exemplary embodiment of the present disclosure, the first transistor, the second transistor, and the third transistor are oxide thin film transistors or low temperature polysilicon thin film transistors with a dual gate structure.

In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes an isolation circuit, connected to the first node, the first input circuit, the second input circuit, and a sixth control signal terminal, for responding to a signal of the sixth control signal terminal to connect the first input circuit, the second input circuit, and the first node.

In an exemplary embodiment of the disclosure, the isolation circuit includes a sixth transistor, a first pole of the sixth transistor is connected to the first input circuit and the second input circuit, a second pole of the sixth transistor is connected to the first node, and a gate of the sixth transistor is connected to the sixth control signal terminal.

In an exemplary embodiment of the disclosure, the sixth transistor and the third transistor are oxide thin film transistors or low temperature polysilicon thin film transistors with a double gate structure.

According to an aspect of the present invention, there is provided a pixel driving circuit driving method for driving the pixel driving circuit described above, the method comprising:

in the detection phase:

in the reset stage, an invalid level is input to the first control signal end and the third control signal end, an effective level is input to the second control signal end, and a reset signal is input to the sensing signal end;

a threshold establishing stage, inputting an invalid level to a first control signal end, and inputting an effective level to a second control signal end and a third control signal end;

in the sampling stage, an invalid level is input into the first control signal end, and an effective level is input into the second control signal end and the third control signal end;

in the driving stage:

a data writing stage, inputting an invalid level to the second control signal end and the third control signal end, inputting an effective level to the first control signal end, and inputting a data signal end to the data signal end;

and in the light-emitting stage, an invalid level is input to the first control signal end, the second control signal end and the third control signal end.

According to an aspect of the present invention, a display panel is provided, which includes the pixel driving circuit, the light emitting unit and the power control circuit; the power supply control circuit is connected with the first power supply end, the third node, the second power supply end, the fourth control signal end and the fifth control signal end, and is used for responding to the signal of the fourth control signal end to transmit the signal of the first power supply end to the third node and responding to the signal of the fifth control signal end to transmit the signal of the second power supply end to the third node; the light emitting unit is connected between the second node and a third node.

In an exemplary embodiment of the present disclosure, the power control circuit includes a fourth transistor and a fifth transistor, a first electrode of the fourth transistor is connected to the first power terminal, a second electrode of the fourth transistor is connected to the third node, and a gate of the fourth transistor is connected to the fourth control signal terminal; a first electrode of the fifth transistor is connected to the second power terminal, a second electrode of the fifth transistor is connected to the third node, and a gate of the fifth transistor is connected to the fifth control signal terminal.

According to an aspect of the present invention, there is provided a display panel driving method for driving the display panel described above, the method comprising:

inputting an effective level to a fourth control signal end and inputting an ineffective level to a fifth control signal end at the detection stage of the pixel driving circuit;

and in the driving stage of the pixel driving circuit, inputting an invalid level to the fourth control signal terminal and inputting an effective level to the fifth control signal terminal.

The present disclosure provides a pixel driving circuit and a driving method thereof, a display panel and a driving method thereof, the pixel driving circuit including: the circuit comprises a first input circuit, a second input circuit, a driving circuit, a detection circuit and a storage circuit. The first input circuit is connected with a data signal end, a first control signal end and a first node and is used for responding to a signal of the first control signal end to transmit a signal of the data signal end to the first node; the second input circuit is connected with a second control signal end, a sensing signal end and the first node and is used for responding to a signal of the second control signal end and transmitting a signal of the sensing signal end to the first node; the driving circuit is connected with the first node, a first power supply end and a second node and is used for outputting driving current to the second node according to the voltage of the first node; the detection circuit is connected with the first node, the second node and the third control signal end and is used for responding to the signal of the third control signal end to communicate the first node and the second node; the memory circuit is connected between the first power supply terminal and the first node. The pixel driving circuit can avoid display ghost caused by hysteresis of the driving transistor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 is a schematic diagram of a pixel driving circuit in the related art;

FIG. 2 is a timing diagram of nodes of the pixel driving circuit of FIG. 1 during a sensing phase;

FIG. 3 is a timing diagram of nodes of the pixel driving circuit of FIG. 1 during a driving phase;

FIG. 4 is a schematic diagram of an exemplary embodiment of a pixel driving circuit according to the present disclosure;

FIG. 5 is a timing diagram of nodes in the sensing phase of the pixel driving circuit shown in FIG. 4;

FIG. 6 is a timing diagram of nodes of the pixel driving circuit of FIG. 4 during a driving phase;

FIG. 7 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;

FIG. 8 is a timing diagram of nodes in the sensing phase of the pixel driving circuit of FIG. 7;

FIG. 9 is a timing diagram of nodes of the pixel driving circuit of FIG. 7 during a driving phase;

FIG. 10 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;

FIG. 11 is a timing diagram of nodes in the sensing phase of the pixel driving circuit of FIG. 10;

fig. 12 is a timing diagram of each node in the driving phase of the pixel driving circuit in fig. 10.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," and the like are used to denote the presence of one or more elements/components/groups; the terms "comprising" and "having" are used in an inclusive sense and mean that there may be additional elements/components/integers other than the listed elements/components/integers.

Fig. 1 is a schematic structural diagram of a pixel driving circuit in the related art. The pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a driving transistor DT, and a capacitor C. The first pole of the first transistor T1 is connected to the composite signal terminal D/S, the second pole is connected to the first node N1, and the gate is connected to the first control signal terminal CN 1; a first pole of the second transistor T2 is connected to the composite signal terminal D/S, a second pole is connected to the first node N1, and a gate is connected to the second control signal terminal CN 2; the driving transistor DT has a first electrode connected to the first power source terminal VDD, a second electrode connected to the second node N2, and a gate connected to the first node N1; the third transistor T3 has a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate connected to the second control signal terminal CN 2; the capacitor C is connected between the first node N1 and the first power source terminal VDD. The second node N2 of the pixel driving circuit may be connected to a first electrode of a light emitting unit OLED, and a second electrode of the light emitting unit OLED may be connected to a power control circuit 01, and the power control circuit 01 includes a fourth transistor T4 and a fifth transistor T5. A first electrode of the fourth transistor T4 is connected to the first power terminal VDD, a second electrode thereof is connected to the second electrode of the light emitting unit OLED, and a gate thereof is connected to the third control signal terminal CN 3; the fifth transistor T5 has a first electrode connected to the second power source terminal VSS, a second electrode connected to the second electrode of the light emitting unit OLED, and a gate connected to the fourth control signal terminal CN 4. The composite signal terminal D/S of the pixel driving circuit may be connected to the sixth transistor T6, the first pole of the sixth transistor T6 is connected to the initial signal terminal Vinit, the second pole is connected to the composite signal terminal D/S, and the gate is connected to the reset signal terminal Ret.

The first transistor T1, the second transistor T2, the third transistor T3, the driving transistor DT, and the sixth transistor T6 may be P-type transistors, and the fourth transistor T4 and the fifth transistor T5 may be N-type transistors. The first power source terminal may be a high-level power source terminal, and the second power source terminal may be a low-level power source terminal. The power control circuit 01 may be integrated in a PowerIC (power management chip) of the display panel, the sixth transistor T6 may be integrated in a bezel region of the display panel, and the second pole of the sixth transistor T6 may be connected to the plurality of pixel driving circuit complex signal terminals D/S.

The driving method of the pixel driving circuit comprises two stages: a sensing phase and a driving phase. The pixel driving circuit may detect the threshold voltage of the driving transistor DT in the sensing phase, thereby compensating the data signal in the driving phase according to the threshold voltage of the driving transistor DT. As shown in fig. 2 and 3, fig. 2 is a timing diagram of each node of the pixel driving circuit in fig. 1 in the sensing phase, and fig. 3 is a timing diagram of each node of the pixel driving circuit in fig. 1 in the driving phase.

As shown in FIG. 2, Hsync is the timing sequence of the horizontal sync signal in the display panel, Ret is the timing sequence of the reset signal end Ret, CN1 is the timing sequence of the first control signal end CN1, CN2 is the timing sequence of the second control signal end CN2, CN3 is the timing sequence of the third control signal end CN3, CN4 is the timing sequence of the fourth control signal end CN4, D/S is the timing sequence of the composite signal end D/S, N1 is the timing sequence of the first node N1, and Vinit is the timing sequence of the initialization signal end Vinit. Wherein, the falling edges of two adjacent effective pulse signals of the horizontal synchronizing signal Hsync define one period of the sensing phase.

In the sensing phase, the voltage of the third control signal terminal CN3 is continuously at a high level, and the voltage of the fourth control signal terminal CN4 is continuously at a low level. The sensing phase of the pixel drive circuit may comprise three phases: a reset phase T1, a threshold establishment phase T2, and a sampling phase T3. During the reset phase T1: the reset signal terminal Ret and the first control signal terminal CN1 output low levels, and the sixth transistor T6 and the first transistor T1 are turned on; the second control signal terminal CN2 outputs a high level signal, and the second transistor T2 and the third transistor T3 are turned off; the initialization signal terminal Vinit outputs an initialization signal to input an initialization signal to the first node through the first transistor T1, wherein the initialization signal can turn on the driving transistor DT. At the threshold establishment phase T2: the reset signal terminal Ret outputs a high level, and the sixth transistor T6 is turned off; the first control signal terminal CN1 and the second control signal terminal CN2 output low level signals, and the first transistor T1, the second transistor T2 and the third transistor T3 are turned on; the first node N1 gradually increases in voltage by the first power terminal VDD until the voltage of the first node N1 is equal to VDD-Vth, where VDD is the voltage of the first power terminal VDD and Vth is the threshold voltage of the driving transistor DT. In the taking stage T3: the reset signal terminal Ret outputs a high level, and the sixth transistor T6 is turned off; the first control signal terminal CN1 and the second control signal terminal CN2 output low level signals, and the first transistor T1, the second transistor T2 and the third transistor T3 are turned on; the voltage of the first node N1 is stabilized to Vdd Vth, at this time, the composite signal terminal D/S is connected with the first node N1, the voltage of Vdd Vth can be detected by detecting the voltage of the composite signal terminal D/S, and the threshold circuit Vth of the driving transistor can be calculated according to the sampling voltage because Vdd is known.

In the driving phase, the voltage of the third control signal terminal CN3 is continuously at a low level, and the voltages of the reset signal terminal Ret, the second control signal terminal CN2 and the fourth control signal terminal CN4 are continuously at a high level. The driving phase of the pixel driving circuit comprises two phases: data is written in T1, and a light-emitting period T2. In the data writing phase T1: the first control signal terminal CN1 outputs a low level signal, and the composite signal terminal D/S outputs a data signal, which is transmitted to the first node N1 through the first transistor. In the light emitting stage: the driving transistor DT is turned on by the first node to drive the light emitting unit OLED to emit light.

However, the driving transistor exhibits different threshold voltages when the gate voltage of the driving transistor DT is swept from the positive direction to the negative direction and swept from the negative direction to the positive direction due to hysteresis characteristics of the driving transistor. For example, when the initial voltage of the driving transistor is 0V, a-5V driving voltage is applied to the driving transistor, which exhibits a threshold voltage of Vth1, and when the initial voltage of the driving transistor is-10V, a-5V driving voltage is also applied to the driving transistor, which exhibits a threshold voltage of Vth2, where Vth1 is not equal to Vth 2. As can be seen from fig. 3, the pixel driving circuit is a data signal written to the first node N1 based on the first node voltage in the previous light emitting phase in the data writing phase. However, the voltage of the first node is not completely the same in the last light emitting phase of each data writing phase, and thus the driving transistor may show different threshold voltages in the light emitting phase. According to the formula of the output current of the driving transistor, I ═ (mu WCox/2L) (Vgs-Vth)²Wherein μ is the carrier mobility; cox is the gate capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, Vgs is the difference in gate-source voltages of the drive transistors, and Vth is the threshold voltage of the drive transistors. When the threshold circuit of the driving transistor is changed, the output current is also changed, and thus, the pixel driving circuit causes a display image sticking phenomenon due to the change of the threshold of the driving transistor.

Based on this, the present exemplary embodiment provides a pixel driving circuit, as shown in fig. 4, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit includes: a first input circuit 1, a second input circuit 2, a drive circuit 3, a detection circuit 4, and a storage circuit 5. The first input circuit 1 is connected to a data signal terminal Vdata, a first control signal terminal CN1, and a first node N1, and is configured to transmit a signal of the data signal terminal Vdata to the first node N1 in response to a signal of the first control signal terminal CN 1; the second input circuit 2 is connected to a second control signal terminal CN2, a Sense signal terminal Sense, and the first node N1, and is configured to transmit a signal of the Sense signal terminal Sense to the first node N1 in response to a signal of the second control signal terminal CN 2; the driving circuit 3 is connected to the first node N1, a first power source terminal VDD, and a second node N2, and is configured to output a driving current to the second node N2 according to the voltage of the first node N1; the detection circuit 4 is connected to the first node N1, the second node N2 and the third control signal terminal CN3, and is configured to respond to a signal of the third control signal terminal CN3 to connect the first node N1 and the second node N2; the memory circuit 5 is connected between the first power source terminal VDD and the first node N1.

As shown in fig. 4, the pixel driving circuit may be used to drive the light emitting cell OLED to emit light, and the light emitting cell OLED may be connected between the second node N2 and the third node N3. The third node N3 may be connected to a power control circuit 6, and the power control circuit 6 may be connected to the first power terminal VDD, the third node N3, the second power terminal VSS, the fourth control signal terminal CN4, the fifth control signal terminal CN5, for transmitting the first power terminal VDD signal to the third node N3 in response to the signal of the fourth control signal terminal CN4, and for transmitting the second power terminal VSS signal to the third node N3 in response to the signal of the fifth control signal terminal CN 5.

In the present exemplary embodiment, as shown in fig. 4, the first input circuit 1 may include a first transistor T1, a first pole of the first transistor T1 is connected to the data signal terminal Vdata, a second pole of the first transistor T1 is connected to the first node N1, and a gate of the first transistor T1 is connected to the first control signal terminal CN 1. The second input circuit 2 may include a second transistor T2, a first pole of the second transistor T2 is connected to the sensing signal terminal Sense, a second pole of the second transistor T2 is connected to the first node N1, and a gate of the second transistor T3684 is connected to the second control signal terminal CN 2. The driving circuit 3 may include a driving transistor DT having a first electrode connected to the first power source terminal VDD, a second electrode connected to the second node N2, and a gate connected to the first node N1. The storage circuit 5 may comprise a storage capacitor C connected between said first power supply terminal VDD and said first node N1. The detection circuit 4 may include a third transistor T3, a first pole of the third transistor T3 is connected to the second node N2, a second pole of the third transistor T3 is connected to the first node N1, and a gate of the third transistor T1 is connected to the third control signal terminal CN 3. The power control circuit may include a fourth transistor T4, a fifth transistor T5, a fourth transistor T4 having a first electrode connected to the first power terminal VDD, a second electrode connected to the third node N3, and a gate connected to the fourth control signal terminal CN 4; the fifth transistor T5 has a first terminal connected to the second power source terminal VSS, a second terminal connected to the third node N3, and a gate connected to the fifth control signal terminal CN 5. It should be understood that, in other exemplary embodiments, the first input circuit 1, the second input circuit 2, the driving circuit 3, the detecting circuit 4, the storage circuit 5, and the power control circuit 6 may have other structures, which are within the protection scope of the present disclosure.

In the present exemplary embodiment, the first transistor T1, the second transistor T2, the third transistor T3, and the driving transistor DT may be P-type transistors, and the fourth transistor T4 and the fifth transistor T5 may be N-type transistors. The first power source terminal may be a high-level power source terminal, and the second power source terminal may be a low-level power source terminal. The power control circuit 6 may be integrated with a PowerIC (power management chip) in the display panel for supplying a power signal to the plurality of light emitting cells.

The driving method of the pixel driving circuit shown in fig. 4 may include two stages: a sensing phase and a driving phase. The pixel driving circuit may detect the threshold voltage of the driving transistor DT in the sensing phase, thereby compensating the data signal in the driving phase according to the threshold voltage of the driving transistor DT. As shown in fig. 5 and 6, fig. 5 is a timing diagram of each node of the pixel driving circuit in fig. 4 in the sensing phase, and fig. 6 is a timing diagram of each node of the pixel driving circuit in fig. 4 in the driving phase.

As shown in fig. 5 and 6, Hsync is a timing sequence of a horizontal synchronization signal in the display panel, CN1 is a timing sequence of the first control signal terminal CN1, CN2 is a timing sequence of the second control signal terminal CN2, CN3 is a timing sequence of the third control signal terminal CN3, CN4 is a timing sequence of the fourth control signal terminal CN4, CN5 is a timing sequence of the fifth control signal terminal CN5, N1 is a timing sequence of the first node N1, and Sense is a timing sequence of the sensing signal terminal Sense. Wherein, the falling edges of two adjacent effective pulse signals of the horizontal synchronizing signal Hsync define one period of the sensing phase.

As shown in fig. 5, during the sensing phase, the voltages of the first control signal terminal CN1 and the fourth control signal terminal CN4 are continuously at a high level, and the voltage of the fifth control signal terminal CN5 is continuously at a low level. The sensing phase of the pixel driving circuit includes three phases: a reset phase T1, a threshold establishment phase T2, and a sampling phase T3. During the reset phase T1: the second control signal terminal CN2 outputs a low level signal, the second transistor T2 is turned on, the third control signal terminal outputs a high level signal, the third transistor T3 is turned off, and the sensing signal terminal Sense outputs an initialization signal, which is transmitted to the first node through the second transistor T2, wherein the initialization signal can turn on the driving transistor DT. At the threshold establishment phase T2: the second and third control signal terminals CN2 and CN3 output low level signals, the second and third transistors T2 and T3 are turned on, and the voltage of the first node N1 gradually increases under the action of the first power terminal VDD until the voltage of the first node N1 is equal to VDD-Vth, where VDD is the voltage of the first power terminal VDD and Vth is the threshold voltage of the driving transistor DT. In the taking stage T3: the second control signal terminal CN2 and the third control signal terminal CN3 output low level signals, the second transistor T2 and the third transistor T3 are turned on, the voltage of the first node N1 is stabilized to Vdd-Vth, at this time, the sensing signal terminal Sense is connected to the first node N1, the voltage of Vdd-Vth can be detected by detecting the voltage of the sensing signal terminal Sense, and the threshold circuit Vth of the driving transistor can be calculated according to the sampling voltage because Vdd is known.

As shown in fig. 6, during the driving phase, the voltage of the fourth control signal terminal CN4 is continuously at a low level, and the voltage of the fifth control signal terminal CN5 is continuously at a high level. The driving phase of the pixel driving circuit comprises three phases: the reset phase T1 is data write T2, light emitting phase T3. In the light emitting period, the second control signal terminal CN2 outputs a low level signal to turn on the second transistor T2, and the sensing signal terminal Sense outputs a reference voltage, which is written into the first node through the second transistor T2, which is insufficient to turn on the driving transistor DT. In the data writing phase T2: the first control signal terminal CN1 outputs a low level signal, and the data signal terminal Vdata outputs a data signal, which is transmitted to the first node N1 through the first transistor. In the light emitting stage: the driving transistor DT is turned on by the first node to drive the light emitting unit OLED to emit light.

The pixel driving circuit provided by the exemplary embodiment writes the reference voltage into the first node in the reset stage, so that the initial voltage of the gate of the driving transistor is the reference voltage when the driving transistor is driven each time, and the driving transistor does not show different threshold voltages due to different initial voltages, thereby avoiding the occurrence of the display ghost.

In the present exemplary embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 in fig. 4 may be low temperature polysilicon thin film transistors with a double gate structure, and this arrangement may prevent charges stored in the capacitor of the pixel driving circuit during the light emitting period from leaking through the first transistor T1, the second transistor T2, and the third transistor T3. The driving transistor DT may be a low temperature polysilicon thin film transistor of a single gate structure. It should be understood that, in other exemplary embodiments, the first transistor T1, the second transistor T2, and the third transistor T3 may also be oxide thin film transistors, which have a small leakage current, so that the capacitor C may also be prevented from leaking in the light emitting stage. The material of the channel region of the oxide transistor may be indium gallium zinc oxide, and the indium gallium zinc oxide is an N-type semiconductor, so that the first transistor T1, the second transistor T2, and the third transistor T3 need to be configured as N-type transistors.

In the present exemplary embodiment, as shown in fig. 7, a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure is shown. The pixel driving circuit may further include an isolation circuit 7, and the isolation circuit 7 may be connected to the first node N1, the first input circuit 1, the second input circuit 2, and a sixth control signal terminal CN6, and is configured to respond to a signal of the sixth control signal terminal CN6 to connect the first input circuit 1, the second input circuit 2, and the first node N1. As shown in fig. 7, the isolation circuit 7 may include a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first input circuit 1 and the second input circuit 2, a second pole of the sixth transistor T6 is connected to the first node N1, and a gate of the sixth transistor T6 is connected to the sixth control signal terminal CN 6. Among them, the sixth transistor T6 may be a P-type transistor.

As shown in fig. 8 and 9, fig. 8 is a timing diagram of each node of the pixel driving circuit in fig. 7 in the sensing phase, and fig. 9 is a timing diagram of each node of the pixel driving circuit in fig. 7 in the driving phase. The pixel driving circuit shown in fig. 7 may also comprise a detection phase and a driving phase. As shown in fig. 8, the detection phase may also include: a reset phase T1, a threshold establishment phase T2, and a sampling phase T3. As shown in fig. 9, the driving phase may also include: a reset phase T1, a data write phase T2, and a light emission phase T3. The pixel driving circuit shown in fig. 7 is substantially the same as the pixel driving circuit shown in fig. 4 in driving method, except that: in a reset stage T1, a threshold establishing stage T2 and a sampling stage T3 of the detection stage, the sixth control signal terminal outputs a low level signal to turn on the sixth transistor; the sixth control signal terminal outputs a low level signal to turn on the sixth transistor during the reset period T1 and the data write period T2 of the driving period.

In the exemplary embodiment, the sixth transistor T6 and the third transistor T3 may be low temperature polysilicon thin film transistors with a dual gate structure, and this arrangement may prevent charges stored in the capacitor of the pixel driving circuit during the light emitting period from leaking through the sixth transistor T6 and the third transistor T3. Compared with the pixel driving circuit shown in fig. 4, the pixel driving circuit shown in fig. 7 only needs to be provided with two low-temperature polysilicon thin film transistors with a double-gate structure, thereby being beneficial to the layout design of the pixel driving circuit. In fig. 7, the first transistor T1, the second transistor T2, and the driving transistor DT may be P-type low temperature polysilicon transistors having a single gate structure.

It should be understood that, in other exemplary embodiments, the sixth transistor T6 and the third transistor T3 may also be oxide thin film transistors, which have a small leakage current, so that the capacitor C may also be prevented from leaking in the light emitting stage. The material of the channel region of the oxide transistor may be indium gallium zinc oxide, and the indium gallium zinc oxide is an N-type semiconductor, so the sixth transistor T6 and the third transistor T3 need to be respectively configured as N-type transistors.

Fig. 10 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. In the pixel driving circuit, the sixth transistor T6 and the third transistor T3 may be N-type oxide thin film transistors. As shown in fig. 11 and 12, fig. 11 is a timing diagram of each node of the pixel driving circuit in fig. 10 in the sensing phase, and fig. 12 is a timing diagram of each node of the pixel driving circuit in fig. 10 in the driving phase. The pixel drive circuit shown in fig. 10 may also include a detection phase and a drive phase. As shown in fig. 11, the detection phase may also include: a reset phase T1, a threshold establishment phase T2, and a sampling phase T3. As shown in fig. 12, the driving phase may also include: a reset phase T1, a data write phase T2, and a light emission phase T3. The pixel driving circuit shown in fig. 10 is substantially the same as the pixel driving circuit shown in fig. 7 in driving method, except that: the active level of the sixth control signal terminal is changed from low level to high level, and the active level of the third control signal terminal is changed from low level to high level.

An exemplary embodiment of the present disclosure also provides a pixel driving circuit driving method for driving the pixel driving circuit described above, the method including:

in the detection phase:

in the driving stage:

The pixel driving method provided by the present disclosure has been described in detail in the above, and is not described herein again.

An exemplary embodiment of the present disclosure also provides a display panel including the pixel driving circuit, the light emitting unit, and the power control circuit.

An exemplary embodiment of the present disclosure also provides a display panel driving method for driving the above display panel, the method including:

The display panel driving method provided by the present disclosure has been described in detail in the above, and is not described herein again.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.

Claims

1. A pixel driving circuit, comprising:

the first input circuit is connected with a data signal end, a first control signal end and a first node and is used for responding to a signal of the first control signal end to transmit a signal of the data signal end to the first node;

the second input circuit is connected with a second control signal end, a sensing signal end and the first node and is used for responding to a signal of the second control signal end and transmitting a signal of the sensing signal end to the first node;

the driving circuit is connected with the first node, a first power supply end and a second node and is used for outputting driving current to the second node according to the voltage of the first node;

the detection circuit is connected with the first node, the second node and the third control signal end and is used for responding to the signal of the third control signal end to communicate the first node and the second node;

and a memory circuit connected between the first power supply terminal and the first node.

2. The pixel driving circuit according to claim 1, wherein the first input circuit comprises:

a first transistor, a first pole of which is connected with the data signal end, a second pole of which is connected with the first node, and a grid of which is connected with the first control signal end;

the second input circuit includes:

a first electrode of the second transistor is connected with the sensing signal end, a second electrode of the second transistor is connected with the first node, and a grid electrode of the second transistor is connected with the second control signal end;

the drive circuit includes:

a driving transistor, wherein a first electrode is connected with the first power supply end, a second electrode is connected with the second node, and a grid electrode is connected with the first node;

the memory circuit includes:

a storage capacitor connected between the first power terminal and the first node;

the detection circuit includes:

and a third transistor having a first pole connected to the second node, a second pole connected to the first node, and a gate connected to the third control signal terminal.

3. The pixel driving circuit according to claim 2, wherein the first transistor, the second transistor, and the third transistor are oxide thin film transistors or low temperature polysilicon thin film transistors with a dual gate structure.

4. The pixel driving circuit according to claim 2, further comprising:

the isolation circuit is connected with the first node, the first input circuit, the second input circuit and the sixth control signal end and used for responding to the signal of the sixth control signal end to communicate the first input circuit, the second input circuit and the first node.

5. The pixel driving circuit according to claim 4, wherein the isolation circuit comprises:

and a sixth transistor, wherein a first pole of the sixth transistor is connected with the first input circuit and the second input circuit, a second pole of the sixth transistor is connected with the first node, and a grid of the sixth transistor is connected with the sixth control signal terminal.

6. The pixel driving circuit according to claim 5, wherein the sixth transistor and the third transistor are oxide thin film transistors or low temperature polysilicon thin film transistors with a dual gate structure.

7. A pixel drive circuit driving method for driving the pixel drive circuit according to any one of claims 1 to 6, comprising:

in the detection phase:

in the driving stage:

8. A display panel comprising the pixel drive circuit, the light emitting unit, and the power supply control circuit according to any one of claims 1 to 6;

the power supply control circuit is connected with the first power supply end, the third node, the second power supply end, the fourth control signal end and the fifth control signal end, and is used for responding to the signal of the fourth control signal end to transmit the signal of the first power supply end to the third node and responding to the signal of the fifth control signal end to transmit the signal of the second power supply end to the third node;

the light emitting unit is connected between the second node and a third node.

9. The display panel according to claim 8, wherein the power supply control circuit comprises:

a fourth transistor, having a first terminal connected to the first power terminal, a second terminal connected to the third node, and a gate connected to the fourth control signal terminal;

and a fifth transistor, wherein a first electrode of the fifth transistor is connected with the second power supply end, a second electrode of the fifth transistor is connected with the third node, and a grid of the fifth transistor is connected with the fifth control signal end.

10. A display panel driving method for driving the display panel according to claim 8 or 9, comprising: