CN111651085B - Self-capacitance detection scanning circuit - Google Patents
Self-capacitance detection scanning circuit Download PDFInfo
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- G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
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Abstract
The invention discloses a self-capacitance detection scanning circuit, aiming at the problem that the existing self-capacitance detection scanning circuit adopts fixed scanning frequency for detection and generates high-intensity electromagnetic radiation in a high-speed scanning process, a control circuit is added in the existing self-capacitance detection scanning circuit and comprises a scanning clock and a random signal generating circuit. The random signal generating circuit comprises a random number generator RNG and a random sequence generator, wherein the random number generator RNG generates a random pnrng signal, the pnrng signal is input into the random sequence generator, the random sequence generator is an 8-bit LFSR circuit, and the LFSR circuit generates an 8-bit pnseq sequence under the control of a scanning clock; meanwhile, the scanning circuit generates random scanning frequency to reduce the peak value of electromagnetic radiation generated in the self-capacitance detection scanning process, so that the aim of reducing electromagnetic interference is fulfilled.
Description
Technical Field
The invention belongs to the field of self-capacitance detection design, and particularly relates to a self-capacitance detection scanning circuit.
Background
With the rapid growth in scale and dramatic increase in complexity of integrated circuits, the problem of electromagnetic interference becomes increasingly acute. The self-capacitance detection scanning circuit can generate high-intensity electromagnetic radiation when working at a high speed under a fixed scanning frequency, and the health of a human body is seriously harmed. In addition, strong electromagnetic interference seriously affects the normal operation of electronic devices and systems, and even damages the electronic devices and systems. In order to reduce the influence of electromagnetic interference on electronic devices and systems, the electromagnetic interference generated by the self-capacitance detection scanning circuit needs to be eliminated.
Patent application No. 201511020533.7 entitled "method for improving electromagnetic interference resistance of capacitive touch key" discloses a method for improving electromagnetic interference resistance of capacitive touch key, which comprises: providing a plurality of switching frequency points, and selecting one switching frequency point as a current key discrimination frequency point; judging whether the slope of the key value under the current key discrimination frequency point exceeds a preset range or not; if the slope of the key values under the frequency point for key judgment exceeds the preset range, judging that the key values under the frequency point for key judgment are interfered, and stopping adopting the frequency point for key judgment; and performing key judgment by using other undisturbed frequency points.
According to the patent application file, key value data are collected in multiple frequencies and are respectively processed, whether the key value data of each frequency point are interfered or not is judged through slope difference, if the key value data of the frequency point for judging the key at present are interfered, the frequency point is stopped from being continuously used for judging the key, and the key is judged by using the key value data of another frequency point which is not interfered, so that the anti-electromagnetic interference performance of the capacitive touch key system is effectively enhanced under the condition that original system components are not changed. The method needs to collect the key value of each capacitive touch key and judge whether the key value is interfered one by one, the related algorithm is complex, and when the key value data of each frequency point is interfered and no available undisturbed frequency point exists, the anti-electromagnetic interference performance can not be enhanced. Therefore, the reliability of the method is poor.
Disclosure of Invention
The invention aims to provide a self-capacitance detection scanning circuit which can reduce electromagnetic interference generated in the self-capacitance detection scanning process.
In order to solve the problems, the technical scheme of the invention is as follows:
a self capacitance detection scan circuit comprising:
the negative end of the comparator is connected with the sampling capacitor, the positive end of the comparator is connected with the reference voltage, and the output end of the comparator is connected with a counter;
the charging circuit is used for charging the sampling capacitor; when the charging voltage of the sampling capacitor reaches the reference voltage, the output of the comparator is inverted, and the counter is increased by 1;
and the control circuit is used for generating a random signal to control the charging circuit and generating a random clock scanning frequency to reduce the electromagnetic radiation peak value in the self-capacitance detection process.
According to an embodiment of the present invention, the control circuit includes a scan clock, a random signal generating circuit;
the random signal generating circuit comprises a random number generator and a random sequence generator, wherein the random number generator generates a random pnrng signal, the pnrng signal is input into the random sequence generator, the random sequence generator is an 8-bit LFSR circuit, and the random sequence generator generates an 8-bit pnseq sequence under the control of the scanning clock;
the calculation formula of the pnseq sequence is as follows:
feedback＝pnseq[4]^pnseq[3]^pnseq[2]^pnseq[0]^pnrng
pnseq＝{feedback,pnseq[7:1]}
wherein feedback is a feedback bit of the pnseq sequence.
According to an embodiment of the present invention, the scan clock is provided with a spread spectrum enable bit, and when the spread spectrum enable bit is valid, the counter is reset when a count value reg _ randcnt of the counter is randsel;
the calculation formula of the randsel is as follows:
pnmod0＝{1’b0,pnseq[0]}+{1’b0,pnseq[1]}
pnmod1＝{1’b0,pnseq[2]}+{1’b0,pnseq[3]}
pnmod2＝{1’b0,pnseq[4]}+{1’b0,pnseq[5]}
pnmod3＝{1’b0,pnseq[6]}+{1’b0,pnseq[7]}
pnmod5＝{1’b0,pnmod3}+{1’b0,pnmod2}
pnmod7＝{1’b0,pnmod1}+pnmod5
pnmod9＝{2’b0,pnmod0}+{1’b0,pnmod7}
randsel＝(randm＝＝2’b00)？{2’d0,pnmod3}:
(randm＝＝2’b01)？{1’d0,pnmod5}:
(randm＝＝2’b10)？{1’d0,pnmod7}:pnmod9
wherein, pnmod0, pnmod1, pnmod2, pnmod3, pnmod5, pnmod7 and pnmod9 are composition patterns of random sequences, randm 2 ' b00 is a random jitter range of (-1, +1) for selecting a scan clock, randm 2 ' b01 is a random jitter range of (-1, +1) or (-2, +2) for selecting a scan clock, and randm 2 ' b10 is a random jitter range of (-1, +1) or (-2, +2) or (-3, +3) for selecting a scan clock.
According to an embodiment of the present invention, the charging circuit includes a first switch, a second switch and a charging capacitor;
one end of the first switch is connected with a power supply, and the other end of the first switch is connected with the charging capacitor;
one end of the second switch is connected to the connection position of the first switch and the charging capacitor, and the other end of the second switch is connected with the negative end of the comparator;
the first switch and the second switch are both connected with the control circuit, and when the first switch is closed and the second switch is opened, the power supply charges the charging capacitor; when the first switch is turned off and the second switch is turned off, the charging capacitor charges the sampling capacitor, and the counter is increased by 1; when the voltage of the sampling capacitor reaches the reference voltage, the counter latches.
According to an embodiment of the present invention, when the spread spectrum enable bit of the scan clock is invalid, the scan frequency of the scan clock is not changed, the scan center frequency of the first switch is only related to the frequency division coefficient of the scan clock, and the scan center frequency of the first switch is calculated as follows:
Fsw1＝Fclk/(2*(divn+1)+2)
wherein, Fsw1 is the scanning center frequency of the first switch, Fclk is the scanning frequency of the scanning clock, divn is the frequency division coefficient of the scanning clock;
when the spread spectrum enable bit is valid, the scanning frequency of the first switch generates random jitter, and the calculation formula of the scanning center frequency is as follows:
Fsw1＝Fclk/(2*(divn+1)+2*(randm+2))
here, randm is a random jitter range selection signal of the scan clock.
According to an embodiment of the present invention, the scan clock is provided with a frequency division counter;
when the first switch is closed and the second switch is opened, the frequency division counter counts at the rising edge of the scanning clock, when the value of the frequency division counter is equal to the frequency division coefficient of the scanning clock, the frequency division counter is reset, and the spread spectrum enable bit of the scanning clock is valid;
when the spread spectrum enable bit of the scanning clock is valid, the counter counts at the rising edge of the scanning clock, when the value of the counter is equal to that of randsel, the counter resets, the spread spectrum enable bit of the scanning clock is invalid, the first switch is disconnected, the second switch is closed, and the charging capacitor starts to charge the sampling capacitor;
when the first switch is turned off and the second switch is turned off, the frequency division counter counts on the rising edge of the scanning clock, when the value of the frequency division counter is equal to the frequency division coefficient of the scanning clock, the frequency division counter is reset, and the spread spectrum enable bit of the scanning clock is valid;
when the spread spectrum enable bit of the scanning clock is valid, the counter counts on the rising edge of the scanning clock, when the value of the counter is equal to the value of randsel, the counter resets, the spread spectrum enable bit of the scanning clock is invalid, the first switch is closed, and the second switch is opened.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
in the self-capacitance detection scanning circuit in an embodiment of the invention, aiming at the problem that the existing self-capacitance detection scanning circuit adopts fixed scanning frequency for detection and generates high-intensity electromagnetic radiation in a high-speed scanning process, the control circuit is added in the existing self-capacitance detection scanning circuit to generate random scanning frequency to reduce the peak value of the electromagnetic radiation generated in the self-capacitance detection scanning process, so that the aim of reducing the electromagnetic interference is fulfilled.
Drawings
FIG. 1 is a diagram of a conventional self-capacitance detection scan circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a self-capacitance detection scan according to an embodiment of the present invention;
fig. 3 is a circuit diagram of generating a randsel signal according to an embodiment of the invention;
FIG. 4 is a circuit diagram of the generation of the randcnt _ rst signal in one embodiment of the invention;
FIG. 5 is a state transition diagram of the self-capacitance detection switch control according to an embodiment of the present invention;
fig. 6 is a signal waveform diagram of the scan clock of the spread spectrum enable and spread spectrum disable lower SW1 according to an embodiment of the present invention.
Detailed Description
The self-capacitance detection scanning circuit provided by the invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims.
Referring to fig. 1, a conventional self-capacitance detection scan circuit is shown. In the figure, Cx is the touch key equivalent capacitance, and forms a switched capacitor circuit with the logic control switches SW1 and SW 2. fs is the switching frequency of the touch key, which can periodically switch the logic control switches SW1, SW2 and make them alternately assume a closed state and an open state. The logic control switches SW1, SW2 and the touch key equivalent capacitance Cx can be equivalent to a resistance Rx of 1/(fs × Cx) according to the switch capacitance characteristics. Vchg is a charging voltage, which periodically charges the charging and discharging capacitor C1 through the switch equivalent resistor Rx. When C1 charges to a voltage at the negative input of comparator CMP higher than the positive input reference voltage Vref, the comparator outputs a low level. The output of the comparator is corresponding to the discharge of the voltage at the end of the charging and discharging capacitor C1 is controlled by a logic control switch SW 3. Under the condition of normal operation after the touch key function is turned on, the holding time of the comparator outputting high level is the charging time of the charging and discharging capacitor C1, and is also the time of SW3 maintaining the off state.
The self-capacitance detection scanning circuit can generate high-intensity electromagnetic radiation when working at a high speed under a fixed scanning frequency fs, and can harm the health of a human body.
To solve the problem, the present invention provides a self-capacitance detection scan circuit, please refer to fig. 2, which includes:
the negative end of the comparator 1 is connected with the sampling capacitor Cs, the positive end of the comparator 1 is connected with the reference voltage, and the output end of the comparator 1 is connected with a counter 2;
the charging circuit 3 is used for charging the sampling capacitor Cs; when the charging voltage of the sampling capacitor Cs reaches the reference voltage Vref, the comparator 1 outputs the inverted phase, and the counter 2 adds 1;
and the control circuit 4 is used for generating a random signal to control the charging circuit 3 and generating a random clock scanning frequency to reduce the electromagnetic radiation peak value in the self-capacitance detection process.
The self-capacitance detection scanning circuit in the implementation charges Cs through the charging circuit, the counter 2 counts the charging times of Cx to Cs through the output of the comparator 1, and the change of capacitance on Cx is calculated through the counting result, so that the purpose of self-capacitance detection is achieved. The most important thing is that, the present embodiment provides the control circuit 4, which can generate a random scanning frequency to control the charging frequency of the charging circuit 3 to Cs, and because of the random scanning frequency, high-intensity electromagnetic radiation generated by adopting a fixed scanning frequency will not occur, and the electromagnetic radiation generated in the self-capacitance detection scanning process can be reduced, thereby achieving the function of reducing electromagnetic interference.
In particular, the control circuit 4 can generate random signals, see fig. 3. The control circuit comprises a scanning clock and a random signal generating circuit. The random signal generating circuit comprises a random number generator RNG and a random sequence generator, wherein the random number generator RNG generates a random pnrng signal, the pnrng signal is input into the random sequence generator, the random sequence generator is an 8-bit LFSR (linear feedback high register) circuit, and the LFSR circuit generates an 8-bit pnseq sequence under the control of a scanning clock;
the calculation formula for the pnseq sequence is as follows:
feedback＝pnseq[4]^pnseq[3]^pnseq[2]^pnseq[0]^pnrng
pnseq＝{feedback,pnseq[7:1]}
wherein feedback is a feedback bit of the pnseq sequence.
After the charging circuit 3 completes one-time charging of the sampling capacitor Cs, the random sequence pnseq is updated once.
The scan clock is provided with a spreading enable bit spread, and when the spreading enable bit spread is valid, and when a count value reg _ randcnt of the counter 2 is randsel, a randcnt _ rst signal is generated, and the counter 2 is reset, please refer to fig. 4.
The calculation formula of the randsel is as follows:
pnmod0＝{1’b0,pnseq[0]}+{1’b0,pnseq[1]}
pnmod1＝{1’b0,pnseq[2]}+{1’b0,pnseq[3]}
pnmod2＝{1’b0,pnseq[4]}+{1’b0,pnseq[5]}
pnmod3＝{1’b0,pnseq[6]}+{1’b0,pnseq[7]}
pnmod5＝{1’b0,pnmod3}+{1’b0,pnmod2}
pnmod7＝{1’b0,pnmod1}+pnmod5
pnmod9＝{2’b0,pnmod0}+{1’b0,pnmod7}
randsel＝(randm＝＝2’b00)？{2’d0,pnmod3}:
(randm＝＝2’b01)？{1’d0,pnmod5}:
(randm＝＝2’b10)？{1’d0,pnmod7}:pnmod9
wherein, pnmod0, pnmod1, pnmod2, pnmod3, pnmod5, pnmod7 and pnmod9 are composition patterns of random sequences, randm 2 ' b00 is a random jitter range of (-1, +1) for selecting a scan clock, randm 2 ' b01 is a random jitter range of (-1, +1) or (-2, +2) for selecting a scan clock, and randm 2 ' b10 is a random jitter range of (-1, +1) or (-2, +2) or (-3, +3) for selecting a scan clock. How does the random sequence generated by the control circuit 4 control the charging circuit 3? The composition of the charging circuit 3 is described below. Referring to fig. 2, the charging circuit 3 includes a first switch SW1, a second switch SW2 and a charging capacitor Cx, one end of the first switch SW1 is connected to the power VDD, and the other end of the first switch SW1 is connected to the charging capacitor Cx; one end of the second switch SW2 is connected to the connection point of the first switch SW1 and the charging capacitor Cx, and the other end of the second switch SW2 is connected to the negative terminal of the comparator 1.
The first switch SW1 and the second switch SW2 are both connected to the control circuit 4, and the switching of the switches is controlled by the random scanning frequency of the control circuit 4.
(1) When the first switch SW1 is open, the second switch SW2 is open, and the SWCs are closed, Cs is discharged to ground;
(2) when the first switch SW1 is off, the second switch SW2 is off, and the SWCs are off, the counter 2 is cleared;
(3) when the first switch SW1 is closed and the second switch SW2 is opened, the power supply VDD charges the charging capacitor Cx;
(4) when the first switch SW1 is turned off and the second switch SW2 is turned on, the charging capacitor Cx charges the sampling capacitor Cs, and 1 is added to the counter 2;
(5) repeating (3) - (4), when the voltage of the sampling capacitance Cs reaches the reference voltage Vref, the counter 2 latches the count result.
To better illustrate the control of the first switch SW1 and the second switch SW2 by the control circuit 4, the present embodiment provides a state transition diagram of the self-capacitance detection switch, please refer to fig. 5.
In the figure, there are 5 states, STA _ IDLE, STA _ SW1T, STA _ SW1J, STA _ SW2T, and STA _ SW2J, respectively. The STA _ IDLE is in an initial state, the STA _ SW1T is in a state where the SW1 is turned on and the SW2 is turned off to generate the divided scan clock, the STA _ SW2T is in a state where the SW1 is turned off and the SW2 is turned on to generate the divided scan clock, the STA _ SW1J is in a spreading state where the SW1 is turned on and the SW2 is turned off, and the STA _ SW2J is in a spreading state where the SW1 is turned off and the SW2 is turned on.
Specifically, the scan is started, the STA _ SW1T state is entered, and the count value reg _ divcnt of the frequency division counter counts at the rising edge of the scan clock clk. divn is the scan clock division coefficient, and when reg _ divcnt is equal to divn, the reset signal divcnt _ rst of the division counter is set to 1, and the state jumps to STA _ SW 1J. When the current state is STA _ SW1J, reg _ divcnt is cleared, and the count value reg _ randcnt of the counter 2 counts at the rising edge of the scan clock clk. When reg _ randcnt is equal to randsel, the reset signal randcnt _ rst of the counter 2 is set to 1, and the state jumps to STA _ SW 2T. When the current state is STA _ SW2T, reg _ randcnt is cleared, reg _ divcnt counts at the rising edge of the scan clock clk, and when the divcnt _ rst signal is pulled high, the state jumps to STA _ SW 2J. When the current state is STA _ SW2J, reg _ randcnt counts at the rising edge of the scan clock clk. When the randcnt _ rst signal is pulled high, the state jumps to STA _ SW1T to begin looping until comparator 1 outputs a high, and the state jumps to STA _ IDLE.
That is, the scan clock is provided with a frequency division counter.
When the first switch SW1 is closed and the second switch SW2 is opened, the frequency division counter counts at the rising edge of the scan clock, and when the value of the frequency division counter is equal to the frequency division coefficient of the scan clock, the frequency division counter is reset, the spread spectrum enable bit of the scan clock is valid, and the state STA _ SW1J is entered.
When the spread spectrum enable bit of the scanning clock is valid, the frequency division counter is cleared, the counter 2 counts on the rising edge of the scanning clock, when the value of the counter 2 is equal to the value of randsel, the counter 2 resets, the spread spectrum enable bit of the scanning clock is invalid, the first switch SW1 is opened, the second switch SW2 is closed, the charging capacitor Cx starts to charge the sampling capacitor Cs, and the state STA _ SW2T is entered.
When the first switch SW1 is turned off and the second switch SW2 is turned on, the counter 2 is cleared, the frequency division counter counts at the rising edge of the scan clock, and when the value of the frequency division counter is equal to the frequency division coefficient of the scan clock, the frequency division counter is reset, the spread spectrum enable bit of the scan clock is valid, and the state STA _ SW2J is entered.
When the spread spectrum enable bit of the scanning clock is valid, the frequency division counter is cleared, the counter 2 counts on the rising edge of the scanning clock, when the value of the counter 2 is equal to the value of randsel, the counter 2 is reset, the spread spectrum enable bit of the scanning clock is invalid, the first switch is closed, the second switch is opened, the state STA _ SW1T is entered, the above-mentioned circulation is started until the comparator 1 outputs high level, and the state jumps to the STA _ IDLE state.
The present invention adds a spread spectrum enable to the existing self-capacitance detection scan circuit, which is different between the spread spectrum enable and the disable, and takes the partial SW1 signal waveform when the frequency division coefficient divn is 0 and randm is 0 of the scan clock as an example, please refer to fig. 6. When the spread spectrum enable is disabled, the scan center frequency of SW1 is only related to the division factor divn of the scan clock, and the calculation formula is as follows:
Fsw1＝Fclk/(2*(divn+1)+2)
wherein, Fsw1 is the scan center frequency of the first switch SW1, Fclk is the scan frequency of the scan clock, divn is the frequency division coefficient of the scan clock;
when the spread spectrum enable is enabled, the sweep frequency of the first switch SW1 is randomly dithered, and the sweep center frequency is calculated as follows:
Fsw1＝Fclk/(2*(divn+1)+2*(randm+2))
here, randm is a random jitter range selection signal of the scan clock.
In summary, the present invention is directed to the problem that the existing self-capacitance detection scanning circuit adopts a fixed scanning frequency for detection and generates high-intensity electromagnetic radiation in a high-speed scanning process, and adds a control circuit to the existing self-capacitance detection scanning circuit, where the control circuit includes a scanning clock and a random signal generating circuit. Wherein the random signal generating circuit comprises a random number generator RNG and a random sequence generator, the random number generator RNG generates a random pnrng signal, the pnrng signal is input to the random sequence generator, the random sequence generator is an 8-bit LFSR (linear feedback high register) circuit, and the LFSR circuit generates an 8-bit pnseq sequence under the control of a scanning clock; meanwhile, the scanning circuit generates random scanning frequency to reduce the peak value of electromagnetic radiation generated in the self-capacitance detection scanning process, so that the aim of reducing electromagnetic interference is fulfilled.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.
Claims (5)
1. A self-capacitance detection scan circuit, comprising:
the negative end of the comparator is connected with the sampling capacitor, the positive end of the comparator is connected with the reference voltage, and the output end of the comparator is connected with a counter;
the charging circuit is used for charging the sampling capacitor; when the charging voltage of the sampling capacitor reaches the reference voltage, the output of the comparator is inverted, and the counter is increased by 1;
the control circuit is used for generating a random signal to control the charging circuit and generating a random clock scanning frequency to reduce an electromagnetic radiation peak value in the self-capacitance detection process;
the control circuit comprises a scanning clock and a random signal generating circuit, wherein the scanning clock is provided with a spread spectrum enabling bit, and when the spread spectrum enabling bit is effective, the counter is reset when the count value reg _ randcnt of the counter is randsel;
the calculation formula of the randsel is as follows:
pnmod0＝{1’b0,pnseq[0]}+{1’b0,pnseq[1]}
pnmod1＝{1’b0,pnseq[2]}+{1’b0,pnseq[3]}
pnmod2＝{1’b0,pnseq[4]}+{1’b0,pnseq[5]}
pnmod3＝{1’b0,pnseq[6]}+{1’b0,pnseq[7]}
pnmod5＝{1’b0,pnmod3}+{1’b0,pnmod2}
pnmod7＝{1’b0,pnmod1}+pnmod5
pnmod9＝{2’b0,pnmod0}+{1’b0,pnmod7}
randsel＝(randm＝＝2’b00)？{2’d0,pnmod3}:
(randm＝＝2’b01)？{1’d0,pnmod5}:
(randm＝＝2’b10)？{1’d0,pnmod7}:pnmod9
wherein, pnmod0, pnmod1, pnmod2, pnmod3, pnmod5, pnmod7 and pnmod9 are composition patterns of random sequences, randm 2 ' b00 is a random jitter range of (-1, +1) for selecting a scan clock, randm 2 ' b01 is a random jitter range of (-1, +1) or (-2, +2) for selecting a scan clock, and randm 2 ' b10 is a random jitter range of (-1, +1) or (-2, +2) or (-3, +3) for selecting a scan clock.
2. The self-capacitance detection scan circuit of claim 1, wherein the random signal generation circuit comprises a random number generator, a random sequence generator, the random number generator generating a random pnrng signal, the pnrng signal being input to the random sequence generator, the random sequence generator being an 8-bit LFSR circuit, the random sequence generator generating an 8-bit pnseq sequence under control of the scan clock;
the calculation formula of the pnseq sequence is as follows:
feedback＝pnseq[4]^pnseq[3]^pnseq[2]^pnseq[0]^pnrng
pnseq＝{feedback,pnseq[7:1]}
wherein feedback is the feedback bit of the pnseq sequence.
3. The self-capacitance detection scan circuit of claim 1, wherein the charging circuit comprises a first switch, a second switch, and a charging capacitor;
one end of the first switch is connected with a power supply, and the other end of the first switch is connected with the charging capacitor;
one end of the second switch is connected to the connection position of the first switch and the charging capacitor, and the other end of the second switch is connected with the negative end of the comparator;
the first switch and the second switch are both connected with the control circuit, and when the first switch is closed and the second switch is opened, the power supply charges the charging capacitor; when the first switch is turned off and the second switch is turned off, the charging capacitor charges the sampling capacitor, and the counter is increased by 1; when the voltage of the sampling capacitor reaches the reference voltage, the counter latches.
4. The self-capacitance detection scan circuit as claimed in claim 3, wherein when the spread spectrum enable bit of the scan clock is invalid, the scan frequency of the scan clock is not changed, the scan center frequency of the first switch is only related to the division factor of the scan clock, and the scan center frequency of the first switch is calculated as follows:
Fsw1＝Fclk/(2*(divn+1)+2)
wherein, Fsw1 is the scanning center frequency of the first switch, Fclk is the scanning frequency of the scanning clock, divn is the frequency division coefficient of the scanning clock;
when the spread spectrum enable bit is valid, the scanning frequency of the first switch generates random jitter, and the calculation formula of the scanning center frequency is as follows:
Fsw1＝Fclk/(2*(divn+1)+2*(randm+2))
here, randm is a random jitter range selection signal of the scan clock.
5. The self-capacitance detection scan circuit as claimed in claim 3, wherein the scan clock is provided with a frequency division counter;
when the first switch is closed and the second switch is opened, the frequency division counter counts at the rising edge of the scanning clock, when the value of the frequency division counter is equal to the frequency division coefficient of the scanning clock, the frequency division counter is reset, and the spread spectrum enable bit of the scanning clock is valid;
when the spread spectrum enable bit of the scanning clock is valid, the counter counts on the rising edge of the scanning clock, when the value of the counter is equal to the value of randsel, the counter resets, the spread spectrum enable bit of the scanning clock is invalid, the first switch is disconnected, the second switch is closed, and the charging capacitor starts to charge the sampling capacitor;
when the first switch is turned off and the second switch is turned off, the frequency division counter counts at the rising edge of the scanning clock, when the value of the frequency division counter is equal to the frequency division coefficient of the scanning clock, the frequency division counter is reset, and the spread spectrum enable bit of the scanning clock is valid;
when the spread spectrum enable bit of the scanning clock is valid, the counter counts on the rising edge of the scanning clock, when the value of the counter is equal to the value of randsel, the counter resets, the spread spectrum enable bit of the scanning clock is invalid, the first switch is closed, and the second switch is opened.
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| CN1528058A (en) * | 2001-05-15 | 2004-09-08 | �����ɷ� | Fast slewing pseudorandom noise generator |
| CN203117298U (en) * | 2013-01-30 | 2013-08-07 | 比亚迪股份有限公司 | Capacitance detection circuit |
| CN104407748A (en) * | 2013-04-25 | 2015-03-11 | 安纳帕斯股份有限公司 | Method for reducing effect of noise and apparatus for detecting touch using the same |
| CN107562410A (en) * | 2017-08-29 | 2018-01-09 | 中国科学院苏州纳米技术与纳米仿生研究所 | The harvester and acquisition method of true random number |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1641124B1 (en) * | 2002-12-24 | 2009-06-03 | Fujitsu Microelectronics Limited | Spread spectrum clock generation circuit |
| CN103116424A (en) * | 2011-11-16 | 2013-05-22 | 飞思卡尔半导体公司 | Touch tablet capacitance-type sensor circuit |
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|---|---|---|---|---|
| CN1528058A (en) * | 2001-05-15 | 2004-09-08 | �����ɷ� | Fast slewing pseudorandom noise generator |
| CN203117298U (en) * | 2013-01-30 | 2013-08-07 | 比亚迪股份有限公司 | Capacitance detection circuit |
| CN104407748A (en) * | 2013-04-25 | 2015-03-11 | 安纳帕斯股份有限公司 | Method for reducing effect of noise and apparatus for detecting touch using the same |
| CN107562410A (en) * | 2017-08-29 | 2018-01-09 | 中国科学院苏州纳米技术与纳米仿生研究所 | The harvester and acquisition method of true random number |
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