CN111640747A - Semiconductor device, electric contact structure and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device, an electrical contact structure and a method of manufacturing the same, by connecting the tops of at least two contact plugs formed at the boundary of the core element region together, at the boundary of the core element region A combined contact structure with a larger top cross-sectional area is formed at the boundary of the core element region, thereby providing sufficient process margin for the subsequent process of forming an electrical structure above the contact structure at the boundary of the core element region, so that the electrical structure at the boundary is The size of the electrical structure is increased, the contact resistance is reduced, and the density difference of the circuit pattern between the core component area and the peripheral circuit area is buffered, and the optical proximity effect is improved to ensure the core component area. The electrical structures above the contact plugs within the boundary are consistent, and the electrical structures above the contact plugs at the boundary are prevented from collapsing, thereby improving device performance.

Description

Semiconductor device and electrical contact structure and manufacturing method thereof

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor device, an electrical contact structure and a manufacturing method thereof.

Background technique

Various techniques have been used to integrate more circuit patterns in the limited area of a semiconductor substrate or wafer. Due to the difference in circuit pattern spacing, integrated circuits are generally divided into device dense area (Dense), device sparse area (ISO) and device isolated area. It is an area with low device density (that is, the device is relatively sparse), and the device isolated area is an area where the relatively sparse area and the dense area are separately set. As the critical dimensions of semiconductor devices continue to decrease, the density of circuit patterns and/or device heights continue to increase, subject to the resolution limit of the optical exposure tool and the difference in density between dense and sparse device regions. Effects (i.e., dense/sparse effects of circuit patterns), the difficulty in performing the photolithography process and/or the etching process is also greatly increased (for example, the process margin is reduced), which in turn leads to the manufacture of semiconductor devices. Performance is affected.

For example, in the case of a dynamic random access memory (hereinafter referred to as DRAM) device, a huge number of memory cells are aggregated to form an array storage area, and peripheral circuits exist beside the array storage area. The peripheral circuit area contains other transistor elements and contact structures, etc. The array storage area is used as the device dense area of DRAM to store data, and the peripheral circuit area is used as the device sparse area of DRAM to provide the required array storage area. Input and output signals, etc. Wherein, each memory cell in the array memory area can be composed of a metal oxide semiconductor (MOS) transistor connected in series with a capacitor structure. The capacitor is located in the array storage area, wherein the capacitor is stacked above the bit line and is electrically coupled to the storage node contact corresponding to the capacitor, and the storage node contact is electrically coupled to the active area below it . With the continuous development of semiconductor technology, the critical dimension of the device is continuously reduced, and the gap between the memory cells of the DRAM device becomes narrower. When the storage node contact is formed by the Self Aligned Contact (SAC) process , Affected by the resolution limit of the exposure machine (optical exposure too1) and the effect of the density difference between the device dense area and the device sparse area, the contact holes formed inside the array storage area are inconsistent, and the contact holes at the boundary of the device dense area are abnormal. In turn, the contact area between the capacitor formed above and the contact plug in the contact hole is reduced, and the contact resistance is increased, which may cause some storage bits to fail due to the open circuit or short circuit of the contact plug, and the boundary of the array storage area. The problem of capacitor collapse, which affects and limits the improvement of DRAM performance.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a semiconductor device, an electrical contact structure and a manufacturing method thereof, so as to solve the problem of the core element area caused by the optical proximity effect and the dense/sparse effect of circuit patterns in the existing semiconductor devices such as dynamic random access memory. The electrical structures connected to the internal contact plugs are inconsistent and the electrical structures connected to the contact plugs at the boundary of the core element area are abnormal.

In order to solve the above technical problems, the present invention provides an electrical contact structure for a semiconductor device, the electrical contact structure includes:

a plurality of contact plugs formed above the core elements in the core element region of the semiconductor device, and the bottoms of the respective contact plugs are in contact with the active regions of the corresponding core elements,

Wherein, the tops of at least two contact plugs formed at the boundary of the core element region are connected together, and the contact plugs whose tops are connected together include the outermost contact plug at the boundary.

Based on the same inventive concept, the present invention also provides a semiconductor device, comprising:

a semiconductor substrate, the semiconductor substrate has a core element region, and a plurality of core elements are formed in the core element region;

an interlayer dielectric layer covering the semiconductor substrate; and,

According to the electrical contact structure of a semiconductor device according to the present invention, the electrical contact structure is formed in the interlayer dielectric layer, and the bottom of each of the contact plugs of the electrical contact structure is connected to the active part of the corresponding core element. area contact, and the tops of at least two contact plugs formed at the boundary of the core element area in the electrical contact structure are connected together, and all the contact plugs connected by the tops include the boundary Outermost contact plug.

Based on the same inventive concept, the present invention also provides a method for manufacturing an electrical contact structure of a semiconductor device, including:

providing a semiconductor substrate, the semiconductor substrate having a core element region in which a plurality of core elements are formed;

An interlayer dielectric layer is formed on the semiconductor substrate, and a plurality of contact holes are formed in the interlayer dielectric layer, each of the contact holes penetrates the interlayer dielectric layer and exposes the active elements of the corresponding core elements Area;

Contact plugs are formed in the contact holes, and the bottom of each of the contact plugs is in contact with the active region of the corresponding core element, and at least two contact plugs formed at the boundary of the core element region have The tops are connected together, and all the contact plugs in which the tops are connected include the outermost contact plug at the boundary.

Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising: using the method for manufacturing an electrical contact structure for a semiconductor device according to the present invention, forming a corresponding contact structure on a semiconductor substrate having a core element region The electrical contact structure for the electrical contact of the core element.

Compared with the prior art, the technical scheme of the present invention has the following beneficial effects:

By connecting the tops of at least two contact plugs formed at the boundary of the core element region together, a combined contact structure with a larger top cross-sectional area is formed at the boundary of the core element region, whereby a In one aspect, a sufficient process margin can be provided for the subsequent process of forming an electrical structure (such as the lower plate of a capacitor of a DRAM) above the combined contact structure at the boundary of the core element region, which is beneficial to the improvement of the electrical structure at the boundary. The size increases to avoid abnormality or collapse of the electrical structure at the boundary; on the other hand, the electrical structure at the boundary and the combined contact structure can have a larger contact area, so the contact resistance is reduced, which is conducive to improving the device. More importantly, the increased size of the electrical structure at the boundary can buffer the density difference of the circuit pattern between the core element area and the peripheral circuit area, so that all electrical circuits in the core element area are formed The photolithography process and/or etching process of the structure can improve the optical proximity effect, reduce the sparse/dense load effect, ensure the consistency of the electrical structure above the contact plug within the boundary of the core element region, and improve the device performance.

Description of drawings

1A-1D are schematic cross-sectional structural views of a method for manufacturing an electrical contact structure of a semiconductor device according to an embodiment of the present invention;

2A-2D are schematic cross-sectional structural views of a method for manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention;

3A is a schematic top-view structure diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

3B to 11 are schematic cross-sectional structural diagrams taken along the line aa' in FIG. 3A in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed ways

The technical solutions proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

1D is a schematic cross-sectional view illustrating an electrical contact structure of a semiconductor device according to an embodiment of the present invention. 1D, an electrical contact structure of a semiconductor device provided by an embodiment of the present invention includes a plurality of contact plugs 106a, 106b, wherein the contact plugs 106a, 106b are formed in the core element of the core element region I of the semiconductor device (not shown), and the bottom of each of the contacted plugs 106a, 106b is in contact with the active region 101 of the corresponding core element. Wherein, the core element area I includes a boundary (or called a boundary area, a boundary area, an interface area) I-2 and a central area I-1 located within the boundary I-2, which is formed on the boundary of the core element area I The tops of at least two contact plugs 106b at I-2 are joined together. The core element area I is a device dense area, and the peripheral circuit area II around it is a device sparse area.

Each contact plug 106a, 106b, 106c may include a barrier metal layer (not shown) and a metal layer (not shown), the barrier metal layer may include, for example, Ti, _Ta , _Mo , _TixNy , _TaxNy , _TixZry , _TixZryNz , _{NbxNy , ZrxNy , WxNy , VxNy , HfxNy , MoxNy} , _{RuxNy and / or TixSi y} N _z . Metal layers may include, for example, tungsten, copper and/or aluminum

All the contact plugs 106b connected with the tops of I-2 at the boundary of the core element region 1 constitute an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, the tops of I-2 at the boundary of the core element region 1 are connected All the contact plugs 106b together, at the boundary I-2 form a combined contact structure with a larger top cross-sectional area.

Referring to FIG. 1D and FIG. 11 , in this embodiment, the semiconductor device is a dynamic random access memory (DRAM), the core element area is a storage array area of the DRAM memory, the core element is a storage transistor, and the electrical contacts The structure is a storage node contact portion, which is connected to a capacitor structure (ie, a storage node, storage node). That is, each contact plug 106a in the central area I-1 of the core element area 1 is connected to a capacitor structure (as shown by 705a in FIG. 11 ), and a combined contact structure in I-2 at the boundary of the core element area 1 A capacitor structure (shown as 705b in FIG. 11 ) is connected on top, and the capacitor structure at I-2 at the boundary has a first width W1, and the boundary at the core element region I is within I-2 (ie, the center The capacitor structure in the region 1-1) has a second width W2. Due to the presence of the combined contact structure with a larger top cross-sectional area formed at the boundary of the core element region 1 at the boundary of the region 1, it can be the width of the capacitor at the boundary of the region 1-2. The formation process of the capacitor structure provides sufficient process margin to facilitate increasing the first width W1 of the capacitor structure of I-2 at the boundary, so that the first width W1 is greater than the second width W2, and further, a On the one hand, the collapse of the capacitor structure formed at the boundary is avoided; on the other hand, a larger contact area can be formed between the capacitor structure at the boundary and the combined contact structure below, which reduces the contact resistance and is conducive to improving the The electrical performance of the device; more importantly, the increased size of the capacitor structure at the boundary can buffer the density difference of the circuit pattern between the core element area I and the peripheral circuit area II, so that the photolithography process and /or during the etching process, the optical proximity effect can be improved, the sparse/dense loading effect can be reduced, and the capacitance structure above the contact plug 106a of the area (ie, the central area) I-1 at the boundary of the core element area I can be guaranteed Consistency prevents the problem of abnormal capacitance structures above the contact plugs at some positions in the core element region I or collapse of the capacitance structures above the contact plugs at the boundary I-2. Optionally, the first width W1 is greater than 1.5 times the second width W2.

3A and FIG. 11 , the semiconductor device includes a plurality of word lines WL and a plurality of bit lines BL, each of the word lines WL intersects with the plurality of the active regions AA1 in the core element region I , the word line WL may be a buried word line, the bit line BL is formed above the core element of the core element region I and is perpendicular to the word line WL, the top is connected with all contact plugs A formed structure (eg, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure) spans at least one of the word lines WL and is aligned (ie, parallel to) with the bit line BL, such as an inverted U-shaped electrical contact structure formed Or the comb-shaped electrical contact structure crosses an active area AA1 on the outermost boundary of the core element area I (that is, the side of I-2 at the boundary that is closest to the peripheral circuit area II, that is, the outermost of I-2 at the boundary). One of the word lines WL in . It should be noted that in this embodiment, although the semiconductor device is exemplified as a DRAM, the technical solution of the present invention is not limited to this, and the semiconductor device can also be any suitable electrical device, such as a memory of other architectures. , the capacitance structure can be replaced by a corresponding electrical structure, such as a resistor, etc.

1A to 1D are schematic cross-sectional views of the device in the method of manufacturing the electrical contact structure of the semiconductor device according to the present embodiment. Please refer to FIG. 1A to FIG. 1D , this embodiment further provides a method for manufacturing an electrical contact structure of a semiconductor device, including the following steps:

First, referring to FIG. 1A , a semiconductor substrate 100 is provided, which includes a core element region I and a peripheral circuit region II. The semiconductor substrate 100 can be selected from a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, and a germanium-on-insulator substrate. Substrate (GOI), silicon germanium substrate, etc. A plurality of shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100. The shallow trench isolation structures are formed by etching the semiconductor substrate 100 to form trenches, and then filling the trenches with insulating materials. To form, the material of the shallow trench isolation structure may include silicon oxide, silicon nitride, or silicon oxynitride. The shallow trench isolation structure defines the boundary between the core element region I and the peripheral circuit region II on a two-dimensional plane (ie, defines the boundary I-2 of the core element region I), and also defines the core element The active region 101 corresponding to each core element in the region I and the active region 101 corresponding to the peripheral elements in the peripheral circuit region II.

Next, please continue to refer to FIG. 1A , an interlayer dielectric layer 102 is covered on the semiconductor substrate 100 , and the interlayer dielectric layer 102 may be configured to have a single-layer structure or a multi-layer structure. The interlayer dielectric layer 102 may include at least one of silicon nitride, silicon oxynitride, and low-k dielectric materials. Among them, the dielectric constant k of the low-k dielectric material is smaller than that of the silicon oxide layer, and it can be used as an intermetal dielectric (IMD) layer, such as high density plasma (HDP) oxide, orthosilicic acid Tetraethyl acetate (TEOS), plasma enhanced TEOS (PE-TEOS), undoped silicate glass (USG), silicate phosphor glass (PSG), silicate boron glass (BSG), boron silicate glass (BPSG), fluorinated silicate glass (FSG), spin-on glass (SOG), etc. In addition, an etch stop layer (not shown) may be formed between the semiconductor substrate 100 and the interlayer dielectric layer 102, and the etch stop layer may include SiN, SiON, SiC, SiCN, BN (Nitride Gate) or any combination thereof. The etch stop layer and interlayer dielectric layer 102 may be formed using plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), atmospheric pressure CVD (APCVD) and/or spin coating processes.

Then, please continue to refer to FIG. 1A , through the first photolithography process, a first mask pattern 103 is formed on the interlayer dielectric layer 102 , the first mask pattern 103 defines the position of each contact plug, and then, using The first mask pattern 103 is used as an etching mask to anisotropically etch the interlayer dielectric layer 102 to form contact holes 102a, 102b and 102c penetrating the interlayer dielectric layer 102 and exposing the underlying corresponding active regions 101 , the contact holes 102a, 102b and 102c are all independent of each other, each contact hole 102a is located in the central region I-1 of the core element region I and exposes the active region 101 of the corresponding core element in the central region I-1, each The contact holes 102b are located at the boundary I-2 of the core element region I and expose the active region 101 of the corresponding core element in the boundary I-2, and each contact hole 102c is located in the peripheral circuit region II and exposes the corresponding peripheral Active region 101 of the element.

1B , after the contact holes 102a-102c are formed, an ashing process or a wet cleaning process may be performed to remove the first mask pattern 103 and fill the sacrificial layer 104 in each of the contact holes 102a-102c. The sacrificial layer 104 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL), which may enable the contact holes 102 a to 102 c having a high aspect ratio to be filled with the sacrificial layer 104 .

Next, please continue to refer to FIG. 1B , a second mask pattern 105 can be formed on the interlayer dielectric layer 102 and the sacrificial layer 104 through a second photolithography process. 2. The tops of the corresponding at least two contact holes 102b are connected to the trench 102d. Using the second mask pattern 105 as a mask, the interlayer dielectric layer at the boundary I-2 is etched to form a trench 102d connecting the tops of the corresponding at least two contact holes 102b at the boundary, and the trench 102d is at least The outermost contact hole of I-2 at the boundary is exposed (eg, trench 102d exposes at least one of the outermost contact holes of I-2 at the core boundary).

Referring to FIG. 1C, the sacrificial layer 104 and the second mask pattern 105 in the contact holes 102a-102c and 102d may be removed by an ashing process of oxygen, ozone or ultraviolet light or by a wet cleaning process to re-exposed the respective contact holes 102a ~102c and trench 102d.

Referring to FIG. 1D, a barrier metal layer (not shown) may be formed in the contact holes 102a-102c and the trench 102d. For example, the barrier metal layer may cover the inner walls of the contact holes and trenches and the interlayer dielectric layer with a uniform thickness 102 on the top surface. The barrier metal layer can reduce or prevent metal materials disposed in the contact holes and trenches from diffusing into the interlayer dielectric layer 102 . For example, the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition Deposition (PVD) (eg, sputtering) and other processes. Then, a metal layer is filled in each of the contact holes 102a-102c and the trench 102d to form the contact plugs 106a, 106c and the combined contact structure 106b. Therein, the metal layer may be formed of refractory metal(s) (eg, cobalt, iron, nickel, tungsten, and/or molybdenum). Additionally, the metal layer may be formed using deposition processes with good step coverage properties, eg, using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (eg, sputtering). The metal layer formed between the layers also covers the surface of the interlayer dielectric layer 102 around the contact holes. After that, a chemical mechanical polishing (CMP) process may be used to perform chemical mechanical polishing on the top surface of the deposited metal layer until exposed. The top surface of the interlayer dielectric layer 102 to form the contact plugs 106 a and 106 c and the combined contact structure 106 b in the interlayer dielectric layer 102 .

Referring to FIG. 2D, another embodiment of the present invention provides an electrical contact structure for a semiconductor device, including a plurality of contact plugs 106, which are formed at the boundary (or referred to as the boundary) of the core element region I of the semiconductor device. The tops of the at least two contact plugs 106 of the region, the interface region, the interface region) I-2 are connected together by a contact pad 109b with a larger area. The core element area I is a device dense area, and the peripheral circuit area II around it is a device sparse area. The tops of the contact plugs 106 in the area (referred to as the central area) I-1 at the boundary of the core element area 1 are provided with independent contact pads 109a, and each contact pad 109a is in a one-to-one correspondence with the corresponding The top of the contact plug 106 is electrically contacted.

All the contact plugs 106 of the I-2 at the boundary of the core element region 1 connected together at the top through the corresponding contact pads 109b constitute an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, that is, at the boundary of the core element region 1 All the contact plugs 106 connected together at the top of I-2 form a combined contact structure with a larger top cross-sectional area at the boundary of I-2.

The method shown in FIGS. 1A to 1D can reduce the number of deposition processes under the same number of photolithography, so that all the contact plugs 106 connected at the top are integrally formed.

Referring to FIG. 2D and FIG. 11 , in another embodiment of the present invention, the semiconductor device is a dynamic random access memory (DRAM), the core element area is a storage array area of the DRAM memory, and the core element is a storage transistor, The electrical contact structure is a storage node contact portion connected to the capacitor structure. That is, each contact plug in the central area I-1 of the core element area I is connected to a capacitor structure (as shown by 705a in FIG. 11 ), and a combined contact structure in I-2 at the boundary of the core element area I is connected A capacitor structure (shown as 705b in FIG. 11) is connected, and the capacitor structure at the boundary has a first width W1, and the capacitor structure within the boundary I-2 of the core element region I has a second width W2, due to the existence of the combined contact structure with a larger top cross-sectional area formed by I-2 at the boundary of the core element region I, it can provide sufficient process margin for the formation process of the capacitor structure at the boundary to facilitate Increasing the first width W1 of the capacitor structure of I-2 at the boundary, so that the first width W1 is greater than the second width W2, and then, on the one hand, the collapse of the capacitor structure formed at the boundary is avoided; , so that the capacitance structure at the boundary and the combined contact structure below can have a larger contact area, reducing the contact resistance, which is conducive to improving the electrical performance of the device; more importantly, all the boundaries at the boundary can have a larger contact area. The size of the capacitor structure is increased, which can buffer the density difference of the circuit pattern between the core element region I and the peripheral circuit region II, so that the optical proximity effect can be improved when the photolithography process and/or the etching process are performed, and the sparse/ The dense load effect ensures the consistency of the capacitance structure above the contact plug 106a of the area (ie, the central area) I-1 at the boundary of the core component area I, and prevents the occurrence of contact plugs at some positions in the core component area I. The capacitor structure above the plug is abnormal or the capacitor structure above the contact plug of I-2 at the boundary collapses. Optionally, the first width W1 is greater than 1.5 times the second width W2.

2A to 2D are schematic cross-sectional views of a device in a method for manufacturing an electrical contact structure of a semiconductor device according to another embodiment of the present invention. Referring to FIGS. 2A to 2D , the present embodiment further provides a method for manufacturing an electrical contact structure of a semiconductor device, including the following steps:

First, referring to FIG. 2A , a semiconductor substrate 100 is provided, which includes a core element region I and a peripheral circuit region II. A plurality of shallow trench isolation structures (not shown) are formed in the semiconductor substrate 100, and the shallow trench isolation structures define the boundary between the core element region I and the peripheral circuit region II on a two-dimensional plane (ie, define the boundary between the core element region I and the peripheral circuit region II). I-2) at the boundary of the core element area I, and also defines the active area 101 corresponding to each core element in the core element area I and the active area 101 corresponding to the peripheral elements in the peripheral circuit area II .

Next, referring to FIG. 2A , the first interlayer dielectric layer 102 is covered on the semiconductor substrate 100 . In addition, an etch stop layer (not shown) can be formed between the semiconductor substrate 100 and the first interlayer dielectric layer 102; through the first photolithography process, a first mask is formed on the first interlayer dielectric layer 102 pattern 103, the first mask pattern 103 defines the position of each contact plug, and then, using the first mask pattern 103 as an etching mask, the first interlayer dielectric layer 102 is anisotropically etched to form a through-hole The first interlayer dielectric layer 102 is described and exposes the contact holes 102a, 102b and 102c of the corresponding active region 101 below, each contact hole 102a is located in the central region I-1 of the core element region 1 and exposes the central region The active region 101 of the corresponding core element in I-1, each contact hole 102b is located at the boundary of the core element region I at I-2 and exposes the active region 101 of the corresponding core element in the boundary I-2, each The contact holes 102c are located in the peripheral circuit region II and expose the active regions 101 of the corresponding peripheral elements.

2B, after the contact holes 102a-102c are formed, an ashing process or a wet cleaning process may be performed to remove the first mask pattern 103, and fill the barrier metal layer (not shown) and A metal layer (not shown) made of tungsten and other materials is placed in each of the contact holes 102a-102c, and a chemical mechanical polishing (CMP) process is used to further chemically mechanically polish the top surface of the deposited metal layer until the first layer is exposed. The top surface of the interlayer dielectric layer 102 is formed to form contact plugs 106 in the interlayer dielectric layer 102. The bottom of each of the contact plugs 106 in the core element region I is in contact with the active region 101 of the corresponding core element. The bottom of each of the contact plugs 106 in the peripheral circuit area II is in contact with the active area 101 of the corresponding peripheral element.

Next, referring to FIG. 2C , a second interlayer dielectric layer 107 and a second mask pattern 105 may be formed on the first interlayer dielectric layer 102 and the contact plugs 106 , and the second mask pattern 105 is subjected to a second photolithography. The process forms a trench that defines a trench for connecting the tops of at least two contact plugs 106 corresponding to I-2 at the boundary. Using the second mask pattern 105 as a mask, the second interlayer dielectric layer 108 is etched to form trenches exposing the tops of the corresponding contact plugs 106, wherein the corresponding trenches 108b at the boundary I-2 will be at least The tops of the two contact plugs 106 and the space therebetween are exposed, and the tops of the corresponding contact plugs 106 are exposed by the trenches 108a within I-2 at the boundary of the core element region 1 (ie, the central region I-1) , the trenches 108c in the peripheral circuit region II expose the tops of the corresponding contact plugs 106 . The trench 108b exposes at least the top of the outermost one of the contact plugs 106 at the boundary I-2.

Referring to FIG. 2D , the second mask pattern 105 can be removed by an ashing process of oxygen, ozone or ultraviolet rays or by a wet cleaning process, and a barrier metal layer (not shown) and a metal layer are sequentially formed in the trenches 108 a ˜ 108 c (not shown). The barrier metal layer can reduce or prevent metal materials disposed in the contact holes and trenches from diffusing into the interlayer dielectric layer 102 . Then, each of the contact hole trenches 108a-108c is filled with a metal layer to form mutually independent contact pads 109a, 109b, and 109c. The contact pads 109a are formed on the tops of the contact plugs 106 in the central region I-1 of the core element region I, and are in electrical contact with the tops of the corresponding contact plugs 106 in a one-to-one correspondence, and the contact pads 109b are formed on the core The tops of the contact plugs 106 of I-2 at the boundary of the element region 1 are in electrical contact with the tops of the corresponding contact plugs 106 in one-to-one correspondence, so that all the tops in the boundary I-2 are connected together. The contact plugs 106 constitute an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure.

The method shown in FIGS. 2A to 2D can make each contact plug (including the contact plug connected at the top and the independent contact plug) equally divided into two heights under the same number of photolithography Therefore, the aspect ratio of the contact holes or trenches corresponding to the etching process and the filling process corresponding to the height of each section can be reduced, so as to ensure the performance of the formed electrical contact structure.

1D and FIG. 2D, an embodiment of the present invention further provides a semiconductor device, including a semiconductor substrate 100, the semiconductor substrate 100 has a core element region I, and a plurality of cores are formed in the core element region I components; an interlayer dielectric layer 102 covering the semiconductor substrate 100 ; and an electrical contact structure of a semiconductor device according to various embodiments of the present invention, the electrical contact structure being formed on the interlayer dielectric layer 102 In the electrical contact structure, the bottom of each of the contact plugs of the electrical contact structure is in contact with the active region 101 of the corresponding core element, and in the electrical contact structure, at least a portion of the electrical contact structure is formed at the boundary of the core element region. The tops of the two contact plugs are joined together.

Please refer to FIG. 2D and FIG. 11 , the semiconductor device further includes a capacitor structure, which is formed on the interlayer dielectric layer 107 and whose bottom is in contact with the electrical contact structure. 705b in FIG. 11 ) has a first width W1, and the capacitance structure within I-2 at the boundary of the core element region I (ie, the central region I-1) (as shown in 705a in FIG. 11 ) Having a second width W2, the first width W1 is greater than the second width W2.

It should be noted that the technical solution of the present invention is not limited to the above-mentioned method for forming an electrical contact structure, and any method that can be used to form an independent contact plug and a contact plug whose tops are connected together can be applied to the present invention. The technical solution of the invention, for example, in another example of the present invention, after the structure of FIG. 1A is formed and the mask pattern 103 is removed, the sacrificial layer is no longer filled, but the material of the contact plug (including the barrier metal layer and the material of the contact plug) is directly filled. metal layer) to form independent contact plugs, then the mask pattern 105 in FIG. 1B is formed on the interlayer dielectric layer 102 and the independent contact plugs, and the interlayer dielectric layer 102 is further etched to form exposed The trenches 102d at the boundary 1-2 contact the top sidewalls of the at least two plugs 102b, after which the trenches 102d are filled with conductive material to form contact pads (not shown) that connect the trenches 102d The exposed tops of the contact plugs 102b are joined together.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 11 . 3A is a schematic top view of a device structure in a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIGS. 3B to 11 are devices along line aa' in FIG. 3A in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Schematic diagram of the structural section.

First, referring to FIGS. 3A and 3B , a semiconductor substrate 300 having a plurality of core elements (ie, memory transistors) is provided, and the specific process includes:

First, referring to FIGS. 3A and 3B , a semiconductor substrate 300 a is provided, which includes a core element region I and a peripheral circuit region II. In this embodiment, the core element area I is a storage area, the core element to be formed on the core element area I includes a selection element, and then a data storage element is connected above the core element. The selection element is, for example, a MOS transistor or a diode. The data storage element is, for example, It is a capacitor, a variable resistor, etc., a selection element and a corresponding data storage element form a storage unit. Peripheral circuits TR (eg, NMOS transistors and PMOS transistors, diodes or resistors) may be formed in the peripheral circuit region II to control the memory cells. A plurality of shallow trench isolation structures 301 are formed in the semiconductor substrate 300a, and the shallow trench isolation structures 301 define the boundary between the core element region I and the peripheral circuit region II on a two-dimensional plane (ie, define the core element region. At the boundary of I, I-2), the active area AA1 corresponding to each core element in the core element area I and the active area AA2 corresponding to the peripheral elements in the peripheral circuit area II are also defined. The distribution of the active areas AA1 on the two-dimensional plane is strip-shaped and extends along the first direction, and the active areas AA1 may be arranged in a dislocation arrangement on the surface of the semiconductor substrate 300a.

Then, the buried word line WL formed in the semiconductor substrate 300a, the buried word line WL is generally buried in a predetermined depth position in the semiconductor substrate 300a, extends along the second direction (ie the row direction) and passes through the shallow trench isolation In the structure 301 and the active area AA1, the second direction is not perpendicular to the first direction of the active area AA1. The buried word line WL is used as a gate to control the switching of the memory cell, which includes but is not limited to doped semiconductor materials (such as doped silicon), metal materials (such as tungsten, aluminum, titanium, or tantalum), conductive metal materials (such as titanium nitride, tantalum nitride, or tungsten nitride), or metal-semiconductor compounds (such as silicon nitride). Usually, the sidewall and bottom of the buried word line WL are surrounded by a gate dielectric layer (not shown), and the top of the buried word line WL is buried by the gate capping layer 302 . Since the buried word line WL is not the focus of the present invention, the related fabrication process can refer to known technical solutions in the art, and will not be described in detail here. In addition, the gate dielectric layer may include silicon oxide or other suitable dielectric materials, the buried word lines WL may include aluminum, tungsten, copper, titanium aluminum alloy, polysilicon or other suitable conductive materials, and the gate capping layer 302 may include Including silicon nitride, silicon oxynitride, silicon nitride carbide or other suitable insulating materials.

Furthermore, a second type of dopant, such as a P-type or N-type dopant, can be doped into the active region AA1 on both sides of the buried word line WL to form a source region and a drain region (uniformly defined as S/ D1), one of the AA1 on both sides of the buried word line WL is located at the center of AA1 corresponding to the predetermined bit line contact structure, and the other is located at the predetermined storage node contact structure at the end of the active region AA1. The word lines WL and S/D1 may constitute or define a plurality of MOS memory transistors formed on the core element region I of the semiconductor device. In addition, at the same time as S/D1 is formed, source regions and drain regions corresponding to peripheral transistors (uniformly defined as S/D2 ) may also be formed in peripheral circuit region II. After the S/D1 and S/D2 are formed, an etch stop layer 303 may be further formed on the semiconductor substrate 300a, and the etch stop layer 303 covers the S/D1 and S/D2, and its material For example, silicon nitride (SiN) and/or silicon oxide (SiO ₂ ) and the like are included.

Then, a plurality of bit line contact plugs (bit line contacts, not shown) and a bit line BL located above the bit line contact plugs are formed on S/D1 serving as a drain region of the core element region I, and the bit line The contact plug can be formed by first etching S/D1 between two adjacent WLs formed in one active area AA1 to form a groove, and then forming a metal silicide in the groove. The plurality of bit lines BL are parallel to each other and extend along a third direction (ie, the column direction) perpendicular to the buried word line WL, and simultaneously span the active area AA1 and the buried word line WL. Each bit line BL includes, for example, a semiconductor layer (such as polysilicon, not shown), a barrier layer (such as Ti or TiN, not shown), and a metal layer (such as tungsten, aluminum, or copper, etc.) stacked in sequence, not shown) and a mask layer (eg, including silicon oxide, silicon nitride or silicon carbonitride, not shown).

In addition, on the peripheral circuit region II of the semiconductor substrate 300a, at least one gate structure G1 is formed, which includes, for example, a gate dielectric layer (not shown) and a gate layer (not shown) stacked in sequence. ). In a specific example, the gate layer of the gate structure G1 and the semiconductor layer or metal layer of the bit line BL are formed together. Further, the sidewall spacers 304 surrounding each bit line BL and the gate structure G1 can be formed by using different processes or the same process. For example, the fabrication process of the sidewall spacers of the gate structure G1 can be performed first, so that the sidewall spacers 304 of the gate structure G1 include silicon oxide or silicon oxynitride (SiON), and then the fabrication process of the sidewall spacers of the bit line BL is performed. The sidewall spacers of the bit line BL may include silicon nitride. In addition, in the fabrication process of the sidewall spacers of the gate structure G1, an etching back fabrication process may be performed again, so that the overall height of the gate structure G1 is lower than the bit lines BL.

Then, the storage node contact structure can be formed by using the method for fabricating the electrical contact structure of the semiconductor device shown in FIGS. 1A to 1D or FIGS. 2A to 2D of the present invention. For example, the manufacturing method of the contact structure to form the storage node contact structure, the specific process is as follows:

First, referring to FIG. 4 , after providing the semiconductor substrate 300 with the bit line BL, the source region and the drain region S/D1 of the core element, an interlayer dielectric layer 400 is formed on the semiconductor substrate 300 , and its material includes, for example, Silicon oxide, silicon nitride or low-K dielectrics, etc. Specifically, the interlayer dielectric layer 400 is fully covered on the semiconductor substrate 300 through a deposition process, and the interlayer dielectric layer 400 fills the space between the bit lines BL and connects the bit lines BL with the gate structure G1 and its structure. The sidewall spacers 304 are buried inside, and then the interlayer dielectric layer 400 is planarized by chemical mechanical polishing and other processes to form the interlayer dielectric layer 400 having a flat top surface as a whole. The top surface of the planarized interlayer dielectric layer 400 is at least not lower than the top surface of each bit line BL.

Next, referring to FIG. 4 , a first mask pattern (not shown) is formed on the interlayer dielectric layer 400 through a photolithography process, and the first mask pattern defines the positions of the contact structures of each storage node. Then, use The first mask pattern is used as an etching mask to anisotropically etch the interlayer dielectric layer 400 to form contact holes 401a, 401a, 401a, 401a, 401a, 401a, 401a penetrating the interlayer dielectric layer 400 and exposing the corresponding S/D1 used as source regions below. 401b and 401d, 401e, each contact hole 401a is located in the central region I-1 of the core element region 1 and exposes S/D1 serving as a source region of the corresponding core element in the central region I-1, each contact The hole 401b is located at the boundary I-2 of the core element region I and exposes the S/D1 serving as a source region of the corresponding core element in the boundary I-2, and each contact hole 401d, 401e is located in the peripheral circuit region II and The source/drain regions S/D2 or gate structures G1 of the corresponding peripheral elements are exposed.

Then, referring to FIG. 5, after the contact holes 401a, 401b and 401d, 401e are formed, an ashing process or a wet cleaning process may be performed to remove the first mask pattern and fill the sacrificial layer 501 in each of the contact holes 401a, 401b and 401d, 401e. The sacrificial layer 501 may be formed of a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL), which may enable the contact holes 401a, 401b and 401d, 401e with a high aspect ratio to be filled with the sacrificial layer 501 .

4 and 5, a second mask pattern (not shown) may be formed on the interlayer dielectric layer 400 and the sacrificial layer 501. The tops of the at least two contact holes 401b are connected to the trench 401c. Using the second mask pattern as a mask, the interlayer dielectric layer 400 at the boundary I-2 is etched to form at least two contact holes 401b corresponding to the boundary I-2 (including the one closest to the peripheral circuit region II). at least one of a row of contact holes) is connected to the top of the trench 401c. The trench 401c spans at least one of the outermost word lines WL of I-2 at the boundary.

Then, referring to FIG. 6, the sacrificial layer 501 and the second mask pattern in the contact holes 401a, 401b and 401d, 401e may be removed using an ashing process of oxygen, ozone or ultraviolet light or through a wet cleaning process to re-exposed the respective Contact holes 401a, 401b and 401d, 401e and trench 401c.

Next, referring to FIG. 7, a barrier metal layer (not shown) may be formed in the contact holes 401a, 401b and 401d, 401e and the trench 401c. For example, the barrier metal layer may cover the contact holes 401a, 401b and 401b with a uniform thickness. 401d, 401e and the inner walls of the trench 401c and the top surface of the interlayer dielectric layer 400. The barrier metal layer can reduce or prevent the metal material disposed in the contact holes 401 a , 401 b and 401 d , 401 e and the trench 401 c from diffusing into the interlayer dielectric layer 400 . For example, the barrier metal layer may be formed of Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or any combination thereof, using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition Deposition (PVD) (eg, sputtering) and other processes. Then, a metal layer is filled in each of the contact holes 401a, 401b and 401d, 401e and the trench 401c to form the contact plugs 501a, 501d, 501e and the combined contact structure 501b. Therein, the metal layer may be formed of refractory metal(s) (eg, cobalt, iron, nickel, tungsten, and/or molybdenum). Additionally, the metal layer may be formed using deposition processes with good step coverage properties, eg, using chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (eg, sputtering). The formed metal layer also covers the surface of the interlayer dielectric layer 400 around the contact holes and the trenches, after which a chemical mechanical polishing (CMP) process may be used to chemically mechanically polish the top surface of the deposited metal layer until exposed. The top surface of the interlayer dielectric layer 400 is removed to form the contact plugs 501 a , 501 d , 501 e and the combined contact structure 501 b in the interlayer dielectric layer 400 . The contact plug 501a serves as a storage node contact structure in the central region I-1 of the core element region I, and is used for connecting with a capacitor structure formed on the central region I-1 subsequently. The combined contact structure 501b is connected by at least two top contact plugs in I-2 at the boundary of the core element region 1 (including the outermost contact plug at the boundary that is in electrical contact with the outermost source region of I-2 at the boundary. plug) is formed as the storage node contact structure in I-2 at the boundary of the core element region 1, for connecting with the subsequent capacitor structure formed above the boundary at I-2, the top structure of the combined contact structure 501b (that is, the top phase The top connection structure formed by all the contact plugs joined together is located above the bit line BL and spans at least one word line WL, and the combined contact structure 501b is aligned parallel to the bit line BL. The combined contact structure 501b is, for example, an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure, which can span at least one of the word lines WL in the outermost active region AA1 at the boundary I-2. The contact plug 501d is used as a contact structure for the gate structure G1 of the peripheral circuit region II, for pulling the gate structure G1 outward, and the contact plug 501e is used as a contact structure for the source region or the drain region S/D2 of the peripheral circuit region II , used to lead out the source or drain region S/D2 of the peripheral circuit region II.

After that, a conventional capacitor structure fabrication method in the art can be used to fabricate a corresponding capacitor structure on the core element region I. Please refer to FIGS. 8 to 11. The specific process is as follows:

First of all, please refer to Figure 8. You can form the underlying support layer 600 and No. 400, 501D, 501E, and combined contact structure 501B through the process of chemical gas deposition, spinning and other processes. A sacrificial layer 611, an intermediate supporting layer 601, a second sacrificial layer 612 and a top supporting layer 602, wherein the bottom supporting layer 600 is used to support the bottom electrode layer formed later on the one hand, and is also used to isolate the semiconductor liner on the other hand Internal components of the bottom 300 and components such as capacitors above. The formation process of the underlying support layer 600 may also be a thermal oxidation process. The materials of the bottom support layer 600 , the middle support layer 601 and the top support layer 602 include but not limited to silicon nitride, and the materials of the first sacrificial layer 611 and the second sacrificial layer 612 include but not limited to silicon oxide. The thickness of the first sacrificial layer 611 defines the height of the intermediate support layer 601 to be formed subsequently. Therefore, the thickness of the first sacrificial layer 611 can be adjusted according to the height of the intermediate support layer 601 to be formed. Under the condition that the thicknesses of the first sacrificial layer 611 and the intermediate support layer 601 are determined, the thickness of the second sacrificial layer 612 defines the height of the top support layer 602 formed subsequently. Therefore, the second sacrificial layer The thickness of 612 can be adjusted according to the height position of the top support layer 602 to be formed. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two intermediate supporting layers 601 may be stacked between the bottom supporting layer 600 and the top supporting layer 602, and between adjacent intermediate supporting layers There are sacrificial layers for isolation.

Next, referring to FIG. 9, a plurality of capacitor holes 700a and 700b are formed in the sacrificial layer and the support layer on the core element region I, and the capacitor hole 700a is formed in the central region I-1 of the core element region I and exposing the surface of the contact plug 501a in the central area I-1 for forming the capacitor structure in the central area I-1. The capacitance hole 700b is formed at the boundary I-2 of the core element region 1 and exposes the surface of the combined contact structure 501b at the boundary I-2 for forming the capacitance structure in the boundary I-2. The capacitor holes 700a and 700b are arranged in an array, and the capacitor hole 700b has a first width W1, and the capacitor hole 700a has a second width W2, optionally, W1 is not less than 1.5*W2. Specifically, a mask layer (not shown) is formed on the top support layer 602, the mask layer is patterned to expose the areas where the capacitor holes 700a and 700b are to be formed, and then the patterned mask The mold layer is used as a mask, and the top supporting layer 602, the second sacrificial layer 612, the middle supporting layer 601, the first sacrificial layer 611 and the bottom supporting layer 600 are sequentially etched to remove the peripheral circuit area II and the core The supporting layer and the sacrificial layer on the edge region of the element region I, and a plurality of capacitor holes 700a and 700b are formed in the core element region I, and then the patterned mask layer is removed. The capacitor holes 700a and 700b penetrate through the top support layer 602, the second sacrificial layer 612, the middle support layer 601, the first sacrificial layer 611 and the bottom support layer 600 in sequence to expose the corresponding parts of the core element region I. On the surfaces of the contact plug 501a and the combined contact structure 501b, optionally, all the capacitor holes are arranged in a hexagonal close-packed arrangement. In addition, the capacitor hole may be an inverted trapezoidal hole, a rectangular hole, etc., and the sidewalls thereof may be irregular in shape, such as having curved sidewalls, etc., which are not specifically limited herein. In addition, in this embodiment, the underlying support layer 600 is still reserved on the peripheral circuit region II, so as to protect the device surface of the peripheral circuit region II in the subsequent capacitor formation process.

It can be understood that, due to the large area of the combined contact structure 501b, sufficient process margin can be provided for the fabrication of the capacitor hole 700b at the border I-2, and the width of the capacitor hole 700b at the border I-2 can be made larger. large, avoid abnormal deformation or collapse of the capacitor hole 700b at the boundary, and at the same time make the subsequent capacitor structure and the combined contact structure formed at the boundary have a larger contact area, thereby reducing the contact resistance reduction, which is conducive to improving electrical properties of the device. In addition, because the width of the capacitor hole 700b at the boundary I-2 is larger, the density difference of the circuit patterns in the peripheral circuit region II and the core element region I can be buffered, so that the photolithography process and/or the etching process of the capacitor hole can be performed during the photolithography process and/or the etching process of the capacitor hole. It can improve the optical proximity effect, reduce the sparse/dense load effect, ensure the consistency of the capacitance holes within the boundary of the core component area, and prevent the abnormality of the capacitance holes above the contact plugs at some positions in the core component area, which may cause subsequent formation. The problem of the failure of the capacitor structure.

Referring to FIG. 10 , a lower electrode layer 701 is formed to cover the side walls and bottom walls of the capacitor holes 700 a and 700 b. The shape of the lower electrode layer 701 in the capacitor holes 700a and 700b is consistent with the shape of the capacitor holes 700a and 700b, so that the lower electrodes located in the capacitor holes 700a and 700b Layer 701 constitutes a cylindrical structure. Specifically, the lower electrode layer 701 can be formed on the basis of the deposition process combined with the planarization process. For example, first, a patterned protective layer (not shown) such as photoresist can be used to protect the peripheral circuit region II, and Expose the top surface of the top support layer 602 and the surfaces of the capacitor holes 700a and 700b in the core element region 1; then, a process such as physical vapor deposition or chemical vapor deposition is used to form an electrode material layer on the patterned protective layer and the core On the exposed surface of the element region I, the electrode material layer covers the bottoms and sidewalls of the capacitor holes 700a, 700b, as well as the top support layer 602 of the core element region I and the patterned protective layer of the peripheral circuit region II top surface; then, a planarization process (eg, chemical mechanical polishing process CMP) is performed to remove the portion of the electrode material layer above the top support layer 602, so that the remaining electrode material layer is only formed on the capacitor hole 700a and 700b, to form a lower electrode layer 701 having a plurality of cylindrical structures, and then remove the patterned protective layer. In addition, in this embodiment, the contact plugs 501a, 501b are exposed through the capacitor holes 700a, 700b, respectively, so that the bottom of the cylindrical structure of the lower electrode layer 701 can be formed with the contact plugs 501a, 501b are in electrical contact. Further, the lower electrode layer 701 may be a polysilicon electrode or a metal electrode. When the lower electrode layer 701 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti may also be used. When the lower electrode layer 701 is a polysilicon electrode, it can be formed using zero-doped and/or doped polysilicon material.

Please continue to refer to FIG. 10 , each of the sacrificial layers is removed and each of the support layers is retained. All the support layers form a lateral support layer to laterally connect the plurality of cylindrical structures of the lower electrode layer 701 . to support the lower electrode layer 701 on the sidewalls of each of the cylindrical structures. Specifically, the top support layer 602 is located at the top periphery of the plurality of cylindrical structures of the lower electrode layer 701 , the middle support layer 601 is located in the middle of the plurality of cylindrical structures of the lower electrode layer 701 , the bottom layer The support layer 600 is located at the bottom periphery of the plurality of cylindrical structures of the lower electrode layer 701 . The specific process includes: forming a first opening (not shown) in the top support layer 602 and exposing the second sacrificial layer 612; and removing the second sacrificial layer 612 by using a wet etching process ; form a second opening in the intermediate support layer 601 to expose the first sacrificial layer 611; use a wet etching process to etch and remove the first sacrificial layer 611; wherein, one of the first openings is only overlapping with one of the capacitor holes 700a or 700b, or one of the first openings simultaneously overlaps with a plurality of the capacitor holes 700a and/or 700b; one of the second openings only overlaps with one of the capacitor holes 700a or 700b 700b overlaps, or one of the second openings simultaneously overlaps a plurality of the capacitor holes 700a and/or 700b. Furthermore, the second opening may be perfectly aligned with the first opening.

Referring to FIG. 11 , a capacitive dielectric layer 702 is formed on the inner and outer surfaces of the lower electrode layer 701 and the exposed surfaces of each of the supporting layers by chemical vapor deposition or atomic layer deposition. Then, an upper Electrode layers 703 are formed on the inner and outer surfaces of the capacitive dielectric layer 702 . The capacitor dielectric layer 702 covers the inner and outer surfaces of the cylindrical structure of the lower electrode layer 701 to make full use of the two opposite surfaces of the lower electrode layer 701 to form a capacitor with a larger electrode surface area. Preferably, the capacitor dielectric layer 702 may be a high-K dielectric layer such as metal oxide. Further, the capacitor dielectric layer 702 is a multi-layer structure, for example, a two-layer structure of Ha-zirconia. The upper electrode layer 703 can be a single-layer structure or a multi-layer structure. When the upper electrode layer 703 is a single-layer structure, such as a polysilicon electrode, it can also be a metal electrode. When the upper electrode layer 703 is a metal electrode For example, titanium nitride (TiN) can be used. The upper electrode layer 703 can form a capacitor with the capacitor dielectric layer 702 and the lower electrode layer 701 both inside the cylindrical structure and outside the cylindrical structure. In addition, on the edge region of the core element region I (ie, the boundary region of the capacitor hole array), due to the existence of the lateral support layers (ie, the middle support layer 601, the top support layer 602), the capacitor dielectric layer 702 and the upper electrode The layers 703 all have sidewall structures with uneven topography, and the sidewall structures with uneven topography correspond to the middle support layer 601 and the top support layer 602 outside the cylindrical structure barrel of the lower electrode layer 701 . , so that the part of the upper electrode layer 703 on the edge region of the core element region I (ie, the boundary region of the capacitor hole array) corresponds to the middle support layer 601 and the top support layer 602 to be far away from the lower electrode The direction of the layer 701 is convex, making the boundary of the capacitor array in the core element region I uneven. In addition, in this embodiment, the capacitor dielectric layer 702 and the upper electrode layer 703 are further extended to cover the surface of the underlying support layer 600 remaining on the peripheral circuit region II in sequence.

Referring to FIG. 11 , a chemical vapor deposition process may be used to form an upper electrode filling layer 704 on the surface of the upper electrode layer 703 , and the upper electrode filling layer 704 fills the gap between the upper electrode layers 703 . That is to say, the upper electrode filling layer 704 fills the gaps between adjacent cylindrical structures and covers the above-formed structures. Preferably, the material of the upper electrode filling layer 704 includes undoped or boron-doped polysilicon. Thus, the fabrication of the capacitor array is completed, that is, the capacitor structure 705a is formed at the central region I-1, and the capacitor structure 705b is formed at the boundary I-2.

Since the width of the capacitor hole 700b is larger than the width of the capacitor hole 700a, the width of the capacitor structure 705b at the boundary I-2 (ie W1) is greater than the width of the capacitor structure 705a at the central region I-1 (ie W2), for example W1=W2*1.5. And because the size of the capacitor hole 700b is relatively large, it is favorable for material filling, thereby improving the performance of the capacitor structure formed at the boundary I-2.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. And, the above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure belong to the protection scope of the technical solutions of the present invention. .

In addition, it should also be noted that, unless otherwise specified or pointed out, the terms "first", "second" and "third" in the specification are only used to distinguish various components, elements, steps, etc. in the specification. It is not used to represent the logical relationship or sequence relationship between various components, elements, steps, etc. The term "and/or" in the text means both or one of the two.

Claims (17)

1. An electrical contact structure for a semiconductor device, wherein the electrical contact structure comprises: a plurality of contact plugs formed above the core elements in the core element region of the semiconductor device, and the bottoms of the respective contact plugs are in contact with the active regions of the corresponding core elements, Wherein, the tops of at least two contact plugs formed at the boundary of the core element region are connected together, and the contact plugs whose tops are connected together include the outermost contact plug at the boundary. 2 . The electrical contact structure of a semiconductor device according to claim 1 , wherein all the contact plugs whose tops are connected together form an inverted U-shaped electrical contact structure or a comb-shaped electrical contact structure. 3 . 3 . The electrical contact structure of a semiconductor device according to claim 2 , wherein a plurality of word lines intersecting with a plurality of the active regions and a plurality of word lines intersecting with the word lines are formed in the core element region of the semiconductor device. 4 . A vertical bit line with all the contact plugs joined together on top of the structure spans at least one of the word lines and is aligned with the bit line. 4 . The electrical contact structure of a semiconductor device according to claim 1 , further comprising contact pads that are independent of each other, formed on top of other contact plugs in the core element region, and corresponding to one another. 5 . Make electrical contact with the top of the corresponding contact plug. 5 . The electrical contact structure of a semiconductor device according to claim 1 , wherein all the contact plugs connected together at the top are integrally formed structures, or at least two contact plugs at the boundary are formed. 6 . The plugs are joined together at the top by attaching the same contact pad. 6 . The electrical contact structure of a semiconductor device according to claim 1 , wherein a capacitor structure is connected to the electrical contact structure, wherein the capacitor structure at the boundary has a first width, and the core element region has a first width. 7 . The capacitive structure within the boundary has a second width, and the first width is greater than the second width. 7. The electrical contact structure for a semiconductor device according to claim 6, wherein the first width is greater than 1.5 times the second width. 8. A semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate has a core element region, and a plurality of core elements are formed in the core element region; an interlayer dielectric layer covering the semiconductor substrate; and, The electrical contact structure of a semiconductor device according to any one of claims 1 to 7, wherein the electrical contact structure is formed in the interlayer dielectric layer, and the bottom of each of the contact plugs of the electrical contact structure is connected to The active regions of the corresponding core elements are in contact, and the tops of at least two contact plugs formed at the boundaries of the core element regions in the electrical contact structure are connected together, and all the tops are connected. The outermost contact plugs at the boundary are included in the contact plugs. 9 . The semiconductor device of claim 8 , wherein the semiconductor device is a DRAM, the core element area is a storage area, the core element is a storage transistor, and the electrical contact structure is a storage node contact structure. 10 . . 10 . The semiconductor device according to claim 9 , wherein the semiconductor device further comprises: a capacitor structure formed on the interlayer dielectric layer and the bottom of which is in contact with the electrical contact structure, and the boundary is at the boundary. 11 . The capacitor structure has a first width, and the capacitor structure within the boundary of the core element region has a second width, and the first width is greater than the second width. 11. The semiconductor device of claim 10, wherein the first width is greater than 1.5 times the second width. 12. The semiconductor device of claim 9, wherein the semiconductor device comprises a plurality of word lines and a plurality of bit lines, and each of the word lines is associated with a plurality of the said core element regions. The source regions intersect, the bit line is perpendicular to the word line, and all the contact plugs joined together at the top form a structure that spans at least one of the word lines and is aligned with the bit line. 13. A method for manufacturing an electrical contact structure of a semiconductor device, comprising: providing a semiconductor substrate, the semiconductor substrate having a core element region in which a plurality of core elements are formed; An interlayer dielectric layer is formed on the semiconductor substrate, and a plurality of contact holes are formed in the interlayer dielectric layer, each of the contact holes penetrates the interlayer dielectric layer and exposes the active elements of the corresponding core elements Area; Contact plugs are formed in the contact holes, and the bottom of each of the contact plugs is in contact with the active region of the corresponding core element, and at least two contact plugs formed at the boundary of the core element region have The tops are connected together, and all the contact plugs in which the tops are connected include the outermost contact plug at the boundary. 14 . The method for manufacturing an electrical contact structure of a semiconductor device according to claim 13 , wherein when forming a plurality of contact holes in the interlayer dielectric layer, a photolithography process is performed first in the interlayer dielectric layer. 15 . forming mutually independent contact holes, and then etching the interlayer dielectric layer through another photolithography process, so that the tops of at least two contact holes at the boundary are connected, so as to form contact plugs whose tops are connected together plug; or, When multiple contact holes are formed in the interlayer dielectric layer, mutually independent contact holes are formed in the interlayer dielectric layer through a single photolithography process; then, mutually independent contact plugs are formed in the contact holes, and then , the interlayer dielectric layer is etched through another photolithography process to form trenches exposing the top sidewalls of at least two contact plugs at the boundary, and contact pads are formed in the trenches, so that the corresponding the tops of the contact plugs together; or, When multiple contact holes are formed in the interlayer dielectric layer, mutually independent contact holes are formed in the interlayer dielectric layer through a single photolithography process; then, mutually independent contact plugs are formed in the contact holes, and then , forming another interlayer dielectric layer to cover the interlayer dielectric layer with the contact plugs; then etching the other interlayer dielectric layer through another photolithography process to form at least a The grooves in the tops of the two contact plugs in which the contact pads are formed such that the tops of the respective contact plugs are joined together. 15. A method for manufacturing a semiconductor device, comprising: using the method for manufacturing an electrical contact structure of a semiconductor device according to any one of claims 13 or 14, on a semiconductor substrate having a core element region Electrical contact structures are formed that make electrical contact with the corresponding core elements. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the core element region is a storage region, the core element is a storage transistor, the electrical contact structure is a storage node contact structure, and the semiconductor The method of fabricating the device also includes: forming the lower electrode of the capacitive structure on the electrical contact structure forming a capacitive dielectric overlying the lower electrode; and, The upper electrode of the capacitive structure is formed on the capacitive medium. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of providing a semiconductor substrate having a core element region comprises: providing a semiconductor substrate in which a plurality of active regions are defined; forming word lines in the semiconductor substrate, the word lines intersecting the active region; forming source regions and drain regions respectively in the active regions on both sides of the word line; forming a bit line contact structure on the drain region; and A bit line is formed on the bit line contact structure, the bit line intersecting the word line, wherein the bottom of the contact plug in the electrical contact structure is in contact with the source region.

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