CN111627865B - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor packaging structure, which comprises a first patterned conducting layer, a first power chip, a second power chip, a conducting adhesive layer, a second patterned conducting layer, a first conducting connecting element, a second conducting connecting element and a molding layer. The first power chip and the second power chip are embedded in the molding layer in a manner that the front surface and the back surface are reversed. In addition, one side of the first power chip and one side of the second power chip are fixed on the first patterned conductive layer through the conductive adhesive layer. The invention also discloses a manufacturing method of the semiconductor packaging structure.

Description

A kind of semiconductor package structure and its manufacturing method

technical field

The present invention relates to a package structure and a manufacturing method thereof, in particular to a semiconductor package structure and a manufacturing method thereof.

Background technique

With the substantial increase in the demand for credit and automotive electronics, the Quad Flat No-Lead (QFN) package structure has become an important package structure because of its better heat dissipation effect, lower impedance value and electromagnetic interference. semiconductor packaging technology.

In the QFN package structure, the copper clip technology is a technology generated in response to high power requirements. The copper sheet is designed in the shape of an arch bridge with a high and low drop. The copper sheet is bonded to the chip by a solder dispenser. It has a small resistance to carry a large current and can withstand the deformation caused by thermal stress, so it is suitable for Such as high power components such as transistors.

Please refer to FIGS. 1A to 1D , for a brief description of the part of the conventional package structure that utilizes the copper bridge technology to bond the transistors.

As shown in FIG. 1A , a solder paste layer 102 is formed on a lead frame 101 with screen printing. Next, as shown in FIG. 1B , a transistor chip 103 is placed on the solder paste layer 102 . Then, as shown in FIG. 1C , solder 104 is formed on the transistor wafer 103 . Finally, as shown in FIG. 1D , a bridging copper sheet 105 is placed on the corresponding solder paste layer 102 and solder 104 , and the lead frame 101 , the transistor chip 103 , and the bridging copper sheet are reflowed at a high temperature of 380 degrees Celsius after being reflowed The sheets 105 are joined to each other.

The above-mentioned processes and finished products have at least the following problems:

(1) The package structure uses lead frames and bridge copper sheets, so the height (thickness) of the package cannot be reduced, which limits its application field.

(2) Solder or solder paste contains a relatively high proportion of lead, and lead metal will cause environmental pollution and have a considerable impact on human health.

(3) The displacement of each component may occur before all components are fixed by the high temperature reflow process of 380 degrees Celsius, resulting in a decrease in accuracy.

Therefore, how to improve the above shortcomings to provide a semiconductor package structure capable of integrating high-power components and a manufacturing method thereof is one of the current important issues.

SUMMARY OF THE INVENTION

In view of the above, an object of the present invention is to provide a semiconductor package structure and a manufacturing method thereof, which can reduce the height of the semiconductor package structure containing high-power components and at the same time increase the electrical performance. Another object of the present invention is to provide a semiconductor package structure and a manufacturing method thereof, which can meet the requirements of environmental protection laws without using lead-containing processes.

In order to achieve the above object, the present invention provides a semiconductor package structure, which includes a first patterned conductive layer, a first power chip, a second power chip, a conductive adhesive layer, a second patterned conductive layer, a A first conductive connection element, a second conductive connection element and a molding layer.

The first power chip has a first front surface and a first back surface, and is disposed with the first front surface facing the first patterned conductive layer. The first front side of the first power chip has a first electrode layout, and the first back side has a second electrode layout. The second power chip is disposed adjacent to the first power chip, and has a second front surface and a second back surface, and the second back surface faces the first patterned conductive layer. The second front side of the second power chip has a third electrode layout, and the second back side has a fourth electrode layout. The conductive adhesive layer is electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer. In addition, the conductive adhesive layer is also electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer. The second patterned conductive layer is disposed opposite to the first patterned conductive layer, and the first back surface of the first power chip and the second front surface of the second power chip are disposed toward the second patterned conductive layer. The first conductive connection element is electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and is electrically connected between the third electrode layout of the second power chip and the second patterned conductive layer between. The second conductive connection element is electrically connected between the first patterned conductive layer and the second patterned conductive layer, and is electrically connected. The molding layer covers the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connection element and the second conductive connection element.

According to an embodiment of the present invention, the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip layout.

According to an embodiment of the present invention, the first power chip and the second power chip are respectively a transistor chip.

According to an embodiment of the present invention, the first electrode layout and the third electrode layout respectively include a gate electrode and a source electrode, and the second electrode layout and the fourth electrode layout respectively include a drain electrode.

According to an embodiment of the present invention, the drain electrode of the second electrode layout is electrically connected to the source electrode of the third electrode layout.

According to an embodiment of the present invention, the material of the molding layer is a molding compound, and the main matrix is phenolic resin, epoxy resin or silicon resin.

In addition, in order to achieve the above purpose, the present invention provides a method for manufacturing a semiconductor package structure, which includes the following steps: step 1: providing a carrier board; step 2: forming a first patterned conductive layer on a surface of the carrier board; Step 3: place a conductive adhesive layer on part of the first patterned conductive layer; Step 4: place a first power chip on the conductive adhesive layer, wherein a first electrode layout on a first front surface of the first power chip contacting the conductive adhesive layer; step 5: disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout on a second back side of the second power chip is in contact with the conductive adhesive layer; step 6: forming at least one conductive adhesive layer connecting elements on the first patterned conductive layer without the conductive adhesive layer, a second electrode layout on a first back side of the first power chip and/or a third electrode layout on a second front side of the second power chip; Step 7: Form a molding layer on the carrier board, and cover the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the conductive connection element; Step 8: Form a second patterned The conductive layer is on the molding layer, and is electrically connected to the conductive connecting element exposed on the molding layer; step 9: removing the carrier board.

According to an embodiment of the present invention, at least one drain electrode of the first back surface of the first power chip is electrically connected to at least one source electrode of the second front surface of the second power chip.

Furthermore, in order to achieve the above purpose, the present invention provides a method for manufacturing a semiconductor package structure, comprising the following steps: step 1: providing a carrier board; step 2: forming a first patterned conductive layer on a surface of the carrier board; step Step 3: Place a conductive adhesive layer on a portion of the first patterned conductive layer; Step 4: Place a first power chip on the conductive adhesive layer, wherein a first electrode on a first front surface of the first power chip is in contact with the layout on the conductive adhesive layer; step 5: disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout on a second back surface of the second power chip is in contact with the conductive adhesive layer; step 6: forming at least one second The conductive connection element is placed on the first patterned conductive layer without the conductive adhesive layer; Step 7: forming a molding layer on the carrier board, and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the first Two power chips and a second conductive connecting element; Step 8: A second electrode layout corresponding to a first back surface of the first power chip and a third electrode on a second front surface of the second power chip on the molding layer forming a plurality of openings in the layout; step 9: forming a first conductive connecting element on the openings; step 10: forming a second patterned conductive layer on the molding layer and electrically connected to the first conductive layer exposed to the molding layer a conductive connection element and a second conductive connection element; and step 11: removing the carrier board.

According to an embodiment of the present invention, the first conductive connection element and the second patterned conductive layer are simultaneously formed in one process.

Based on the above, in a semiconductor package structure and a manufacturing method thereof of the present invention, the first power chip and the second power chip, such as transistor chips, are arranged in an inverted manner, so as to shorten the electrical connection between the chips. distance to increase electrical performance. On the other hand, replacing the existing lead-containing and high-temperature reflow process with semiconductor technology can not only greatly improve the precision of the package structure, but also meet the trend of lead-free environmental protection technology.

Description of drawings

1A to FIG. 1D are schematic diagrams illustrating a manufacturing method for bonding transistors using a copper sheet bridging technique in a package structure of the prior art.

2A to 2I are schematic diagrams illustrating a method for fabricating a semiconductor package structure according to a first embodiment of the present invention.

3A to 3D are schematic diagrams illustrating a manufacturing method of a part of the semiconductor package structure according to the second embodiment of the present invention.

4 is a schematic diagram of a semiconductor package structure disposed on a circuit board according to a preferred embodiment of the present invention.

5 is a schematic diagram of a semiconductor package structure carrying electronic components disposed on a circuit board according to a preferred embodiment of the present invention.

Description of reference numerals

101, lead frame; 102, solder paste layer; 103, transistor chip; 104, solder;

105. Bridge copper sheet; 20. Semiconductor packaging structure; 21. Carrier board;

211, surface; 22, first patterned conductive layer; 23, conductive adhesive layer;

24. The first power chip; 241, the first front side; 242, the first back side;

25, the second power chip; 251, the second front; 252, the second back;

261, a first conductive connection element; 262, a second conductive connection element;

27, molding layer; 27a, protective layer;

271, 272, 273, 274, 275: openings;

28. Second patterned conductive layer; 30. Circuit board; 33. Electronic components;

32, 34: conductive bumps;

D1, D2: drain;

G1, G2: gate;

S1, S2: source;

T01, T02: Top.

Detailed ways

The content of the present invention will be explained by the following examples, which are not intended to limit the implementation of the present invention in any specific environment, application or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of illustrating the present invention, but not for limiting the present invention. It should be noted that, in the following embodiments and the accompanying drawings, elements not directly related to the present invention are omitted and not shown; and the dimensions between the elements in the accompanying drawings are only for easy understanding and are not intended to limit the actual scale. In addition, in the following embodiments, the same elements will be described with the same reference numerals.

Please refer to FIG. 2A to FIG. 2I below, which are schematic diagrams of a manufacturing method of the semiconductor package structure according to the first embodiment of the present invention. The manufacturing method of the semiconductor package structure includes steps S11 to S20.

As shown in FIG. 2A , step S11 forms a first patterned conductive layer 22 on a surface 211 of a carrier board 21 . The carrier plate 21 may be a metal plate or an insulating plate. The material of the first patterned conductive layer 22 is a conductive metal, such as copper, silver, nickel or alloys thereof, which can be exposed, developed and etched by using a lithography etching technique in conjunction with an additional photoresist layer (not shown in the figure). process, and perform an electroplating process to form the first patterned conductive layer 22 .

It should be noted here that, in the traditional wafer type process, the packaging process can only be performed on the chips or dies formed in a single wafer at the same time, which is relatively time-consuming. Sometimes there are many limitations in the process. Compared with the traditional wafer type packaging process, the present invention adopts a large size panel level type packaging process. Wherein, the area of the carrier board 21 is multiple times the area of a single wafer. Accordingly, the carrier board 21 of the present invention can simultaneously perform the packaging process on all the chips (or die) cut from multiple wafers, thereby effectively saving the manufacturing time.

Next, as shown in FIG. 2B , in step S12 , a conductive adhesive layer 23 is disposed on a portion of the first patterned conductive layer 22 . The conductive adhesive layer 23 can be a conductive paste, and its material can include a high heat dissipation conductive material, such as silver or copper. In other embodiments, the conductive adhesive layer 23 may also be anisotropic conductive adhesive to provide vertical (Z-axis) conduction.

Next, as shown in FIG. 2C , step S13 disposes a first power chip 24 on the conductive adhesive layer 23 . The first power chip 24 has a first front surface 241 and a first back surface 242 . The first front surface 241 has a first electrode layout, and the first back surface 242 has a second electrode layout. The first electrode layout of the first front surface 241 is in contact with the conductive adhesive layer 23 .

Next, step S14 disposes a second power chip 25 on the conductive adhesive layer 23 . The second power chip 25 has a second front side 251 and a second back side 252 . There is a third electrode layout on the second front side 251 and a fourth electrode layout on the second back side 252 . The fourth electrode layout of the second back surface 252 is in contact with the conductive adhesive layer 23 .

In this embodiment, the first power chip 24 and the second power chip 25 are respectively a transistor chip, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) chip. Therefore, the first electrode layout and the third electrode layout respectively include a gate (Gate) G1, G2 and a source (Source) S1, S2. On the other hand, the second electrode layout and the fourth electrode layout respectively include a drain (Drain) D1, D2. In other embodiments, the transistor wafer may also be a bipolar junction transistor (BJT) wafer or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor; IGBT) wafer or the like.

Based on the above, the first power chip 24 and the second power chip 25 have the same components, so the first electrode layout of the first power chip 24 is the same as the third electrode layout of the second power chip 25 , and the first power chip 24 has the same element. The two-electrode layout is the same as the fourth electrode layout of the second power chip 25 . In other words, the first power chip 24 and the second power chip 25 are disposed on the conductive adhesive layer 23 in a reversed manner.

Next, as shown in FIG. 2D , step S15 forms a second electrode layout of the first conductive connecting element 261 on the first back surface 242 of the first power chip 24 and a third electrode layout on the second front surface 251 of the second power chip 25 . The first conductive connection element 261 can be formed by using a lithography etching technique, performing exposure, developing and etching processes with an additional photoresist layer (not shown in the figure), and performing an electroplating process.

Next, as shown in FIG. 2E , step S16 forms a second conductive connection element 262 on the first patterned conductive layer 22 without the conductive adhesive layer 23 . The second conductive connecting element 262 , such as a conductive post, is made of metal and can be directly formed on the first patterned conductive layer 22 through an electroplating process. In addition to providing electrical conduction paths, it can also increase support strength. In other embodiments, the second conductive connecting element 262 can also be pre-shaped and then fixed by conductive glue and electrically connected to the first patterned conductive layer 22 (not shown in the figure).

Next, as shown in FIG. 2F, step S17 forms a molding layer 27 on the carrier board 21, and covers the first patterned conductive layer 22, the conductive adhesive layer 23, the first power chip 24, the second power chip 25, The first conductive connection element 261 and the second conductive connection element 262 . The material of the molding layer 27 can be a high filler content dielectric material, such as a molding compound, which is made of a phenolic-based resin (Novolac-Based Resin), an epoxy-based resin (Epoxy resin) -Based Resin) or Silicone-Based Resin (Silicone-Based Resin) is the main matrix, which accounts for about 8 wt.% to 12 wt.% of the overall casting compound, and the doping accounts for about 70 wt.% to 90 wt.%. wt.% filler. Wherein, the filler may include silicon dioxide and aluminum oxide, so as to increase the mechanical strength, reduce the number of linear thermal expansion, increase the heat conduction, increase the water resistance and reduce the glue overflow.

In this embodiment, step S17 further includes grinding the top of the molding layer 27 through a grinding process to expose the tops T01 and T02 of the first conductive connection element 261 and the second conductive connection element 262 .

Next, as shown in FIG. 2G , step S18 forms a second patterned conductive layer 28 on the molding layer 27 and is electrically connected to the first conductive connecting element 261 and the second conductive connecting element exposed on the molding layer 27 . 262.

Next, as shown in FIG. 2H , step S19 forms a cover layer 27 a on the molding layer 27 and wraps the second patterned conductive layer 28 to protect the molding layer 27 and the cover layer 27 a components inside. In this embodiment, a grinding process may also be selectively performed to grind the top of the protective layer 27a.

Finally, as shown in FIG. 2I , step S20 removes the carrier board 21 to form a semiconductor package structure 20 . In the present embodiment, the first power chip 24 and the second power chip 25 are arranged in an inverted manner, and the drain electrode D1 of the first power chip 24 is connected to the first power chip 24 through the first conductive connection element 261 and the second patterned conductive layer 28 It is electrically connected to the source S2 of the second power chip 25 . Accordingly, the electrical conduction distance between the drain electrode D1 and the source electrode S2 can be shortened, and the electrical effect can be increased. On the other hand, the semiconductor package structure can be applied to a half-bridge circuit.

Next, the manufacturing method of the semiconductor package structure according to the second embodiment of the present invention will be described. In this embodiment, the manufacturing method of the semiconductor package structure includes steps S31 to S40. Since some steps of the manufacturing method of the present embodiment are the same as those of the manufacturing method of the first embodiment, the description of the same steps will be omitted. In addition, in this embodiment, the same elements as those in the first embodiment are the same as those in the first embodiment.

First of all, steps S31 to S34 are the same as steps S11 to S14 of the first embodiment, so they will not be repeated here.

Next, as shown in FIG. 3A , in step S35 , a second conductive connection element 262 is formed on the first patterned conductive layer 22 without the conductive adhesive layer 23 . Similar to the above-mentioned embodiment, the second conductive connecting element 262, such as the conductive column, is made of metal and can be directly formed on the first patterned conductive layer 22 through an electroplating process. In addition to providing an electrical conduction path, it can also increase support strength. In other embodiments, the second conductive connecting element 262 can also be pre-shaped and then fixed by conductive glue and electrically connected to the first patterned conductive layer 22 (not shown in the figure).

Next, as shown in FIG. 3B , in step S36 , a molding layer 27 is formed on the carrier board 21 , and the first patterned conductive layer 22 , the conductive adhesive layer 23 , the first power chip 24 , the second power chip 25 and the first patterned conductive layer 22 are covered. Two conductive connection elements 262 . In addition, step S36 may further include grinding the top of the molding layer 27 through a grinding process to expose the top T02 of the second conductive connection element 262 .

Next, as shown in FIG. 3C , in step S37 , laser drilling technology is used in the molding layer 27 to correspond to the drain electrode D1 of the first power chip 24 and the source electrode S2 and the gate electrode G2 of the second power chip 25 respectively. Three openings 271 , 272 , and 273 are formed at the position of the first power chip 24 to expose the drain electrode D1 of the first power chip 24 and the source electrode S2 and the gate electrode G2 of the second power chip 25 .

Next, as shown in FIG. 3D , step S38 forms a first conductive connecting element 261 on the openings 271 , 272 , and 273 and forms a second patterned conductive layer 28 on the molding layer 27 , and is electrically connected to the exposed molding layer. 27 of the first conductive connection element 261 and the second conductive connection element 262. In this embodiment, the first conductive connection element 261 and the second patterned conductive layer 28 can be formed at the same time, and the photolithography etching technology can be used in conjunction with an additional photoresist layer (not shown in the figure) to perform exposure development and etching processes, and An electroplating process is performed to form the first conductive connection elements 261 and the second patterned conductive layer 28 .

Next, step 39 and step 40 are the same as step S19 and step S20 of the first embodiment, so they will not be repeated here.

The semiconductor package structure 20 of the present invention can be electrically connected to a circuit board 30 through conductive bumps 32 as shown in FIG. 4 . The circuit board 30 may be a printed circuit board, a metal core circuit board or a glass circuit board.

In addition, as shown in FIG. 5 , openings 274 and 275 can be formed on the protective layer 27 a by laser drilling technology to expose part of the second patterned conductive layer 28 , and an electronic component 33 can pass through the conductive bumps 34 to It is electrically connected to the second patterned conductive layer 28 .

To sum up, a semiconductor package structure and a manufacturing method thereof of the present invention set the first power chip and the second power chip, such as transistor chips, in an inverted manner, which has the following characteristics:

(1) The first power chip and the second power chip are set upside down to each other, so that the distance of electrical connection between the chips can be shortened, the electrical performance can be increased, and the height of the package structure can be reduced.

(2) The existing reflow process is replaced by a semiconductor process to greatly improve the precision of the packaging structure.

(3) The lead-containing reflow process is abandoned in the process, so it can meet the trend of environmental protection and the needs of laws and regulations.

(4) One side of the power wafer is fixed to the first patterned conductive layer by using a thermally conductive adhesive layer, which can simplify the process.

Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Claims (12)

1. A semiconductor package structure, comprising:

a first patterned conductive layer;

a first power chip having a first front surface and a first back surface, and disposed with the first front surface facing the first patterned conductive layer, the first front surface of the first power chip having a first electrode layout, and the first back surface having a second electrode layout;

a second power chip, disposed adjacent to the first power chip, having a second front surface and a second back surface, and disposed with the second back surface facing the first patterned conductive layer, wherein the second front surface of the second power chip has a third electrode layout, and the second back surface has a fourth electrode layout, wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip;

a conductive adhesive layer electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer, and electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer;

the second patterned conductive layer is arranged opposite to the first patterned conductive layer, and the first back surface of the first power wafer and the second front surface of the second power wafer face the second patterned conductive layer;

a first conductive connecting element electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and electrically connected between the third electrode layout of the second power chip and the second patterned conductive layer;

a second conductive connecting element electrically connected between the first patterned conductive layer and the second patterned conductive layer; and

and the molding sealing layer is used for coating the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connecting element and the second conductive connecting element.

2. The semiconductor package according to claim 1, wherein the first power chip and the second power chip are each a transistor chip.

3. The semiconductor package according to claim 2, wherein the first electrode layout and the third electrode layout respectively comprise a gate and a source, and the second electrode layout and the fourth electrode layout respectively comprise a drain.

4. The semiconductor package according to claim 3, wherein the drain of the second electrode layout is electrically connected to the source of the third electrode layout.

5. The semiconductor package according to claim 1, wherein the molding compound is a phenolic-based resin, an epoxy-based resin, or a silicon-based resin.

6. A method for manufacturing a semiconductor package structure, comprising:

providing a bearing plate;

forming a first patterned conductive layer on a surface of the carrier plate;

arranging a conductive adhesive layer on part of the first patterned conductive layer;

disposing a first power chip on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip contacts the conductive adhesive layer;

disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer, wherein the first electrode layout of the first power chip is identical to the third electrode layout of the second power chip, and the second electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip;

forming at least one conductive connecting element on the first patterned conductive layer without the conductive adhesive layer, a second electrode layout on a first back surface of the first power chip, and/or a third electrode layout on a second front surface of the second power chip;

forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the conductive connecting element;

forming a second patterned conductive layer on the molding layer and electrically connected to the conductive connecting element exposed to the molding layer; and

the carrier plate is removed.

7. The method as claimed in claim 6, wherein at least one drain of the first back side of the first power chip is electrically connected to at least one source of the second front side of the second power chip.

8. The method of manufacturing a semiconductor package according to claim 6, further comprising:

forming a protective layer on the molding layer to cover the second patterned conductive layer.

9. A method for manufacturing a semiconductor package structure, comprising:

providing a bearing plate;

forming a first patterned conductive layer on a surface of the carrier plate;

arranging a conductive adhesive layer on part of the first patterned conductive layer;

disposing a first power chip on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip contacts the conductive adhesive layer;

disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer, wherein the first electrode layout of the first power chip is identical to the third electrode layout of the second power chip, and the second electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip;

forming at least one second conductive connecting element on the first patterned conductive layer without the conductive adhesive layer;

forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the second conductive connecting element;

forming a plurality of openings on the molding layer corresponding to a second electrode layout on a first back surface of the first power chip and a third electrode layout on a second front surface of the second power chip;

forming a first conductive connecting element on the openings;

forming a second patterned conductive layer on the molding layer and electrically connected to the first conductive connecting element and the second conductive connecting element exposed to the molding layer; and

the carrier plate is removed.

10. The method as claimed in claim 9, wherein at least one drain of the first back side of the first power chip is electrically connected to at least one source of the second front side of the second power chip.

11. The method of manufacturing a semiconductor package according to claim 9, further comprising:

forming a protective layer on the molding layer to cover the second patterned conductive layer.

12. The method of claim 9, wherein the first conductive connecting element and the second patterned conductive layer are formed simultaneously in one process.

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