CN111625197A - Memory control method, memory storage device and memory controller - Google Patents
Memory control method, memory storage device and memory controller Download PDFInfo
- Publication number
- CN111625197A CN111625197A CN202010466395.XA CN202010466395A CN111625197A CN 111625197 A CN111625197 A CN 111625197A CN 202010466395 A CN202010466395 A CN 202010466395A CN 111625197 A CN111625197 A CN 111625197A
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- cache
- count value
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides a memory control method, a memory storage device and a memory controller. The memory module comprises a cache area and a data area. Each physical unit in the cache is programmed based on a first programming mode. Each physical unit in the data region is programmed based on a second programming mode. The memory control method includes: receiving a write command from a host system, indicating to store first data; storing the first data and filling data to at least one first entity unit in the cache area or the data area according to the write instruction; updating a count value associated with the padding data; and if the count value meets a preset condition, performing data sorting operation on at least one second entity unit in the cache region.
Description
Technical Field
The present invention relates to a memory control technology, and in particular, to a memory control method, a memory storage device, and a memory controller.
Background
Non-volatile memory modules, such as flash memory modules, have the advantages of non-volatile storage of data, low power consumption, and fast data access. Some types of memory storage devices may additionally provide a cache (also referred to as a cache buffer) in the non-volatile memory module. When storing data, if the cache area is not full, the data can be quickly stored into the cache area through a Single Level Cell (SLC) mode, and then the data is moved from the cache area to the data area for storage in the background. However, if the cache is full, the data is directly stored to the data block by Direct-Triple Level Cell (Direct-TLC) or similar programming scheme.
Generally, if the host system indicates to store small data (e.g., data having a data size of 4kb (bytes)), the memory storage device may need to write the small data to a predetermined storage location along with fill (dummy) data. For SLC mode, for example, a small data block of 4KB may be written to a physical page of 16KB in the cache with 12KB of fill data. However, if Direct-TLC is used to write data, 4KB of small data may be accompanied by 44KB of padding data to fill up three physical pages of 16KB each in the data area. When the data area is used for a long time, the use space of the cache area and the data area is easily used up by the filling data, and the write amplification of the memory storage device is increased rapidly.
Disclosure of Invention
Embodiments of the present invention provide a memory control method, a memory storage device and a memory controller, which can reduce the amount of padding data used and/or reduce the write amplification caused by the use of the padding data.
Embodiments of the present invention provide a memory control method for controlling a memory module. The memory module comprises a cache area and a data area. Each physical unit in the cache is programmed based on a first programming mode. Each physical unit in the data region is programmed based on a second programming mode. The memory control method includes: receiving a write command from a host system, indicating to store first data; storing the first data and filling data to at least one first entity unit in the cache area or the data area according to the write instruction; updating a count value associated with the padding data; and if the count value meets a preset condition, performing data sorting operation on at least one second entity unit in the cache region.
In an embodiment of the present invention, the step of storing the first data and the fill data into the at least one first physical unit in the cache or the data area according to the write command comprises: determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
In an embodiment of the present invention, the memory control method further includes: and if the count value reaches a preset value, judging that the count value meets the preset condition.
An embodiment of the present invention further provides a memory storage device, which includes a memory module, a connection interface, and a memory controller. The connection interface is used for connecting to a host system. The memory controller is connected to the memory module and the connection interface. The memory module comprises a cache area and a data area. Each physical unit in the cache is programmed based on a first programming mode. Each physical unit in the data region is programmed based on a second programming mode. The memory controller is configured to receive a write command from the host system, the write command indicating that first data is stored. The memory controller is further configured to store the first data and the fill data to at least one first physical unit in the cache or the data area according to the write command. The memory controller is further configured to update a count value associated with the padding data. If the count value meets a preset condition, the memory controller is further used for executing data sorting operation on at least one second entity unit in the cache region.
In an embodiment of the present invention, the operation of the memory controller to store the first data and the fill data to the at least one first physical unit in the cache area or the data area according to the write command includes: determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
In an embodiment of the invention, if the count value reaches a predetermined value, the memory controller is further configured to determine that the count value satisfies the predetermined condition.
The embodiment of the invention also provides a memory controller which is used for controlling the memory module. The memory module comprises a cache area and a data area. Each physical unit in the cache is programmed based on a first programming mode. Each physical unit in the data region is programmed based on a second programming mode. The memory controller includes a host interface, a memory interface, a counting circuit, and a memory control circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the memory module. The memory control circuit is connected to the host interface, the memory interface, and the counting circuit. The memory control circuitry is to receive a write command from the host system. The write instruction indicates that the first data is stored. The memory control circuit is further configured to store the first data and the fill data to at least one first physical unit in the cache or the data area according to the write command. The counting circuit is configured to update a count value associated with the padding data. And if the count value meets a preset condition, the memory control circuit is further used for executing data sorting operation on at least one second entity unit in the cache region.
In an embodiment of the present invention, the operation of the memory control circuit storing the first data and the fill data to the at least one first physical unit in the cache area or the data area according to the write command includes: determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
In an embodiment of the present invention, the count value reflects a total data amount of all padding data used within a preset time range.
In an embodiment of the invention, if the count value reaches a predetermined value, the memory control circuit is further configured to determine that the count value satisfies the predetermined condition.
In an embodiment of the present invention, the data sorting operation includes: copying at least a part of the valid data stored in the at least one second entity unit to at least one third entity unit in the data area; and erasing the at least one second physical unit.
In an embodiment of the invention, the first programming mode is used for storing a first number of bit data into one memory cell, the second programming mode is used for storing a second number of bit data into one memory cell, and the first number is smaller than the second number.
Based on the above, after receiving a write command from the host system indicating to store first data, the first data and the fill data may be stored in at least one first physical unit of the cache or the data area, and the count value associated with the fill data may be updated. After the count value meets a preset condition, the data sorting operation can be performed on at least one second entity unit in the cache area in advance. Thereby, the amount of padding data used in subsequent write operations can be reduced and/or the write amplification due to the use of padding data can be reduced.
Drawings
FIG. 1 is a schematic diagram of a memory storage device shown in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating storing first data and padding data to a first entity unit according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating a memory control method according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the present invention. Referring to fig. 1, a memory storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 may be any type of computer system. For example. The host system 11 may be a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, etc. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid state disk, a U-disk, or other type of non-volatile storage device. The host system 11 may be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Thus, the host system 11 may store data to the memory storage device 12 and/or read data from the memory storage device 12.
The memory module 122 is used for storing data. The memory module 122 may include a rewritable non-volatile memory module. The memory module 122 includes an array of memory cells. The memory cells in the memory module 122 store data in the form of voltages. For example, the memory modules 122 may include Single Level Cell (SLC) NAND type flash memory modules, Multi-Level Cell (MLC) NAND type flash memory modules, Triple Level Cell (TLC) NAND type flash memory modules, Quad Level Cell (QLC) NAND type flash memory modules, or other memory modules with similar characteristics.
The memory controller 123 is connected to the connection interface 121 and the memory module 122. Memory controller 123 may be used to control memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 for data access and data management. For example, the memory controller 123 may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other Programmable general purpose or special purpose microprocessor, a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar devices or combinations thereof.
In one embodiment, memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 may receive a sequence of instructions from the memory controller 123 and access data stored in the memory cells according to this sequence of instructions.
FIG. 2 is a schematic diagram of a memory controller according to an embodiment of the invention. Referring to fig. 1 and 2, the memory controller 123 includes a host interface 21, a memory interface 22, a counting circuit 23, and a memory control circuit 24. The host interface 21 is used to connect to the host system 11 via the connection interface 121 for communication with the host system 11. The memory interface 22 is used to connect to the memory module 122 for communication with the memory module 122. The counting circuit 23 is used for performing a counting operation. For example, the counting circuit 23 may include at least one counter. In one embodiment, the counting circuit 23 may also be disposed in the memory control circuit 24.
The memory control circuit 24 is connected to the host interface 21, the memory interface 22, and the counting circuit 23. Memory control circuitry 24 may be used to control host interface 21, memory interface 22, and counting circuitry 23. For example, the memory control circuitry 24 may communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. The memory control circuit 24 may also be considered a control core of the memory controller 123. In the following embodiments, the description of the memory control circuit 24 is equivalent to that of the memory controller 123. In addition, the memory control circuit 24 may include one or more buffer memories for temporarily storing data.
FIG. 3 is a schematic diagram illustrating a management memory module according to an embodiment of the invention. Referring to fig. 1 and 3, the memory module 122 includes a plurality of physical units 301(1) -301 (C). Each physical unit comprises a plurality of storage units and is used for storing data in a nonvolatile mode. For example, a physical unit may refer to a physical page or other unit of memory management. Multiple memory cells in a physical cell can be programmed simultaneously to store data. A plurality of physical units can constitute a physical block. Multiple physical cells (or memory cells) in a physical block can be erased simultaneously. In addition, the memory control circuit 24 may be configured with a plurality of logic units for mapping physical units in the cache 310 and the data 320. For example, a logical unit may consist of one or more logical addresses. The mapping relationship between the logic unit and the entity unit can be recorded in the logic-to-entity mapping table.
In one embodiment, the memory module 122 includes a cache area 310, a data area (also referred to as a static data area) 320, and an idle area 330. The physical units 301(1) to 301(A) in the cache 310 and the physical units 301(A +1) to 301(B) in the data area 320 store data (also referred to as user data) from the host system 11. Physical units in the cache area 310 and the data area 320 are erased and then associated with the idle area 330. In other words, the physical units 301(B +1) -301 (C) in the idle region 330 are all erased and no valid data is stored.
In one embodiment, when new data from the host system 11 needs to be stored, one or more physical units in the idle region 330 are selected and used to store the data. Depending on the programming mode employed, the physical unit storing the data may instead be associated with the cache 310 or the data area 320. In addition, data stored in the cache 310 may be copied to the data block 320 for storage at a later point in time in the background operation of the memory storage device 12.
In one embodiment, the maximum size of physical units 301(A), (1) and (301A) in cache 310 is less than the maximum size of physical units 301(A +1) and (301B) in data block 320. In one embodiment, the maximum size of physical units 301(1) to 301(A) in cache 310 is about 1% to 5% of the maximum size of physical units 301(A +1) to 301(B) in data block 320, but the invention is not limited thereto.
In one embodiment, the physical units 301(1) to 301(A) in the cache 310 are programmed to store data based on a certain programming mode (also referred to as a first programming mode), and the physical units 301(A +1) to 301(B) in the data area 320 are programmed to store data based on another programming mode (also referred to as a second programming mode). The first programming mode is different from the second programming mode. For example, a first programming mode can be used to store a predetermined number (also referred to as a first number) of bits of data into a memory cell, and a second programming mode can be used to store another predetermined number (also referred to as a second number) of bits of data into a memory cell, where the first number is smaller than the second number. For example, the first number may be 1, and the second number may be 2, 3, or 4.
In one embodiment, the first programming mode may include an SLC mode (or a virtual SLC mode), and the second programming mode may include an MLC mode, a TLC mode, or a QLC mode. One cell programmed based on SLC mode can store 1 bit, and one cell programmed based on MLC mode, TLC mode or QLC mode can store 2, 3 or 4 bits, respectively.
In one embodiment, the reliability and/or programming speed of the first programming mode is higher than the reliability and/or programming speed of the second programming mode. In the following embodiments, the first programming mode is an SLC mode as an example, and the second programming mode is a TLC mode as an example, but the invention is not limited thereto.
In one embodiment, memory control circuitry 24 may receive write instructions from host system 11. The write command indicates that a certain data (also referred to as a first data) is stored. The memory control circuit 24 may store the first data and the filling data to at least one physical unit (also referred to as a first physical unit) in the cache area 310 or the data area 320 according to the write command. For example, the memory control circuit 24 may determine the data amount of the padding data to be used according to the data amount of the first data and the available capacity of the first physical unit for storing the first data.
Fig. 4 is a schematic diagram illustrating storing first data and padding data in a first entity unit according to an embodiment of the invention. Referring to FIG. 4, in one embodiment, when the first data (i.e., valid data) 401 is to be stored, if the cache 310 is not full (i.e., the total data size of the data currently stored in the cache 310 does not reach a predetermined data size), the memory control circuit 24 may preferentially store the first data in the cache 310. Thus, in this example, the first physical unit may be assumed to be physical unit 301 (1). The memory control circuit 24 may obtain the data amount (e.g. 12 KB-16 KB) of the padding data 402 according to the data amount (say 4KB) of the first data 401 and the available capacity (say 16KB) of the entity unit 301 (1). Memory control circuitry 24 may write the first 4KB data 401 and the 12KB fill data 402 to physical unit 301(1) simultaneously and associate physical unit 301(1) with cache 310. In one embodiment, the programming operation (i.e., the first programming operation) for physical cell 301(1) in FIG. 4 is also referred to as an SLC (or virtual SLC) programming operation.
On the other hand, in one embodiment, when the first data 411 is to be stored, if the cache 310 is full (i.e. the total data amount of the data currently stored in the cache 310 has reached the predetermined data amount), the memory control circuit 24 may skip the cache 310 and directly store the first data 411 in the data area 420. Thus, in this example, the first physical unit may be assumed to be 3 physical units 301(a +1) to 301(a + 3). The memory control circuit 24 may obtain the data amount of the padding data 412 (e.g., 44KB ═ 48KB-4KB) according to the data amount of the first data 411 (assume 4KB) and the available capacity of the entity units 301(a +1) to 301(a +3) (assume 48KB ═ 3 × 16 KB). The memory control circuit 24 may simultaneously write the 4KB first data 411 and the 44KB padding data 412 into the physical units 301(a +1) to 301(a +3) and associate the physical units 301(a +1) to 301(a +3) to the data area 420. In one embodiment, the programming operation (i.e., the second programming operation) for the physical cells 301(a +1) -301 (a +3) in fig. 4 is also referred to as Direct-TLC programming operation.
As can be seen from the embodiment of FIG. 4, when the first data 401 and 411 of the same data size are written into the cache area 310 and the data area 320, respectively, the data size of the fill data 402 and 412 required to be used differs by 32KB (44KB-12KB ═ 32 KB). Since the filler data may be data that has no meaning (i.e., invalid data), using more filler data will result in more memory space being wasted. Therefore, if the cache 310 can be maintained as empty as possible, then there is a higher probability that subsequent data from the host system 11 will be written into the cache 310, thereby reducing the amount of fill data that may be subsequently used.
In one embodiment, memory control circuitry 24 may update a count value associated with used padding data via count circuitry 23. This count value may reflect the total data amount of all padding data used over a preset time period in the past. For example, the count value may be positively correlated to the total data amount of all padding data used within a preset time frame in the past. For example, the predetermined time range may be 5 seconds to 10 seconds, etc., and is not limited thereto. If the count value satisfies a predetermined condition, the memory control circuit 24 may perform a data sorting operation on at least one physical unit (also referred to as a second physical unit) in the cache 310. The data flushing operation is used to free up new memory in the cache 310. If the count value does not satisfy the predetermined condition, the memory control circuit 24 may temporarily not perform the data sorting operation on the second physical unit in the cache 310.
In one embodiment, the memory control circuit 24 can determine whether the count value reaches a predetermined value. If the count value reaches the predetermined value, it indicates that relatively more padding data have been used within a predetermined time period. Therefore, the memory control circuit 24 may determine that the count value satisfies the predetermined condition and perform a data sorting operation on the second physical unit in the cache 310. Otherwise, if the count value does not reach the predetermined value, the memory control circuit 24 may determine that the count value does not satisfy the predetermined condition.
In one embodiment, during the data grooming operation, the memory control circuit 24 may select at least one physical unit having valid data stored therein from the physical units 301(1) -301 (A) currently associated with the cache 310 as the second physical unit. Memory control circuitry 24 may copy at least a portion of the valid data stored by the second physical unit to at least one physical unit (also referred to as a third physical unit) in data region 320. For example, during the process of copying data, valid data collected from the fast fetching region 310 may be stored into the data region 320 based on the second programming mode. After the data copy is completed, the second physical unit may be erased, thereby freeing up new storage space in the cache 310. When the next data (also referred to as the second data) from the host system 11 needs to be stored, the second data can be stored in the cache 310 with less fill data even if the fill data needs to be used, so as to reduce the amount of fill data to be used subsequently and/or reduce the write amplification due to the use of the fill data.
FIG. 5 is a flow chart illustrating a memory control method according to an embodiment of the present invention. Referring to fig. 5, in step S501, a write command is received from a host system. The write instruction indicates that the first data is stored. In step S502, the first data and the filling data are stored in at least one first entity unit of the cache or the data area according to the write command. In step S503, the count value related to the padding data is updated. In step S504, it is determined whether the count value meets a preset condition. If the count value satisfies the predetermined condition, in step S505, a data sorting operation is performed on at least one second entity unit in the cache. In addition, if the count value does not satisfy the preset condition, the process may return to step S501 or perform other preset operations.
However, the steps in fig. 5 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 5 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 5 can be used with the above exemplary embodiments, or can be used alone, and the invention is not limited thereto.
In summary, after receiving a write command from the host system indicating to store first data, the first data and the fill data can be stored in at least one first physical unit of the cache or the data area, and the count value associated with the fill data can be updated. After the count value meets the preset condition, the data sorting operation can be performed on at least one second entity unit in the cache area in advance, so that the probability of preferentially storing the data from the host system to the cache area in the follow-up process is increased. Thereby, the data amount of the padding data used in the subsequent write operation can be reduced and/or the write amplification due to the use of the padding data can be reduced.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (18)
1. A memory control method for controlling a memory module, the memory module including a cache area and a data area, each physical unit in the cache area being programmed based on a first programming mode, each physical unit in the data area being programmed based on a second programming mode, the memory control method comprising:
receiving a write command from a host system, wherein the write command indicates to store first data;
storing the first data and filling data to at least one first entity unit in the cache area or the data area according to the write instruction;
updating a count value associated with the padding data; and
and if the count value meets a preset condition, performing data sorting operation on at least one second entity unit in the cache region.
2. The memory control method of claim 1, wherein storing the first data and the fill data to the at least one first physical unit in the cache or the data area according to the write command comprises:
determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
3. The memory control method according to claim 1, wherein the count value reflects a total data amount of all padding data used within a preset time range.
4. The memory control method of claim 1, further comprising:
and if the count value reaches a preset value, judging that the count value meets the preset condition.
5. The memory control method of claim 1, wherein the data grooming operation comprises:
copying at least a part of the valid data stored in the at least one second entity unit to at least one third entity unit in the data area; and
and erasing the at least one second physical unit.
6. The memory control method of claim 1, wherein the first programming mode is used to store a first number of bits of data to a memory cell, the second programming mode is used to store a second number of bits of data to a memory cell, and the first number is smaller than the second number.
7. A memory storage device, comprising:
a memory module;
a connection interface for connecting to a host system; and
a memory controller connected to the memory module and the connection interface,
wherein the memory module comprises a cache area and a data area, each physical unit in the cache area is programmed based on a first programming mode, each physical unit in the data area is programmed based on a second programming mode,
the memory controller to receive a write command from the host system, the write command indicating to store first data,
the memory controller is further configured to store the first data and fill data to at least one first physical unit of the cache or the data area according to the write command,
the memory controller is further configured to update a count value associated with the padding data, and
if the count value meets a preset condition, the memory controller is further configured to perform a data sorting operation on at least one second physical unit in the cache.
8. The memory storage device of claim 7, wherein the operation of the memory controller to store the first data and the fill data to the at least one first physical unit in the cache or the data area according to the write instruction comprises:
determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
9. The memory storage device of claim 7, wherein the count value reflects a total data amount of all padding data used within a preset time range.
10. The memory storage device of claim 7, wherein the memory controller is further configured to determine that the count value satisfies the predetermined condition if the count value reaches a predetermined value.
11. The memory storage device of claim 7, wherein the data grooming operation comprises:
copying at least a part of the valid data stored in the at least one second entity unit to at least one third entity unit in the data area; and
and erasing the at least one second physical unit.
12. The memory storage device of claim 7, wherein the first programming mode is configured to store a first number of bits of data to a memory cell, the second programming mode is configured to store a second number of bits of data to a memory cell, and the first number is less than the second number.
13. A memory controller for controlling a memory module, the memory module including a cache area and a data area, each physical unit in the cache area being programmed based on a first programming mode, each physical unit in the data area being programmed based on a second programming mode, the memory controller comprising:
a host interface for connecting to a host system;
a memory interface to connect to the memory module;
a counting circuit; and
a memory control circuit connected to the host interface, the memory interface, and the counting circuit,
wherein the memory control circuitry is to receive a write instruction from the host system, the write instruction indicating to store first data,
the memory control circuit is further configured to store the first data and fill data to at least one first physical unit of the cache or the data area according to the write command,
the counting circuit is used for updating the counting value related to the filling data, and
if the count value meets a preset condition, the memory control circuit is further configured to perform a data sorting operation on at least one second physical unit in the cache.
14. The memory controller of claim 13, wherein the operation of the memory control circuitry to store the first data and the fill data to the at least one first physical unit in the cache or the data area according to the write instruction comprises:
determining the data amount of the padding data according to the data amount of the first data and the available capacity of the at least one first entity unit.
15. The memory controller according to claim 13, wherein the count value reflects a total data amount of all padding data used within a preset time range.
16. The memory controller of claim 13, wherein the memory control circuit is further configured to determine that the count value satisfies the predetermined condition if the count value reaches a predetermined value.
17. The memory controller of claim 13, wherein the data grooming operation comprises:
copying at least a part of the valid data stored in the at least one second entity unit to at least one third entity unit in the data area; and
and erasing the at least one second physical unit.
18. The memory controller of claim 13, wherein the first programming mode is configured to store a first number of bits of data to a memory cell, the second programming mode is configured to store a second number of bits of data to a memory cell, and the first number is less than the second number.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010466395.XA CN111625197A (en) | 2020-05-28 | 2020-05-28 | Memory control method, memory storage device and memory controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010466395.XA CN111625197A (en) | 2020-05-28 | 2020-05-28 | Memory control method, memory storage device and memory controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111625197A true CN111625197A (en) | 2020-09-04 |
Family
ID=72271980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010466395.XA Pending CN111625197A (en) | 2020-05-28 | 2020-05-28 | Memory control method, memory storage device and memory controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111625197A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230849A (en) * | 2020-10-13 | 2021-01-15 | 深圳宏芯宇电子股份有限公司 | Memory control method, memory storage device and memory controller |
| CN112527204A (en) * | 2020-12-15 | 2021-03-19 | 深圳星火半导体科技有限公司 | Storage method and device |
| CN117555492A (en) * | 2024-01-12 | 2024-02-13 | 合肥开梦科技有限责任公司 | Memory controller, memory management method and memory device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106445397A (en) * | 2015-07-28 | 2017-02-22 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
| CN107544922A (en) * | 2016-06-24 | 2018-01-05 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| CN107818808A (en) * | 2016-09-14 | 2018-03-20 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| CN109273033A (en) * | 2017-07-17 | 2019-01-25 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
-
2020
- 2020-05-28 CN CN202010466395.XA patent/CN111625197A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106445397A (en) * | 2015-07-28 | 2017-02-22 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
| CN107544922A (en) * | 2016-06-24 | 2018-01-05 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| CN107818808A (en) * | 2016-09-14 | 2018-03-20 | 群联电子股份有限公司 | Data writing method, memory control circuit unit and memory storage device |
| CN109273033A (en) * | 2017-07-17 | 2019-01-25 | 群联电子股份有限公司 | Memory management method, memory control circuit unit and memory storage device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112230849A (en) * | 2020-10-13 | 2021-01-15 | 深圳宏芯宇电子股份有限公司 | Memory control method, memory storage device and memory controller |
| CN112230849B (en) * | 2020-10-13 | 2023-12-05 | 深圳宏芯宇电子股份有限公司 | Memory control method, memory storage device and memory controller |
| CN112527204A (en) * | 2020-12-15 | 2021-03-19 | 深圳星火半导体科技有限公司 | Storage method and device |
| CN117555492A (en) * | 2024-01-12 | 2024-02-13 | 合肥开梦科技有限责任公司 | Memory controller, memory management method and memory device |
| CN117555492B (en) * | 2024-01-12 | 2024-03-29 | 合肥开梦科技有限责任公司 | Memory controller, memory management method and memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8812784B2 (en) | Command executing method, memory controller and memory storage apparatus | |
| US10120615B2 (en) | Memory management method and storage controller using the same | |
| US9268687B2 (en) | Data writing method, memory control circuit unit and memory storage apparatus | |
| US10579518B2 (en) | Memory management method and storage controller | |
| CN110083546B (en) | Method for writing management in memory device, memory device and controller thereof | |
| US20180024738A1 (en) | Data reading method, data writing method and storage controller using the same | |
| US8489942B1 (en) | Memory management method, and memory controller and memory storage device using the same | |
| US10324651B2 (en) | Data transmission method, and storage controller and list management circuit using the same | |
| CN107665091B (en) | Data reading method, data writing method and storage controller thereof | |
| CN111625197A (en) | Memory control method, memory storage device and memory controller | |
| US9383929B2 (en) | Data storing method and memory controller and memory storage device using the same | |
| CN118092807A (en) | Cache space allocation method and memory storage device | |
| CN113885808A (en) | Mapping information recording method, memory control circuit unit and memory device | |
| CN107943710B (en) | Memory management method and memory controller using the same | |
| CN110471612B (en) | Memory management method and memory controller | |
| CN103914391B (en) | Data reading method, memory controller and memory storage device | |
| CN112230849B (en) | Memory control method, memory storage device and memory controller | |
| US12147674B1 (en) | Memory control method, memory storage device and memory control circuit unit | |
| CN114416147A (en) | Firmware loading method, memory and computer readable storage medium | |
| CN112988069B (en) | Memory management method, memory storage device and memory controller | |
| CN113094306B (en) | Effective data management method, memory storage device and memory controller | |
| CN114625322A (en) | Firmware partition management method and memory storage system | |
| CN110162493B (en) | Memory management method and memory controller using same | |
| CN115079928B (en) | Jumping data clearing method and data storage system | |
| CN118349186B (en) | Mapping table updating method and storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |