CN111624460B - Method for detecting defect distribution area of monocrystalline silicon - Google Patents
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Abstract
The invention provides a detection method of a monocrystalline silicon defect distribution area, which comprises the following steps: evenly dividing a sample silicon wafer into two parts; carrying out primary heat treatment on the first part of the sample silicon wafer, and carrying out secondary heat treatment on the second part of the sample silicon wafer; splicing the first sample silicon wafer subjected to the primary heat treatment and the second sample silicon wafer subjected to the secondary heat treatment to obtain a third sample silicon wafer, and carrying out minority carrier lifetime test on the third sample silicon wafer; and determining a defect distribution region of the third sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer. According to the detection method provided by the embodiment of the invention, the time for processing the sample silicon wafer can be reduced, the detection process is saved, the operation process of detection is simplified, and the accuracy of the detection result is high.
Description
Technical Field
The invention relates to the technical field of silicon wafer defect detection, in particular to a method for detecting a monocrystalline silicon defect distribution area.
Background
As a method for producing a silicon wafer, a Floating Zone (FZ) method or a Czochralski (CZ) method is widely used, and the CZ method is most common. In the CZ method, polysilicon is added into a quartz crucible, then a graphite heating element is used for heating until the polysilicon is melted, then seed crystals are soaked in silicon melt, a monocrystalline silicon crystal rod grows in a mode of pulling upwards while rotating, then a silicon wafer is sliced (Slicing), etched (Etching) and polished (Polishing), and finally the silicon wafer is made into a wafer shape.
Single Crystal silicon or silicon wafer produced by CZ method has Crystal defects such as Crystal Originated defects COP (Crystal Originated defects), flow Pattern defects FPD (Flow Pattern Defect), oxygen induced Stacking Fault OISF (Oxygen induced Stacking Fault), bulk Micro Defect density BMD (Bulk Micro Defect), and Large number of Dislocation pits LDP (Large Dislocation Pit). Because of the many defects mentioned above, there are subsequent requirements for density and size control of the defects that accompany the growth process. It was confirmed that the above-mentioned crystal defects have an influence on the yield and quality of the device. Therefore, a technique for evaluating crystal defects simply and quickly while completely eliminating them is important.
Depending on the growth conditions of the crystal, the single crystal silicon rod or wafer comprises a v-rich region in which vacancy type point defects predominate and which has supersaturated agglomerated defects of vacancy type point defects; a Pv region in which vacancy type point defects are dominant but no agglomerated defects exist; vacancy (Vacancy)/Interstitial (boundary)/boundary (boundary of V/I), I-rich region having supersaturated Interstitial silicon aggregation, and the like, are dominant in Interstitial defect amount.
How these regions change is determined according to the positions where these defect regions are generated and the crystal length of the single crystal silicon wafer, which is an important content for evaluating the level of the crystalline characteristics, however, the current defect region detection process is cumbersome and takes a long time.
Disclosure of Invention
In view of this, the present invention provides a method for detecting a defect distribution area of monocrystalline silicon, which can solve the problems of the prior art that the detection process of the defect distribution area of monocrystalline silicon is complicated and the time consumption is long.
In order to solve the technical problems, the invention adopts the following technical scheme:
the embodiment of the invention provides a method for detecting a defect distribution area of monocrystalline silicon, which comprises the following steps:
evenly dividing a sample silicon wafer into two parts;
carrying out primary heat treatment on the first part of sample silicon wafer, and carrying out secondary heat treatment on the second part of sample silicon wafer;
splicing the first part of the silicon wafer subjected to the primary heat treatment and the second part of the silicon wafer subjected to the secondary heat treatment to obtain a third sample silicon wafer, and carrying out a minority carrier lifetime test on the third sample silicon wafer;
and determining a defect distribution region of the third sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer.
Optionally, the performing a heat treatment on the first sample silicon wafer includes:
the first sample silicon wafer is heat treated for 0.1 to 3.5 hours at the temperature of between 800 and 100 ℃.
Optionally, the performing the second heat treatment on the second sample silicon wafer includes:
and sequentially carrying out heat treatment on the second sample silicon wafer for 0.1-3.5 hours at 800-950 ℃ and for 0.1-3.5 hours at 1000-1150 ℃.
Optionally, before the sample silicon wafer is equally divided into two parts, the method further includes:
and cleaning the sample silicon wafer by adopting hydrofluoric acid and drying.
Optionally, the concentration of the hydrofluoric acid is 4% -20%, and the cleaning time is 1-15 minutes.
Optionally, the sample silicon wafer is any one of a silicon wafer obtained by slicing a crystal bar, a silicon wafer after roll grinding and a silicon wafer after grinding.
Optionally, the primary heat treatment and the secondary heat treatment are performed in at least one gas of helium, nitrogen, argon, and oxygen.
Optionally, the temperature rising and/or falling speed of the primary heat treatment and the secondary heat treatment is controlled to be less than 200 ℃/min.
Optionally, the determining a defect distribution region of the sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer includes:
and comparing the minority carrier lifetime value of the first sample silicon wafer with the minority carrier lifetime value of the second sample silicon wafer in the test result of the third sample silicon wafer to determine the distribution regions of different defects of the sample silicon wafer.
The technical scheme of the invention has the following beneficial effects: according to the detection method provided by the embodiment of the invention, the time for processing the sample silicon wafer can be reduced, the detection process is saved, the operation process of detection is simplified, and the accuracy of the detection result is high.
Drawings
FIG. 1 is a schematic flow chart of a method for detecting a defect distribution area of monocrystalline silicon according to an embodiment of the invention;
FIG. 2 is a diagram illustrating test results of V-rich, P-band, and Pv regions according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the test results of Pv, pi, I-rich areas provided by the embodiment of the invention;
fig. 4 is a schematic diagram of a test result of a defect region obtained by a metal contamination method.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the description of the embodiments of the invention given above, are within the scope of protection of the invention.
In order to determine the distribution area of different defects generated in the growth process of the monocrystalline silicon, the method comprises the following steps: first, a polished silicon wafer is cleaned and then evaluated after counting by a particle counter (particle counter); second, etching (Secco etching) is performed using an etching solution, and then a Flow Pattern Defect FPD (Flow Pattern Defect) is evaluated; thirdly, after oxygen precipitates are formed through high-temperature or long-time heat treatment, evaluating by utilizing the difference of oxygen precipitation in different defect areas; fourthly, the silicon wafer is subjected to diffusion heat treatment by adopting low-concentration metal, and finally the service life of the combination is prolonged.
However, in the first method, the polished and cleaned silicon wafer must be kept clean, and the polished silicon wafer can be obtained through a plurality of subsequent processing steps after the single crystal is grown, so that the whole detection time is prolonged; moreover, an expensive device called a Particle Counter (Particle Counter) is required for evaluation, and the detection cost is high. In the second method, in the etching with the etching liquid, the etching effect is applied to all crystal faces at an appropriate etching rate, and thus it is difficult to find an etchant for evaluating crystal defects which does not contain a harmful substance to the environment. The third method has the defects of long detection time, high cost for high-temperature heat treatment and other expensive equipment; further, there is a disadvantage that it is difficult to clearly distinguish different defect regions only by the difference in the amount of oxygen precipitation in a single wafer surface. In the fourth method, a silicon wafer is contaminated by, for example, a copper solution on one side of the silicon wafer and is subjected to a long-time heat treatment to form a recombination center inside the silicon wafer, and then the recombination lifetime is measured, or a haze region appearing on the surface is cleared, so that a defect distribution region is analyzed.
To solve the above problem, referring to fig. 1, an embodiment of the invention provides a method for detecting a defect distribution area of a single crystal silicon, where the method includes the following steps:
step 11: the sample silicon wafer was divided equally into two portions.
In the step, the sample silicon wafer is evenly split into two equal parts to obtain a first sample silicon wafer and a second sample silicon wafer.
In the embodiment of the invention, the sample silicon wafer can be a silicon wafer obtained by slicing a grown silicon single crystal rod, can also be a silicon wafer obtained by barrel grinding, and can also be a ground silicon wafer, wherein the silicon wafer obtained by slicing the silicon single crystal rod can be obtained by cutting the silicon single crystal rod along the axis of the silicon single crystal rod through the center of the silicon single crystal rod, or can be obtained by cutting the silicon single crystal rod through the center of the silicon single crystal rod along the radial direction of the silicon single crystal rod; because the requirement on the sample silicon wafer is reduced, a large amount of time required for preparing the sample silicon wafer can be saved, and the detection efficiency is improved.
In the embodiment of the present invention, before the sample silicon wafer is divided into two equal parts, the method further includes:
and cleaning the sample silicon wafer by adopting hydrofluoric acid and drying.
That is, the two surfaces of the sample silicon wafer are firstly cleaned by hydrofluoric acid, so that the influence of impurities possibly existing on the surface of the sample silicon wafer on the detection accuracy is avoided; after the cleaning is completed, drying may be performed using a rotary blower or blowing with nitrogen.
In some embodiments of the invention, the concentration of hydrofluoric acid used for cleaning is 4% -20%, and the cleaning time is 1-15 minutes, so as to ensure the cleaning effect.
Step 12: and carrying out primary heat treatment on the first sample silicon wafer, and carrying out secondary heat treatment on the second sample silicon wafer.
In the step, different heat treatment processes are performed on two sample silicon wafers, wherein the first sample silicon wafer is subjected to primary heat treatment, and the second sample silicon wafer is subjected to secondary heat treatment.
Specifically, the heat treatment of the first sample silicon wafer comprises the following steps: carrying out heat treatment on the first sample silicon wafer for 0.1-3.5 hours at the temperature of 800-1000 ℃; in one embodiment, the heat treatment time may be preferably 0.1 to 2 hours. Performing secondary heat treatment on the second sample silicon wafer comprises: the second sample silicon wafer is firstly heat-treated for 0.1 to 3.5 hours at the temperature of between 800 and 950 ℃, and then heat-treated for 0.1 to 3.5 hours at the temperature of between 1000 and 1150 ℃; in one embodiment, the time for the two heat treatments may be preferably 0.1 to 2 hours. Compared with the heat treatment time of at least more than five hours, even more than ten hours in the prior art, the embodiment of the invention can save the time for processing the sample silicon wafer by reducing the heat treatment time, thereby saving the processing cost and improving the detection efficiency.
In some embodiments of the present invention, the primary heat treatment and the secondary heat treatment may be performed in at least one gas atmosphere of helium, nitrogen, argon, oxygen; during the primary heat treatment and the secondary heat treatment, the speed of temperature rise and/or temperature drop can be controlled to be less than 200 ℃/min, so as to obtain better heat treatment effect.
Step 13: and splicing the first part of the silicon wafer subjected to the primary heat treatment and the second part of the silicon wafer subjected to the secondary heat treatment to obtain a third sample silicon wafer, and carrying out minority carrier lifetime test on the third sample silicon wafer.
After the two sample silicon wafers are subjected to heat treatment, the two sample silicon wafers can be recombined into a complete sample to obtain a third sample silicon wafer; and then carrying out minority carrier lifetime test on the third sample silicon wafer to obtain the minority carrier lifetime values of different regions of the third sample silicon wafer. In the embodiment of the invention, the minority carrier lifetime test is only carried out after the heat treatment, expensive detection equipment is not needed, and the problem of detection equipment pollution possibly caused by metal pollution is avoided.
Step 14: and determining a defect distribution region of the sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer.
Referring to fig. 2 and 3, in this step, the defect distribution area of the sample silicon wafer may be determined according to the result of the minority carrier lifetime test performed on the third sample silicon wafer. Specifically, the minority carrier lifetime value of the first sample silicon wafer and the minority carrier lifetime value of the second sample silicon wafer in the test result of the third sample silicon wafer obtained by the test can be compared, so that distribution regions of different defects of the sample silicon wafers are identified and determined; that is to say, originally, the first sample silicon wafer and the second sample silicon wafer are symmetrical and average two halves, and if the measured minority carrier lifetime values are almost the same under the same heat treatment conditions, in the embodiment of the present invention, because the first sample silicon wafer and the second sample silicon wafer adopt different heat treatment processes, the oxygen precipitation amount of each crystallization characteristic region (i.e., defect region) is also different, so that a certain difference is generated between the measured minority carrier lifetime values of the first sample silicon wafer and the second sample silicon wafer, and the distribution regions of various defects, specifically including V-rich, P-band, pv, pi, and I-rich regions, can be determined according to the difference.
Referring to fig. 4, fig. 4 shows that after a silicon wafer is subjected to metal contamination by using a conventional metal contamination method, metal mist is generated by heat treatment, and then the metal mist is obtained by combining a minority carrier lifetime test, and as compared with fig. 2 and fig. 3 obtained by using the detection method of the embodiment of the present invention, it can be seen that the detection result of the embodiment of the present invention is clearer and more accurate, and the defect regions are distinguished more clearly.
In the embodiment of the invention, the first part of sample silicon wafer after primary heat treatment and the second part of sample silicon wafer after secondary heat treatment are spliced and then subjected to minority carrier lifetime test, so that the minority carrier lifetime test results of the two parts of sample silicon wafers can be directly obtained, the minority carrier lifetime values of the two parts of sample silicon wafers can be conveniently and directly compared visually, and the distribution regions of various defects can be quickly determined. Of course, in an alternative embodiment, the first sample silicon wafer after the first heat treatment and the second sample silicon wafer after the second heat treatment may not be spliced, that is, the minority carrier lifetime test is performed on the first sample silicon wafer after the first heat treatment and the second sample silicon wafer after the second heat treatment, and then the test results of the two sample silicon wafers are compared, so as to determine the distribution regions of various types of defects.
According to the detection method provided by the embodiment of the invention, metal pollution is not needed, a long-time heat treatment process is not needed, the requirement on the sample silicon wafer is low, the sample silicon wafer is divided into two parts for different heat treatments, the two parts of the sample silicon wafer are spliced and then minority carrier lifetime scanning is simultaneously carried out, and the measured values of the two parts of the sample silicon wafer are compared, so that the distribution areas of different defects can be rapidly determined, the detection process is greatly simplified, the detection efficiency is improved, and the detection cost is reduced.
While the foregoing is directed to embodiments of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made without departing from the principles of the invention, and it is intended that all such changes and modifications be considered as within the scope of the invention.
Claims (9)
1. A method for detecting a defect distribution area of a single crystal silicon comprises the following steps:
evenly dividing a sample silicon wafer into two parts;
carrying out primary heat treatment on the first part of sample silicon wafer, and carrying out secondary heat treatment on the second part of sample silicon wafer;
splicing the first part of the silicon wafer subjected to the primary heat treatment and the second part of the silicon wafer subjected to the secondary heat treatment to obtain a third sample silicon wafer, and carrying out a minority carrier lifetime test on the third sample silicon wafer;
and determining a defect distribution region of the sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer.
2. The detection method according to claim 1, wherein the performing of the heat treatment on the first sample silicon wafer comprises:
and carrying out heat treatment on the first sample silicon wafer at 800-100 ℃ for 0.1-3.5 hours.
3. The detection method according to claim 1, wherein the second heat treatment of the second sample silicon wafer comprises:
and sequentially carrying out heat treatment on the second sample silicon wafer for 0.1-3.5 hours at 800-950 ℃ and for 0.1-3.5 hours at 1000-1150 ℃.
4. The method of claim 1, wherein before the step of equally dividing the sample wafer into two parts, the method further comprises:
and cleaning the sample silicon wafer by adopting hydrofluoric acid and drying.
5. The detection method according to claim 4, wherein the concentration of the hydrofluoric acid is 4 to 20% and the cleaning time is 1 to 15 minutes.
6. The detection method according to claim 1, wherein the sample silicon wafer is any one of a silicon wafer obtained by slicing a boule, a silicon wafer after barrel polishing, and a silicon wafer after polishing.
7. The method for detecting according to claim 1, wherein the primary heat treatment and the secondary heat treatment are performed in at least one gas of helium, nitrogen, argon, and oxygen.
8. The method according to claim 1, wherein the rate of temperature rise and/or fall of the primary heat treatment and the secondary heat treatment is controlled to be less than 200 ℃/min.
9. The method for testing according to claim 1, wherein the determining the defect distribution area of the sample silicon wafer according to the minority carrier lifetime test result of the third sample silicon wafer comprises:
and comparing the minority carrier lifetime value of the first sample silicon wafer with the minority carrier lifetime value of the second sample silicon wafer in the test result of the third sample silicon wafer to determine the distribution regions of different defects of the sample silicon wafer.
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| CN114000198B (en) * | 2021-11-15 | 2023-03-10 | 苏州优晶光电科技有限公司 | Multi-crucible silicon carbide crystal synchronous growth method and equipment |
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