CN111613856B - Double-passband balance filter adopting double-layer circular patch - Google Patents
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Abstract
本发明公开了一种采用双层圆形贴片的双通带平衡滤波器，包括上下两层介质基板，所述上下两层介质基板中间设有金属接地板，所述上层介质基板顶层金属板设有顶层圆形贴片、第一输入端口馈线、第二输入端口馈线、顶层第一槽线和顶层第二槽线，所述下层介质基板底层金属板设有底层圆形贴片、第一输出端口馈线、第二输入端口馈线、底层第一槽线和底层第二槽线，所述金属接地板设有接地板第一槽线和接地板第二槽线。所述输入端口馈线一端延伸至介质基板的侧边，另一端与圆形贴片相切。
The invention discloses a dual-pass-band balanced filter using a double-layer circular patch, comprising an upper and lower layer of dielectric substrates, a metal grounding plate is arranged between the upper and lower layers of the dielectric substrate, and a top metal plate of the upper layer of the dielectric substrate The top layer circular patch, the first input port feeder, the second input port feeder, the top layer first slot line and the top layer second slot line are provided, and the bottom layer metal plate of the lower dielectric substrate is provided with the bottom layer circular patch, the first The output port feeder line, the second input port feeder line, the bottom first slot line and the bottom layer second slot line, the metal ground plate is provided with the ground plate first slot line and the ground plate second slot line. One end of the input port feed line extends to the side of the dielectric substrate, and the other end is tangent to the circular patch.
Description
Technical Field
The invention relates to the technical field of microwave passive devices, in particular to a dual-passband balance filter adopting a double-layer circular patch.
Background
Modern wireless communication systems require compact and high performance balanced bandpass filters. In recent years, the multi-passband filter has attracted extensive research interest due to the diversity of operating frequencies in the same device, and since many rf devices have strong robustness to electromagnetic interference and common mode noise, and thus the addition of the balancing function is required, the integration of the dual-passband, the balancing and the bandpass filtering can greatly reduce the number of microwave devices used in the same system. However, a multi-passband balanced filter with good application prospects has not been widely studied. To achieve the balancing function, a Dual-Mode Ring resonator is introduced in document 2[ w.feng, w.che, and q.xue, "New Balance-Applications for Dual-Mode Ring," IEEE micro.maga.vol., No., pp.15-23, july.2019 ]. The method has the advantages of multiple transmission zeros, high selectivity, strong harmonic suppression capability and the like.
Document 3[ g.g.roberto, m.f.jos-mari a, w.f.f and p.dimitra, "Balanced symmetric Quasi-reflective Single and Dual-Band Planar Filters," IEEE micro.wireless company.lett.vol.28, No.9, pp.798-800, sept.2018 ] consists of a direct input-output k-order branch BPF, the characteristic impedance of the quarter-wavelength terminal of which is connected to a virtual short circuit for differential mode operation. Although the above designs use different resonators, they all use microstrip structures, resulting in a large amount of space in the circuit being underutilized, making the circuit too bulky.
Document 4[ h.liu, t.liu and q.zhang, "Compact Balanced band transmit SIR Pairs and Spoof Surface plasma polarization Feeding Structure," IEEE micro.wire company.lett.vol.28, No.11, pp.987-989, No. 2018 ] designs a Compact Balanced BPF with high impedance bandwidth and high CM suppression Using Asymmetric SIR Pairs. The structure of the SIR takes full advantage of the reduction in circuit size.
Document 5[ q.liu, j.wang, g.zhang, l.zhu and w.wu, "a New Design Approach for Balanced bandwidth," IEEE micro.wire composite.lett.vol.29, No.1, pp.5-7, jun.2019 ] utilizes the resonance characteristics of single-wall double-wall isosceles right triangle patch resonators to achieve the effect of Balanced filtering. Compared with documents 2 to 4, 5 adopts patch resonance, has no vacant position in the circuit, and fully utilizes space. However, the simple distribution of the patches in the same plane also makes the circuit too large. Although documents 2 to 5 implement the functions of balancing and filtering, they all have only one pass band.
In document 6[ b.ren, z.ma, h.liu, m.ohira, x.guan and p.wen, "Design of Balanced Dual-Band Superconducting bandwidth Filter With High Selectivity and Deep Common-Mode Suppression," Asia-capacitive micro.configuration.vol., No., pp.,2018 ], a Balanced Dual-Band Bandpass Filter was designed using a new symmetric cylindrical resonator.
Document 7[ y.song, h.liu, w.zhao, p.wen, and z.wang, "Compact Balanced Dual-Band Filter With High Common-Mode Suppression Using Planar Via-Free CRLH Resonator," IEEE micro.wireless component.lett.vol.28, No.11, pp.996-999, nov.2018 ] implements a Dual-frequency Balanced Filter consisting of independent capacitors and curved microstrip lines Using the proposed structure of a Planar, channel-Free CRLH Resonator. However, documents 6 and 7 have the same problem as documents 2 and 3, and the circuit is too large.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the technical problem of providing a dual-passband balance filter adopting a double-layer circular patch aiming at the defects of the prior art.
In order to solve the technical problem, the invention discloses a dual-passband balance filter adopting a double-layer circular patch, which is characterized by comprising an upper-layer dielectric substrate and a lower-layer dielectric substrate, wherein a metal grounding plate is arranged between the upper-layer dielectric substrate and the lower-layer dielectric substrate, and a top-layer metal plate arranged on the upper surface of the upper-layer dielectric substrate consists of the following parts: the top layer circular patch is positioned in the center of the upper layer dielectric slab, the first input port feeder line and the second input port feeder line are positioned at the edge of the upper layer dielectric slab and connected with the top layer circular patch, and the top layer first slot line and the top layer second slot line are positioned on a diagonal CD of the upper layer dielectric slab; the lower surface of the lower medium substrate is provided with a bottom metal plate which consists of the following parts: the bottom circular patch is positioned in the center of the lower dielectric slab, the first output port feeder line and the second output port feeder line are positioned on the edge of the upper dielectric substrate and connected with the top circular patch, the bottom first slot line and the bottom second slot line are positioned on the diagonal line C 'D' of the upper dielectric substrate, and the metal ground plate is provided with a ground plate first slot line and a ground plate second slot line which are positioned on the diagonal line AB of the metal ground plate.
In the invention, the first input port feeder is an input first 50 ohm microstrip line conduction band, one end of the input first 50 ohm microstrip line conduction band extends to the side edge of the upper layer dielectric substrate, the other end of the input first 50 ohm microstrip line conduction band is tangent to the top layer circular patch, the second input port feeder comprises an input second 50 ohm microstrip line conduction band, one end of the input second 50 ohm microstrip line conduction band extends to the side edge of the upper layer dielectric substrate, and the other end of the input second 50 ohm microstrip line conduction band is tangent to the top layer circular patch.
In the invention, the first output port feeder line is used for outputting a first 50 ohm microstrip line conduction band, one end of the first 50 ohm microstrip line conduction band is extended to the side edge of the lower layer dielectric substrate, the other end of the first 50 ohm microstrip line conduction band is tangent to the bottom layer circular patch, the second output port feeder line comprises a second 50 ohm microstrip line conduction band, one end of the second 50 ohm microstrip line conduction band is extended to the side edge of the lower layer dielectric substrate, and the other end of the second 50 ohm microstrip line conduction band is tangent to the bottom layer circular patch.
In the invention, the first input port feeder line and the second input port feeder line are respectively positioned at the lower edge and the right edge of the upper-layer dielectric substrate, extension lines of the first input port feeder line and the second input port feeder line are mutually vertical, an intersection point of the extension lines is a middle point of the upper-layer dielectric substrate, and the top-layer first slot line and the top-layer second slot line are positioned on a diagonal line CD of the upper-layer dielectric substrate. The first output port feeder line and the second output port feeder line are respectively positioned at the upper edge and the left edge of the lower-layer dielectric substrate, extension lines of the first output port feeder line and the second output port feeder line are perpendicular to each other, an intersection point of the extension lines is a middle point of the lower-layer dielectric substrate, and the first slot line at the bottom layer and the second slot line at the bottom layer are positioned on a diagonal line C 'D' of the lower-layer dielectric substrate. The ground plate first slot line and the ground plate second slot line are positioned on the metal ground plate diagonal line AB.
In the invention, the first slot line and the second slot line of the grounding plate on the metal grounding plate are symmetrical about a diagonal GH of the metal grounding plate, the first slot line and the second slot line of the top layer are symmetrical about a diagonal EF of the upper-layer dielectric substrate, and the first slot line and the second slot line of the bottom layer are symmetrical about a diagonal E 'F' of the lower-layer dielectric substrate.
In the invention, the first input port feeder line and the second input port feeder line are symmetrical about a diagonal EF of the upper layer dielectric substrate, the first output port feeder line and the second output port feeder line are symmetrical about a diagonal E 'F' of the lower layer dielectric substrate, the first input port feeder line is perpendicular to the first output port feeder line in a non-coplanar manner, the second input port feeder line is perpendicular to the second output port feeder line in a non-coplanar manner, the second input port feeder line is parallel to the first output port feeder line, and the first input port feeder line is parallel to the second output port feeder line.
In the invention, the intersection point of the extension lines of the first input port feeder and the second input port feeder is the middle point of a diagonal line CD of the upper-layer dielectric substrate; and the intersection point of the extension lines of the first output port feeder line and the second output port feeder line is the midpoint of a diagonal line C 'D' of the lower dielectric substrate.
Has the advantages that: by adopting the technical scheme, compared with the prior art, the invention has the following advantages:
due to the fact that the patch structure is adopted, compared with a microwave device in a traditional micro-strip mode, the inner space of the microwave device can be utilized more fully, on the other hand, the double-layer structure is adopted, the size of the microwave device is enabled to be more fully utilized compared with the traditional direct flat-laying type design, and further the microwave device combines three functions of a double-pass band, a balancer and a filter. The three advantages enable the circuit to be simple in structure, small in size and complete in function, can be achieved on a single PCB, is convenient to process and integrate, and has a balanced double-frequency filter with good common-mode rejection performance.
Drawings
The above and other advantages of the present invention will become more apparent from the following detailed description of the invention when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic perspective view of a dual-passband balanced filter employing a double-layer circular patch according to the present invention.
Fig. 2 is a side view of fig. 1.
Fig. 3 is a top view of each metal layer of fig. 1.
Fig. 4 is a dimension diagram of each metal layer of fig. 1.
Fig. 5 is an S-parameter simulation diagram of example 1.
Fig. 6 is a phase difference simulation diagram of two output ports of example 1.
In fig. 1, a first input port feeder 1, a second input port feeder 2, a first output port feeder 3, a second output port feeder 4, a top circular patch 8, a bottom circular top layer 9, a top first slot line 51, a top second slot line 52, a ground plate first slot line 61, a ground plate second slot line 62, a bottom first slot line 71, a bottom second slot line 72, an upper dielectric substrate 101, a lower dielectric substrate 102, a metal ground plate 200, a top metal sheet 401, and a bottom metal sheet 402.
Detailed Description
Example 1:
as shown in fig. 1 and 3, this example provides a dual-passband balanced filter using a double-layer circular patch. Comprises a metal grounding plate 200, an upper dielectric substrate 101 and a lower dielectric substrate 102. A ground plate first slot line 61 and a ground plate second slot line 62 are arranged on the metal ground plate 200, and a top metal plate 401 on the upper surface of the upper dielectric substrate 101 is composed of the following parts: the first input port feeder 1 and the second input port feeder 2 are located at the edge of the upper-layer dielectric metal plate 101 and connected with the top-layer circular patch 8, the bottom-layer metal plate 402 of the lower-layer dielectric substrate 102 is provided with a first output port feeder 3 and a second output port feeder 4 which are located at the edge of the lower-layer dielectric substrate 102 and connected with the bottom-layer circular patch, the first input port feeder 1 and the second input port feeder 2 are respectively close to the mutually perpendicular edges of the upper-layer dielectric substrate 101, and the first output port feeder 3 and the second output port feeder 4 are respectively close to the mutually perpendicular edges of the lower-layer dielectric substrate 102. One end of the first input port feeder line 1 and one end of the second input port feeder line 2 are provided with a top layer circular patch 8 which is positioned at the center of the upper layer dielectric substrate 101, and one end of the first output port feeder line 3 and one end of the second output port feeder line 4 are provided with a bottom layer circular patch 9 which is positioned at the center of the lower layer dielectric substrate 102. The top layer circular patch 8 is provided with a top layer first slot line 51 and a top layer second slot line 52 which are positioned on an upper layer medium substrate diagonal line CD, and the bottom layer circular patch 9 is provided with a bottom layer first slot line 71 and a bottom layer second slot line 72 which are positioned on a lower layer medium substrate diagonal line C 'D'.
The ground plane first slot line 61 and the ground plane second slot line 62 are located on a diagonal line AB of the metal ground plane 200, and are symmetrical with respect to a vertical line of a diagonal line GH of the metal ground plane 200.
The first input port feeder 1 is an input first 50 ohm microstrip line conduction band 11, one end face of the input first 50 ohm microstrip line conduction band 11 is tangent to the top layer circular patch 8, the other end face of the input first 50 ohm microstrip line conduction band 11 is connected with the side face of the upper layer dielectric substrate 101, and the extension line of the first input port feeder 1 passes through the center of the upper layer dielectric substrate 101.
The second input port feeder 2 is an input second 50 ohm microstrip line conduction band 21, one end face of the input second 50 ohm microstrip line conduction band 21 is tangent to the bottom layer circular patch 9, the other end face of the input second 50 ohm microstrip line conduction band 21 is connected with the side face of the lower layer dielectric substrate 102, and the extension line of the second input port feeder 2 passes through the center of the upper layer dielectric substrate 101.
The first output port feeder line 3 is used for outputting a first 50 ohm microstrip conduction band 31, one end face of the first 50 ohm microstrip conduction band 31 is tangent to the bottom circular patch 9, the other end face of the first 50 ohm microstrip conduction band 31 is connected with the side face of the lower layer dielectric substrate 102, and the extension line of the first output port feeder line 3 passes through the center of the lower layer dielectric substrate 102.
The second output port feeder 4 is a second 50 ohm microstrip conduction band 41, one end face of the second 50 ohm microstrip conduction band 41 is tangent to the bottom circular patch 9, the other end face is connected with the side face of the lower dielectric substrate 102, and the extension line of the second output port feeder 4 passes through the center of the lower dielectric substrate 102.
The top circular patch 8 is positioned in the center of the upper dielectric substrate 101. The circle center of the top circular patch 8 is the intersection point of the extension lines of the first input port feeder line 1 and the second input port feeder line 2, and the top circular patch 8 is tangent to the first input port feeder line 1 and the second input port feeder line 2 respectively.
The bottom circular patch 9 is positioned at the center of the lower dielectric substrate 102. The circle center of the bottom layer circular patch 9 is the intersection point of extension lines of the first output port feeder line 3 and the second output port feeder line 4, and the bottom layer circular patch 9 is tangent to the first output port feeder line 3 and the second output port feeder line 4 respectively.
The top layer first slot line 51 and the top layer second slot line 52 are located on the diagonal CD of the upper layer dielectric substrate 101, and are symmetrical with respect to the diagonal EF of the upper layer dielectric substrate 101.
The bottom layer first slot line 61 and the bottom layer second slot line 62 are located on the diagonal C 'D' of the lower dielectric substrate 102, and are symmetrical with respect to the diagonal E 'F' of the lower dielectric substrate 102.
The top first slot line 51 and the top second slot line 52 on the top circular patch 8 and the bottom first slot line 71 and the bottom second slot line 72 on the bottom circular patch 9 are used to perturb the resonant mode TM21 to affect the center frequency of the second pass band. The ground plane first slot line 61 and the ground plane second slot line 62 on the metallic ground plane 200 transmit the resonance modes TM11 and TM21 of the patch from the upper layer to the lower layer.
The embodiment processes and corrodes the metal surfaces of the front surface and the back surface of the circuit substrate in the manufacturing process through the printed circuit board manufacturing process, so that required metal patterns are formed, the structure is simple, the method can be realized on a single PCB, and the processing and integration are convenient. Meanwhile, the design not only realizes the function of the double-frequency balance filter, but also fully utilizes the circuit space and greatly reduces the circuit volume due to the adoption of the circular patch and the double-layer structure. By using the resonant modes TM11 and TM21 of the ground plate slot line transfer patch, a balanced dual-frequency filter with good common-mode rejection performance is designed. The present invention is described in further detail below.
The structure of example 1 is shown in fig. 1, the top view is shown in fig. 3, and the relevant dimensions are shown in fig. 4. The adopted matrixes of the upper dielectric substrate 101 and the lower dielectric substrate 102 are RO4003C matrixes, the relative dielectric constant is 3.55, the thickness is 0.508mm, and the loss tangent is 0.0027. With reference to fig. 4, the two-passband balanced filter using the double-layer circular patch has the following dimensional parameters: r is 8.0mm, L1＝6.0mm,L2＝4.9mm,W1＝0.3mm,W2The total area of the double-passband balance filter of the double-layer circular patch, which does not comprise a 50-ohm microstrip line conduction band, is 16 multiplied by 16mm2The corresponding waveguide length dimension is 0.50 lambdag×0.50λgWherein λ isgThe length of the waveguide having a center frequency of 6.8 GHz.
The dual-passband balanced filter using the double-layer circular patch in this example was modeled and simulated in the electromagnetic simulation software hfss.13.0. Fig. 5 is a simulation diagram of the S-parameters and the two-path output phases of the dual-passband balanced filter using the double-layer circular patch in this example, and it can be seen from the diagram that the center frequencies of the dual-passband balanced filter using the double-layer circular patch are 5.5GHz and 8.1GHz, the 3-dB bandwidths are 1.0GHz and 2.0GHz, the return loss in the passband is lower than 20dB, the minimum insertion loss is 1dB, and the minimum common mode rejection is 20 dB.
Fig. 6 is a phase simulation diagram of two power output ports of the dual band-pass balanced filter of the double-layer circular patch in this example, and it can be seen that the phase difference is between 179 deg. -181 deg..
In summary, the dual-band balanced filter of the present embodiment employs the dual-layer circular patch. A dual-band balanced filter was designed using the resonant modes of the circular patches TM11 and TM 21. The resonant frequency is changed by the slot perturbation on the patch. A crack in the ground transmits a particular resonant mode to another layer. In addition, the center frequencies of the two pass bands can be independently controlled. The dual-frequency balanced filter is very suitable for modern wireless communication systems.
The present invention provides a concept and a method for a dual-band balanced filter using a dual-layer circular patch, and a method and a way for implementing the technical solution are many, and the above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. All the components not specified in the present embodiment can be realized by the prior art.
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| CN113161702A (en) * | 2021-05-10 | 2021-07-23 | 桂林电子科技大学 | Filter adopting annular microstrip patch resonator |
| CN113644397A (en) * | 2021-07-13 | 2021-11-12 | 广东盛路通信科技股份有限公司 | A balanced-to-single-ended power division filter |
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