CN111613601A - Semiconductor package including bridge die - Google Patents

Abstract

A semiconductor package including a bridge wafer. A semiconductor package includes an external redistribution line (RDL) structure, a first semiconductor chip disposed on the external RDL structure, a stacked module stacked on the first semiconductor chip, and a bridge wafer stacked on the external RDL structure. A portion of the stacked module laterally protrudes from a side surface of the first semiconductor chip. The bridging wafer supports the tabs of the stacked modules. The stacked module includes an inner RDL structure, a second semiconductor chip disposed on the inner RDL structure, a capacitor wafer disposed on the inner RDL structure, and an inner encapsulant. The capacitor wafer serves as a decoupling capacitor for the second semiconductor chip.

Description

Semiconductor package including bridge die

technical field

The present disclosure relates to semiconductor packaging technology, and more particularly, to a semiconductor package including a bridge die.

Background technique

Recently, much effort has been devoted to integrating multiple semiconductor chips into a single semiconductor package. That is, attempts have been made to increase the package integration density to realize high-performance semiconductor packages that process large amounts of data at high speed through multi-function operations. For example, system-in-package (SiP) technology can be considered an attractive candidate for realizing high performance semiconductor packaging. A plurality of semiconductor chips included in each SiP are arranged side by side. However, this may make it difficult to reduce the width of the SiP. Therefore, various techniques for arranging multiple semiconductor chips in SiP packages have been proposed to reduce the size of SiPs.

SUMMARY OF THE INVENTION

According to one embodiment, a semiconductor package includes: an external redistribution line (RDL) structure; a first semiconductor chip disposed on the external RDL structure; a stacked module stacked on the first semiconductor chip on, such that a portion of the stacked module protrudes laterally from the side surface of the first semiconductor chip in plan view; and a bridge wafer stacked on the outer RDL structure to support the protrusion of the stacked module and configured to include the stacked module Electrically connected to conductive vias of external RDL structures. The stacked module includes: an internal RDL structure; a second semiconductor chip disposed on the internal RDL structure such that die pads of the second semiconductor chip are electrically connected to the internal RDL structure; The semiconductor chips are spaced apart on the inner RDL structure and configured to include a capacitor electrically connected to the die pad through the inner RDL structure; and an inner encapsulant formed on the inner RDL structure to cover the second A semiconductor chip and the capacitor wafer.

Description of drawings

FIG. 1 is a cross-sectional view illustrating a system-in-package (SiP) according to one embodiment.

FIG. 2 is an enlarged cross-sectional view illustrating a portion of FIG. 1 including a bridge wafer.

FIG. 3 is a perspective view illustrating electrical paths connecting the semiconductor chips shown in FIG. 2 to each other.

FIG. 4 is an enlarged cross-sectional view focusing on the bridge wafer of FIG. 1 .

FIG. 5 is a plan view illustrating an array of stud bumps included in the bridge wafer of FIG. 4 .

FIG. 6 is an enlarged cross-sectional view illustrating a connection portion between the semiconductor chips shown in FIG. 1 .

FIG. 7 is a cross-sectional view illustrating a SiP according to another embodiment.

FIG. 8 is a cross-sectional view illustrating a SiP according to yet another embodiment.

FIG. 9 is a cross-sectional view illustrating a portion of FIG. 8 including through mold vias.

FIG. 10 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

11 is a cross-sectional view illustrating a capacitor wafer of a semiconductor package according to an embodiment.

FIG. 12 is a plan view illustrating internal redistribution lines provided in a stacked module of semiconductor packages according to one embodiment.

13 is a block diagram illustrating an electronic system employing a memory card including at least one SiP or at least one semiconductor package according to one embodiment.

14 is a block diagram illustrating another electronic system including at least one SiP or at least one semiconductor package according to one embodiment.

Detailed ways

Terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be interpreted differently according to those of ordinary skill in the art to which the embodiments belong. If defined in detail, terms can be interpreted according to the definition. Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another, and are not used to limit the elements themselves or to denote a particular order.

It will also be understood that when an element or layer is referred to as being "on," "over," "under," "under" or "outside" another element or layer, the element or layer can be directly on the other element or layer contacts, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers (eg, "between" versus "directly between" or "adjacent to" versus "directly adjacent to") should be used in a similar fashion way to explain.

Elements and/or features may be described using spatially relative terms such as "below," "below," "lower," "above," "upper," "top," "bottom," and the like Relationship to another element and/or feature, eg, as shown in the accompanying drawings. It will be understood that in addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use and/or operation. For example, when the device in the figures is turned over, elements described as below and/or below other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

A system-in-package (SiP) may correspond to a semiconductor package, and the semiconductor package may include electronic devices such as semiconductor chips or semiconductor wafers. Semiconductor chips or semiconductor wafers can be obtained by dividing a semiconductor substrate such as a wafer into pieces using a wafer sawing process. The semiconductor chip may correspond to a memory chip, a logic chip, an application specific integrated circuit (ASIC) chip, an application processor (AP), a graphics processing unit (GPU), a central processing unit (CPU), or a system on a chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a NAND type flash memory circuit, a NOR type flash memory circuit, a magnetic random access memory (MRAM) circuit, Resistive Random Access Memory (ReRAM) circuits, Ferroelectric Random Access Memory (FeRAM) circuits or Phase Change Random Access Memory (PcRAM) circuits. The logic chip may include logic circuits integrated on a semiconductor substrate. Semiconductor packages can be used in communication systems such as mobile phones, electronic systems associated with biotechnology or healthcare, or wearable electronic systems. The semiconductor package may be suitable for the Internet of Things (IoT).

Throughout the specification, the same reference numbers refer to the same elements. Even if a reference number is not mentioned or described with reference to one drawing, the reference number will be mentioned or described with reference to another drawing. In addition, even if a reference number is not shown in a drawing, a reference number will be referred to or described with reference to another drawing.

FIG. 1 is a cross-sectional view illustrating a system-in-package (SiP) 10 according to one embodiment.

Referring to FIG. 1 , the SiP 10 may be configured to include a redistribution line (RDL) structure 100 , a first semiconductor chip 300 , a second semiconductor chip 400 and a bridge wafer 500 .

The first semiconductor chip 300 may be disposed on the RDL structure 100 . The second semiconductor chip 400 may be stacked on the surface of the first semiconductor chip 300 opposite to the RDL structure 100 to overlap the first semiconductor chip 300 . The second semiconductor chip 400 may be stacked on the first semiconductor chip 300 to have protrusions 435 corresponding to overhangs protruding laterally from vertical lines aligned with the side surfaces of the first semiconductor chip 300 . The bridge wafer 500 may be disposed on the RDL structure 100 to support the protrusions 435 of the second semiconductor chip 400 . The bridge wafer 500 may be disposed between the protrusions 435 of the second semiconductor chip 400 and the RDL structure 100 and may be disposed laterally spaced apart from the first semiconductor chip 300 in the same direction as the protrusions 435 .

The SiP 10 may also include a mold layer 700 formed on the RDL structure 100 . The molding layer 700 may be formed to cover the first semiconductor chip 300 and the bridge wafer 500 . The molding layer 700 may extend to cover the second semiconductor chip 400 . The molding layer 700 may be formed to surround and protect the second semiconductor chip 400 and expose the second surface 402 of the second semiconductor chip 400 opposite to the first semiconductor chip 300 . In the case where the molding layer 700 is formed to expose the second surface 402 of the second semiconductor chip 400, heat from the second semiconductor chip 400 and the first semiconductor chip 300 generated by the operation of the SiP 10 may pass through the second semiconductor chip 400. The second surface 402 of the chip 400 diffuses more easily to the outside space. The molding layer 700 may be formed of any of various molding materials or encapsulating materials. For example, the molding layer 700 may be formed of an epoxy molding compound (EMC) material.

FIG. 2 is an enlarged cross-sectional view illustrating a portion of FIG. 1 including the bridge wafer 500 .

Referring to FIGS. 1 and 2 , the RDL structure 100 may include a first RDL pattern 120 . The first RDL pattern 120 may be a conductive pattern having a first end overlapping a portion of the first semiconductor chip 300 and a second end overlapping a portion of the bridge wafer 500 .

The first semiconductor chip 300 may include a first group of die pads 310 . The first semiconductor chip 300 may be disposed on the RDL structure 100 such that the first die pads 312 of the first semiconductor chip 300 are electrically connected to the first ends of the first RDL patterns 120 . The first die pad 312 may be any one of the first set of die pads 310 . The first semiconductor chip 300 may be flip-chip mounted on the RDL structure 100 such that the first set of die pads 310 of the first semiconductor chip 300 face the RDL structure 100 .

The first set of internal connectors 610 may be disposed between the first semiconductor chip 300 and the RDL structure 100 to electrically connect the first semiconductor chip 300 to the RDL structure 100 . The first set of internal connectors 610 may be conductive bumps or solder bumps. The fifth internal connector 612 may be bonded to a portion of the first RDL pattern 120 to electrically connect the first die pad 312 to the first RDL pattern 120 . The fifth internal connector 612 may be any of the first set of internal connectors 610 .

The second semiconductor chip 400 may include a second group of die pads 410 disposed on the protrusions 435 of the second semiconductor chip 400 . The second semiconductor chip 400 may be mounted on the first semiconductor chip 300 in a flip chip form. Therefore, the second die pad 412 disposed on the protrusion 435 may face the RDL structure 100 . Since the second die pads 412 are disposed on the protrusions 435 , it is impossible for the second die pads 412 to vertically overlap with the first semiconductor chip 300 to be exposed in an outer area of the first semiconductor chip 300 . The second die pad 412 may be any one of the second set of die pads 410 .

The bridge wafer 500 may be disposed on the RDL structure 100 to overlap the protrusions 435 of the second semiconductor chip 400 . The bridge wafer 500 may be configured to include a body 510 and a plurality of vias 520 extending through the body 510 . Although not shown in the drawings, an insulating layer may be additionally disposed between the body 510 and each of the through holes 520 to electrically insulate the through holes 520 from the body 510 . The first through holes 522 may be disposed to overlap the second die pads 412 of the second semiconductor chip 400 and may be electrically connected to the second die pads 412 . The first through hole 522 may be any one of the through holes 520 . The first through holes 522 may be disposed to overlap the second ends of the first RDL patterns 120 and may be electrically connected to the first RDL patterns 120 overlapping the first through holes 522 . The first through holes 522 may be disposed to electrically connect the second die pads 412 to the first RDL patterns 120 in a vertical direction.

The bridge wafer 500 may also include a plurality of stud bumps 530 . The first stud bumps 532 may be disposed on the body 510 to protrude from the top surface of the body 510 . The first stud bumps 532 may be connected to the tops of the first through holes 522 . The first stud bumps 532 may be any of the stud bumps 530 .

A third set of internal connectors 630 may be disposed between the bridge wafer 500 and the second semiconductor chip 400 to electrically connect the bridge wafer 500 to the second semiconductor chip 400 . The bridge wafer 500 may be bonded to the second semiconductor chip 400 through the third set of internal connectors 630 and may be electrically connected to the second semiconductor chip 400 through the third set of internal connectors 630 . The second internal connectors 632 may electrically connect the second die pads 412 to the first stud bumps 532 . The second internal connector 632 may be any of the third set of internal connectors 630 . The bridge wafer 500 may also include via pads 540 disposed on the bottom surface of the body 510 . The first via pad 542 may be connected to the bottom of the first via 522 . The first via pad 542 may be any of the via pads 540 .

A second set of internal connectors 620 may be disposed between the bridge die 500 and the RDL structure 100 to electrically connect the bridge die 500 to the RDL structure 100 . The bridge die 500 can be bonded to the RDL structure 100 through the second set of internal connectors 620 and can be electrically connected to the RDL structure 100 through the second set of internal connectors 620 . The first internal connector 622 may engage and be electrically coupled to the first via pad 542 . The first internal connector 622 may be any of the second set of internal connectors 620 . The first internal connector 622 may be bonded to a portion of the first RDL pattern 120 to electrically connect the first via pad 542 to the first RDL pattern 120 .

FIG. 3 is a perspective view illustrating a first electrical path P1 that electrically connects the first semiconductor chip 300 and the second semiconductor chip 400 to each other shown in FIG. 2 .

2 and 3 , the bridge wafer 500 structurally supports the protrusions 435 of the second semiconductor chip 400 and also provides a portion of the first electrical path P1 that electrically connects the second semiconductor chip 400 to the first semiconductor chip 300 . The first electrical path P1 may be configured to include the second die pad 412 of the second semiconductor chip 400 , the second internal connector 632 , the first stud bump 532 , the first via 522 , the first via pad 542 , the first internal connector 622 , the first RDL pattern 120 , the fifth internal connector 612 , and the first die pad 312 of the first semiconductor chip 300 .

The first semiconductor chip 300 may be a processor that performs logical operations on data. For example, the first semiconductor chip 300 may include a system on chip (SoC) such as an application processor that performs logic operations. The second semiconductor chip 400 may be a memory semiconductor chip that stores data. The memory semiconductor chips can be used as cache memory chips that temporarily store and provide data used in the logic operations of the SoC. The second semiconductor chip 400 may be configured to include a DRAM device.

As shown in FIG. 3 , the first group of die pads 310 of the first semiconductor chip 300 may be uniformly disposed on the entire area of the first surface 301 of the first semiconductor chip 300 . The second group of die pads 410 of the second semiconductor chip 400 may be disposed on the protrusions 435 of the second semiconductor chip 400 . The second group of die pads 410 of the second semiconductor chip 400 may be disposed on a portion (ie, the protrusion 435 ) of the second semiconductor chip 400 overhanging the first semiconductor chip 300 (that does not overlap with the first semiconductor chip 300 ). . The second group of die pads 410 of the second semiconductor chip 400 may be disposed on the peripheral region 430 of the second semiconductor chip 400 . The peripheral region 430 on which the second group of die pads 410 are disposed may be located on the first surface 401 of the protrusion 435 of the second semiconductor chip 400 .

The second semiconductor chip 400 may partially overlap the first semiconductor chip 300 . Other regions of the second semiconductor chip 400 other than the protrusions 435 may overlap with the first semiconductor chip 300 . Other regions of the second semiconductor chip 400 may be covered by the first semiconductor chip 300 . Therefore, the second group of die pads 410 of the second semiconductor chip 400 may not be disposed on other regions of the second semiconductor chip 400 .

The first die pad 312 may be electrically connected to the second die pad 412 of the second semiconductor chip 400 through the first electrical path P1. The first die pad 312 may be one of the first set of die pads 310 . Although FIG. 3 illustrates the first electrical path P1 as a single path, the SiP 10 may include multiple first electrical paths P1. In this case, the first group of die pads 310 may be electrically connected to the second group of die pads 410 through a plurality of first electrical paths P1, respectively. In an embodiment, each of the plurality of first electrical paths P1 may be configured to include one of the second set of die pads 410 of the second semiconductor chip 400 , one of the third set of internal connectors 630 , a columnar One of bumps 530 , one of vias 520 , one of via pads 540 , one of second set of internal connectors 620 , one of first RDL patterns 120 , first set of internal connectors 610 and one of the first group of die pads 310 of the first semiconductor chip 300 . Since the second semiconductor chip 400 is electrically connected to the first semiconductor chip 300 through the plurality of first electrical paths P1, a plurality of input/output (I/O) may be provided between the first semiconductor chip 300 and the second semiconductor chip 400 path. That is, since two adjacent semiconductor chips are electrically connected to each other through a plurality of short signal paths corresponding to the I/O paths, it is possible to pass a plurality of paths between the two adjacent semiconductor chips instead of a single one The path sends relatively much data at the same time. Therefore, a larger amount of data can be transferred from the first semiconductor chip 300 to the second semiconductor chip 400 at a given speed using parallel paths, and vice versa. If the first semiconductor chip 300 is a logic chip (eg, a processor chip) and the second semiconductor chip 400 is a memory chip, the first semiconductor chip 300 may operate together with the second semiconductor chip 400 serving as a high-performance cache memory . Therefore, the operation speed and performance of the SiP 10 including the first semiconductor chip 300 and the second semiconductor chip 400 can be improved.

Referring again to FIG. 2 , the second semiconductor chip 400 may further include third die pads 411 provided on the protrusions 435 to be spaced apart from the second die pads 412 . The bridge wafer 500 may further include second stud bumps 531 disposed to substantially overlap the third die pads 411 . The bridge wafer 500 may further include second vias 521 electrically connected to the second stud bumps 531 and disposed to be spaced apart from the first vias 522 . The bridge wafer 500 may also include second via pads 541 electrically connected to the second vias 521 .

The RDL structure 100 may further include a second RDL pattern 110 arranged to be spaced apart from the first RDL pattern 120 . The second RDL pattern 110 may be disposed to have a portion overlapping the second via pad 541 . The second RDL pattern 110 may be electrically connected to the first external connector 210 through the fifth RDL pattern 140 . The first external connector 210 may be one of a plurality of external connectors 200 connected to the RDL structure 100 . The external connector 200 may be used as a connection terminal or a connection pin for electrically connecting the SiP 10 to an external device. The external connector 200 may be a connection member such as a solder ball.

The RDL structure 100 may further include a first dielectric layer 191 disposed between the fifth RDL pattern 140 and the second RDL pattern 110 . The first RDL pattern 120 and the second RDL pattern 110 may be disposed on the top surface of the first dielectric layer 191 , and the fifth RDL pattern 140 may be disposed on the bottom surface of the first dielectric layer 191 . The fifth RDL pattern 140 may substantially penetrate the first dielectric layer 191 to be connected to the second RDL pattern 110 . The RDL structure 100 may further include a second dielectric layer 193 disposed on a top surface of the first dielectric layer 191 opposite to the external connector 200 to connect the second RDL pattern 110 with the first RDL The patterns 120 are electrically isolated. The RDL structure 100 may further include a third dielectric layer 195 disposed on a bottom surface of the first dielectric layer 191 opposite to the first semiconductor chip 300 to connect the fifth RDL pattern 140 with the SiP 10 external space is electrically isolated. The first external connector 210 may substantially penetrate the third dielectric layer 195 to be connected to the fifth RDL pattern 140 .

The sixth inner connector 621 may be bonded to the second RDL pattern 110 to electrically connect the second via pad 541 to the second RDL pattern 110 . The sixth internal connector 621 may be any of the second set of internal connectors 620 that electrically connect the bridge die 500 to the RDL structure 100 . The seventh internal connector 631 may electrically connect the second stud bump 531 to the third die pad 411 . The seventh internal connector 631 may be any one of the third set of internal connectors 630 that electrically connect the bridge wafer 500 to the second semiconductor chip 400 .

2 and 3, the second electrical path P2 may be provided to include the first external connector 210, the fifth RDL pattern 140, the second RDL pattern 110, the sixth internal connector 621, the second via pad 541, The second through hole 521 , the second stud bump 531 , the seventh internal connector 631 and the third die pad 411 . The second electrical path P2 may be a path that electrically connects the second semiconductor chip 400 to the first external connector 210 . Unlike the first electrical path P1 , the second electrical path P2 may not be electrically connected to the first semiconductor chip 300 . The first electrical path P1 may electrically connect the first semiconductor chip 300 and the second semiconductor chip 400 to each other such that the first semiconductor chip 300 and the second semiconductor chip 400 communicate with each other. In contrast, the second electrical path P2 may be used as an electrical path for supplying the power supply voltage or the ground voltage to the second semiconductor chip 400 .

Referring again to FIG. 2 , the RDL structure 100 may further include a third RDL pattern 130 disposed to be spaced apart from the first RDL pattern 120 and the second RDL pattern 110 . The third RDL pattern 130 may be positioned to overlap the first semiconductor chip 300 . The third RDL pattern 130 may be electrically connected to the second external connector 230 through the sixth RDL pattern 150 . The first semiconductor chip 300 may further include fourth die pads 313 disposed to be spaced apart from the first die pads 312 . The third internal connector 613 may be provided to electrically connect the fourth die pad 313 to the third RDL pattern 130 . The third internal connector 613 may be any one of the first set of internal connectors 610 that electrically connect the first semiconductor chip 300 to the RDL structure 100 .

The third electrical path P3 may be provided to include the fourth die pad 313 , the third internal connector 613 , the third RDL pattern 130 , the sixth RDL pattern 150 and the second external connector 230 . The third electrical path P3 may be an electrical path that electrically connects the first semiconductor chip 300 to the second external connector 230 . The first semiconductor chip 300 may communicate with the external device through the third electrical path P3, or may receive power from the external device through the third electrical path P3.

FIG. 4 is an enlarged cross-sectional view illustrating a portion of FIG. 1 including the bridge wafer 500 . FIG. 5 is a plan view illustrating the stud bumps 530 of the bridge wafer 500 shown in FIG. 4 .

Referring to FIGS. 1 and 4 , the body 510 of the bridge wafer 500 may correspond to a semiconductor substrate such as a silicon substrate. When the body 510 of the bridge wafer 500 is made of a silicon material, the via 520 may be formed using a photolithography process applied to a silicon wafer. The vias 520 of the bridge wafer 500 may correspond to through-silicon vias (TSVs) having a diameter D1. The diameter D1 may be smaller than the diameter of the through-mold via (TMV) through the molding layer. Therefore, the number of through holes 520 formed in the body 510 having a limited size can be increased.

As shown in FIG. 3 , the second group of die pads 410 may be densely disposed on the protrusions 435 of the second semiconductor chip 400 . The stud bumps 530 of the bridge wafer 500 electrically connected to the second group of die pads 410 may include at least two bumps, as shown in FIG. 5 . In this case, the vias 520 of the bridge wafer 500 may be aligned with the second group of die pads 410 to overlap such that the stud bumps 530 overlap with the second group of die pads 410 of the second semiconductor chip 400 . Because the through hole 520 of the bridge wafer 500 is formed using the TSV process, the through hole 520 may be formed, for example, with a diameter D1 having a relatively small value compared to the diameter of the TMV. Therefore, the number of the through holes 520 of the bridge wafer 500 corresponding to the plurality of I/O terminals, power terminals, and ground terminals, respectively, can be maximized. That is, even if the second group of die pads 410 are densely arranged, the vias 520 bridging the wafer 500 may be formed such that the vias 520 are positioned to have the same pitch size as the second group of die pads 410 . Therefore, even if the second group of die pads 410 are densely arranged, the second group of die pads 410 can be vertically connected to the corresponding through holes 520 of the bridge wafer 500 without forming any further on the second semiconductor chip 400 . distribution line.

If the diameter D1 of the through hole 520 is reduced, the vertical length of the through hole 520 may also be reduced. When the through hole 520 is formed to penetrate the body 510 having the thickness T3, there may be a limitation in reducing the diameter D1 of the through hole 520 due to the limitation of the aspect ratio of the through hole filled with the through hole 520. In order to reduce the diameter D1 of the through hole 520 of the bridge wafer 500, it may be necessary to reduce the thickness T3 of the body 510 to meet the limitation of the aspect ratio of the via hole in which the through hole 520 is formed. In order to increase the number of through holes 520 formed in the body 510 , it may be necessary to reduce the thickness T3 of the body 510 to be smaller than the thickness T1 of the first semiconductor chip 300 . In this case, the diameter D1 of the through hole 520 of the bridge wafer 500 can be reduced.

In order for the bridge wafer 500 to structurally support the second semiconductor chip 400 , it may be effective to set the total thickness T2 of the bridge wafer 500 to be equal to the thickness T1 of the first semiconductor chip 300 . For example, the thickness T3 of the body 510 smaller than the thickness T1 of the first semiconductor chip 300 may be compensated by the thickness T4 of the stud bumps 530 of the bridge wafer 500 and the thickness T5 of the via pads 540 of the bridge wafer 500 . That is, by appropriately adjusting the thickness T4 of the stud bumps 530 of the bridge wafer 500 , the total thickness T2 of the bridge wafer 500 can be adjusted to be equal to the thickness T1 of the first semiconductor chip 300 . The total thickness T2 of the bridge wafer 500 may include the thickness T4 of the stud bumps 530 of the bridge wafer 500 , the thickness T5 of the via pads 540 of the bridge wafer 500 , and the thickness T3 of the body 510 .

The stud bumps 530 may be directly coupled to the third set of internal connectors 630, respectively. The diameter D2 of the first stud bump 532 may be larger than the diameter D1 of the through hole 520 . Therefore, the solder bumps used as the third set of internal connectors 630 may be directly bonded to the stud bumps 530 of the bridge wafer 500, respectively. In order for the via pads 540 of the bridge wafer 500 to be directly bonded to the second set of internal connectors 620 , the diameter D3 of the via pads 540 may be larger than the diameter D1 of the vias 520 .

FIG. 6 is an enlarged cross-sectional view illustrating a connection portion between the first semiconductor chip 300 and the second semiconductor chip 400 shown in FIG. 1 .

1 and 6 , the second semiconductor chip 400 may partially overlap the first semiconductor chip 300 , and the protrusions 435 of the second semiconductor chip 400 may be supported by the bridge wafer 500 . The protrusions 435 of the second semiconductor chip 400 are bonded to the bridge wafer 500 through the third set of internal connectors 630 , and dummy bumps 690 may be used to support the edges 436 of the second semiconductor chip 400 opposite the protrusions 435 . Since the dummy bump 690 supports the edge 436 of the second semiconductor chip 400, the second semiconductor chip 400 can be prevented from tilting. Since the dummy bumps 690 are disposed between the first semiconductor chip 300 and the second semiconductor chip 400 when the protrusions 435 of the second semiconductor chip 400 are bonded to the bridge wafer 500, the second semiconductor chip 400 may remain horizontal.

The dummy bumps 690 may be solder bumps. The dummy bumps 690 may be attached to the first surface 401 of the second semiconductor chip 400 . Dummy bonding pads 691 may be formed on the first surface 401 of the second semiconductor chip 400 . In this case, the dummy bumps 690 may be bonded to the dummy bond pads 691 . The dummy bond pads 691 may be formed on the passivation layer 425 disposed on the first surface 401 of the second semiconductor chip 400 . Dummy bond pads 691 may be formed on passivation layer 425 using a metal sputtering process. The passivation layer 425 may be formed to cover and electrically insulate the body 420 (made of silicon material) of the second semiconductor chip 400 . Therefore, the dummy bumps 690 may be electrically insulated from the internal circuits of the second semiconductor chip 400 . The dummy bumps 690 may be in contact with the second surface 302 of the first semiconductor chip 300 opposite to the RDL structure 100 .

FIG. 7 is a cross-sectional view illustrating a SiP 11 according to another embodiment.

Referring to FIG. 7 , the SiP 11 may be configured to include an RDL structure 100 , a first semiconductor chip 300 , a second semiconductor chip 400 , a bridge wafer 500 and a molding layer 700 . The second semiconductor chip 400 may partially overlap the first semiconductor chip 300 , and the protrusions 435 of the second semiconductor chip 400 may be supported by the bridge wafer 500 . The adhesive layer 690L may be disposed between the first semiconductor chip 300 and the second semiconductor chip 400 . The adhesive layer 690L may support the second semiconductor chip 400 . The adhesive layer 690L may prevent the second semiconductor chip 400 from tilting when the protrusions 435 of the second semiconductor chip 400 are bonded to and supported by the bridge wafer 500 . The adhesive layer 690L may help the second semiconductor chip 400 to remain level.

The adhesive layer 690L may be attached to the first surface 401 of the second semiconductor chip 400 and the second surface 302 of the first semiconductor chip 300 . The adhesive layer 690L may bond the second semiconductor chip 400 to the first semiconductor chip 300 .

FIG. 8 is a cross-sectional view illustrating a SiP 12 according to yet another embodiment. FIG. 9 is a cross-sectional view illustrating a portion of FIG. 8 including a through die via (TMV) 2800 .

Referring to FIG. 8 , the SiP 12 may be implemented to have a package-on-package (PoP) shape. The SiP 12 may be configured to include a first sub-package SP1 and a second sub-package SP2 mounted on the first sub-package SP1. The first subpackage SP21 may be configured to include an RDL structure 2100 , a first semiconductor chip 2300 , a second semiconductor chip 2400 , a bridge wafer 2500 , a molding layer 2700 and a TMV 2800 .

The RDL structure 2100 may be configured to include a first RDL pattern 2120, a second RDL pattern 2110, a third RDL pattern 2130, a fourth RDL pattern 2170, a fifth RDL pattern 2140, a sixth RDL pattern 2150, a seventh RDL pattern 2180, and Eighth RDL pattern 2190. The RDL structure 2100 may further include a first dielectric layer 2191 , a second dielectric layer 2193 and a third dielectric layer 2195 . The first RDL pattern 2120 , the second RDL pattern 2110 , the third RDL pattern 2130 , the fourth RDL pattern 2170 and the seventh RDL pattern 2180 may be disposed on the top surface of the first dielectric layer 2191 . The second dielectric layer 2193 may be disposed on the top surface of the first dielectric layer 2191 such that the first RDL pattern 2120 , the second RDL pattern 2110 , the third RDL pattern 2130 , the fourth RDL pattern 2170 and the seventh RDL pattern 2180 electrically insulated from each other. The fifth RDL pattern 2140 , the sixth RDL pattern 2150 and the eighth RDL pattern 2190 may be disposed on the bottom surface of the first dielectric layer 2191 opposite to the second dielectric layer 2193 . The third dielectric layer 2195 may be formed on the bottom surface of the first dielectric layer 2191 to electrically insulate the fifth RDL pattern 2140 , the sixth RDL pattern 2150 and the eighth RDL pattern 2190 from each other.

The RDL structure 2100 may correspond to an interconnect structure electrically connected to the first semiconductor chip 2300 and the second semiconductor chip 2400 . In another embodiment, a printed circuit board (PCB) may be used as the interconnect structure.

External connectors 2200 may be attached to the RDL structure 2100 . The external connector 2200 may include a first external connector 2210, a second external connector 2230, and a third external connector 2270 that are spaced apart and electrically insulated from each other.

The first semiconductor chip 2300 may include a system on a chip (SoC), and the second semiconductor chip 2400 may include a first memory semiconductor chip. The second sub-package SP2 may include a second memory semiconductor chip connected to the SoC corresponding to the first semiconductor chip 2300 . The second memory semiconductor chip may include a NAND-type flash memory device or a DRAM device. The first memory semiconductor chip may function as a temporary memory device or a buffer memory device, and the second memory semiconductor chip may function as a main memory device.

The first semiconductor chip 2300 may include a plurality of die pads 2310 . The die pads 2310 of the first semiconductor chip 2300 may include a first die pad 2312 , a fourth die pad 2313 and a fifth die pad 2317 .

The first semiconductor chip 2300 may be electrically connected to the RDL structure 2100 through a plurality of internal connectors 2610 . The inner connector 2610 may include a third inner connector 2613 , a fourth inner connector 2617 and a fifth inner connector 2612 .

The second semiconductor chip 2400 may include protrusions 2435 corresponding to overhangs protruding laterally from vertical lines aligned with the side surfaces of the first semiconductor chip 2300 . The second semiconductor chip 2400 includes a plurality of die pads 2410 disposed on the protrusions 2435 .

The bridge wafer 2500 may structurally support the protrusions 2435 of the second semiconductor chip 2400 . Bridge wafer 2500 may be configured to include body 2510 , vias 2520 , stud bumps 2530 , and via pads 2540 .

The bridge die 2500 may be electrically connected to the RDL structure 2100 through the internal connectors 2620 . The bridge wafer 2500 may be electrically connected to the second semiconductor chip 2400 through other internal connectors 2630 .

A plurality of dummy bumps 2690 may be disposed between the first semiconductor chip 2300 and the second semiconductor chip 2400 to maintain the level of the second semiconductor chip 2400 .

The TMV 2800 may substantially penetrate the molding layer 2700 to be electrically connected to the RDL structure 2100 . The second sub-package SP2 may be disposed on the molding layer 2700 and may be electrically connected to the TMV 2800 through the interconnector 2250 . The interconnector 2250 may be a connection member such as a solder ball. Although not shown in the drawings, the second sub-package SP2 may be provided to include a semiconductor wafer containing integrated circuits, internal interconnect lines for electrical connection between components in the semiconductor wafer, and a protection for the semiconductor wafer. Molded layer.

Referring to FIG. 9 , the first TMV 2817 corresponding to any one of the TMVs 2800 may be connected to one end of the fourth RDL pattern 2170 . The other end of the fourth RDL pattern 2170 may be electrically connected to the fifth die pad 2317 of the first semiconductor chip 2300 through the fourth internal connector 2617 . The first TMV 2817 may be electrically connected to the second sub-package SP2 through the first interconnector 2257 corresponding to any one of the interconnectors 2250 . The first interconnector 2257, the first TMV 2817, the fourth RDL pattern 2170, the fourth internal connector 2617, and the fifth die pad 2317 may constitute a fourth electrical path P4. The fourth electrical path P4 may be a signal path connecting the second subpackage SP2 to the first semiconductor chip 2300 .

The second TMV 2818 corresponding to any one of the TMVs 2800 may electrically connect the seventh RDL pattern 2180 to the second interconnector 2258 corresponding to any one of the interconnectors 2250 . The seventh RDL pattern 2180 may be connected to the eighth RDL pattern 2190 , and the eighth RDL pattern 2190 may be connected to the third external connector 2270 . Therefore, the second interconnector 2258, the second TMV 2818, the seventh RDL pattern 2180, the eighth RDL pattern 2190, and the third external connector 2270 may constitute the fifth electrical path P5. The fifth electrical path P5 may be an electrical path for supplying a power supply voltage or a ground voltage to the second subpackage SP2.

As described above, according to the embodiment, the second semiconductor chip 400 (or 2400 ) may be stacked on the first semiconductor chip 300 (or 2300 ) to reduce the width or size of the SiP 10 , 11 or 12 . According to SiP 10, 11 or 12, since the second semiconductor chip 400 (or 2400) is electrically connected to the first semiconductor chip 300 (or 2300) using the bridge wafer 500 (or 2500), the second semiconductor chip 400 (or 2400) can be electrically connected to the first semiconductor chip 300 (or 2300). ) are stacked on the first semiconductor chip 300 (or 2300).

The process of applying heat to the semiconductor chip may degrade the characteristics of the semiconductor chip (especially the memory chip). For example, when heat is applied to a DRAM device, the data retention time of the memory cells of the DRAM device is shortened, reducing the refresh cycle of the DRAM device. In addition, if heat is applied to the NAND-type flash memory device, the data retention time of the memory cells of the NAND-type flash memory device is also shortened.

SiPs 10 , 11 and 12 according to embodiments of the present teachings may be implemented to include internal connectors attached to RDL structure 100 for interconnection between semiconductor chips and between external devices and the semiconductor chips. Thus, the heat treatment (or annealing process) for curing the polymer layer used to form the redistribution lines may be omitted or reduced. As a result, the performance of the SiPs 10, 11 and 12 can be improved. For example, if the first semiconductor chip 300 and the second semiconductor chip 400 are stacked on the RDL structure 100 to form the SiP 10, 11 or 12 after the RDL structure 100 is formed, it can be prevented from performing a heat treatment (or annealing process) to use Heat is applied to the first semiconductor chip 300 and the second semiconductor chip 400 while the polymer layer forming the RDL pattern is cured.

FIG. 10 is a cross-sectional view illustrating a semiconductor package 30 according to an embodiment.

10 , the semiconductor package 30 may be configured to include an outer RDL structure 3100 , a first semiconductor chip 3300 , a stacked module 3400S including a second semiconductor chip 3400 , a bridge wafer 3500 and an outer encapsulant 3700 . The semiconductor package 30 may correspond to a system-in-package (SiP). For example, the first semiconductor chip 3300 may be configured to include a system on a chip (SoC), and the second semiconductor chip 3400 may be configured to include a memory semiconductor chip. The memory semiconductor chip may be a memory chip that stores data, eg, a DRAM chip, and the SoC may be a logic chip that communicates with the second semiconductor chip 3400 to perform various logic operations.

The first semiconductor chip 3300 may be disposed on the outer RDL structure 3100 . The first semiconductor chip 3300 may be disposed on the outer RDL structure 3100 such that the first group of die pads 3310 of the first semiconductor chip 3300 corresponding to the connection terminals face the outer RDL structure 3100 . The first set of internal connectors 3610 may electrically connect the first set of die pads 3310 to the external RDL structure 3100 .

The external RDL structure 3100 may be used as an interconnection member to electrically connect the semiconductor package 30 to external devices or external systems. The outer RDL structure 3100 may be configured to include a first RDL pattern 3110 disposed on a surface of the first dielectric layer 3191 and a first RDL pattern 3110 disposed on the other surface of the first dielectric layer 3191 opposite to the first RDL pattern 3110. Two RDL patterns 3140. The second dielectric layer 3193 may be formed on the first dielectric layer 3191 to electrically isolate or insulate the first RDL patterns 3110 from each other. The third dielectric layer 3195 may be formed on the bottom surface of the first dielectric layer 3191 to electrically isolate or insulate the second RDL patterns 3140 from each other. The second RDL pattern 3140 may penetrate through the first dielectric layer 3191 to be electrically connected to the first RDL pattern 3110 . The external connector 3200 may be attached to the second RDL pattern 3140 .

The first group of internal connectors 3610 may electrically connect the first group of die pads 3310 of the first semiconductor chip 3300 to some of the first RDL patterns 3110 . The second set of internal connectors 3620 may electrically connect the conductive vias 3520 of the bridge wafer 3500 to other ones of the first RDL patterns 3110. Like the first RDL patterns 120 shown in FIG. 1 , further ones of the first RDL patterns 3110 may electrically connect the conductive vias 3520 of the bridge wafer 3500 to the first semiconductor chip 3300 . Still some of the first RDL patterns 3110 may electrically connect the conductive vias 3520 of the bridge wafer 3500 to the external connectors 3200 through the second RDL patterns 3140 .

Referring again to FIG. 10 , the stacked module 3400S may be vertically stacked on the first semiconductor chip 3300 . An adhesive layer 3340 may be disposed between the stacked module 3400S and the first semiconductor chip 3300 to attach the stacked module 3400S to the first semiconductor chip 3300 . The adhesive layer 3340 may fix the stacked module 3400S to the first semiconductor chip 3300 .

The stacked module 3400S may be stacked on the first semiconductor chip 3300 such that edges of the stacked module 3400S protrude laterally from the side surface 3301 of the first semiconductor chip to provide protrusions 3435 corresponding to the overhangs when viewed in plan. A bridge wafer 3500 may be disposed on the outer RDL structure 3100 to support the protrusions 3435 of the stacked module 3400S. Bridge wafer 3500 may be configured to include conductive vias 3520 that electrically connect stacked module 3400S to external RDL structure 3100 . The conductive vias 3520 may penetrate vertically through the body 3510 of the bridge wafer 3500 .

A third set of internal connectors 3630 may be disposed between the bridge wafer 3500 and the protrusions 3435 of the stacked module 3400S. The third set of internal connectors 3630 may electrically connect the vias 3520 of the bridge wafer 3500 to the second set of die pads 3410 of the second semiconductor chip 3400 of the stacked module 3400S. Therefore, the protrusions 3435 of the stacked module 3400S can be supported by the second group of internal connectors 3620 and the third group of internal connectors 3630 and can be stably fixed.

Similar to bridge wafer 500 shown in FIG. 1 , bridge wafer 3500 may be configured to further include stud bumps ( 530 of FIG. 1 ).

The stacked module 3400S is configured to include an internal RDL structure 3900 , a second semiconductor chip 3400 , a capacitor wafer 3800 , and an internal encapsulant 3750 . An inner encapsulant 3750 may be formed on the inner RDL structure 3900 to cover the second semiconductor chip 3400 and the capacitor wafer 3800 . The inner encapsulant 3750 can be used as a base layer for holding the inner RDL structure 3900, the second semiconductor chip 3400 and the capacitor wafer 3800 to provide a module. The inner sealant 3750 may be formed from at least one of various molding materials. The inner encapsulant 3750 may be formed from a molding layer including an epoxy molding compound (EMC) material.

The second semiconductor chip 3400 may be disposed on the inner RDL structure 3900 such that the second group of die pads 3410 are electrically connected to the inner RDL structure 3900 . The capacitor wafer 3800 may be disposed on the inner RDL structure 3900 spaced apart from the second semiconductor chip 3400 . The capacitor die 3800 may be configured to include a body 3890 composed of a silicon material and a capacitor 3830 formed in the body 3890 . The internal RDL structure 3900 may be provided as an interconnect structure that electrically connects the capacitors 3830 of the capacitor wafer 3800 to the second set of die pads 3410 of the second semiconductor chip 3400 .

FIG. 11 is a cross-sectional view illustrating a capacitor wafer 3800 . FIG. 11 is a cross-sectional view illustrating some components of the capacitor die 3800 shown in FIG. 10 .

Referring to FIGS. 10 and 11 , the capacitor die 3800 may include capacitors 3830 formed on the surface of the body 3890 of the capacitor die 3800 . The capacitor 3830 may be configured to include a first electrode plate 3832 , a dielectric layer 3833 and a second electrode plate 3834 . The first electrode plate 3832 may be formed on the body 3890 of the capacitor wafer 3800 , the dielectric layer 3833 may be formed on the first electrode plate 3832 , and the second electrode plate 3834 may be formed on the dielectric layer 3833 . The body 3890 of the capacitor wafer 3800 may have a surface that provides concave trenches 3839 . The first electrode plate 3832 , the dielectric layer 3833 and the second electrode plate 3834 may further extend into the trenches 3839 . The effective overlapping area between the first electrode plate 3832 and the second electrode plate 3834 may be increased due to the presence of the trench 3839, thereby increasing the capacitance value of the capacitor 3830.

The first insulating layer 3831 may be disposed between the body 3890 of the capacitor wafer 3800 and the first electrode plate 3832 to insulate the body 3890 and the first electrode plate 3832 . Also, a second insulating layer 3837 may be additionally formed to cover the capacitor 3830 . The capacitor 3830 may further include a first electrode 3835 penetrating the second insulating layer 3837 to be electrically connected to the first electrode plate 3832 . In addition, the capacitor 3830 may further include a second electrode 3836 penetrating the second insulating layer 3837 to be electrically connected to the second electrode plate 3834 .

FIG. 12 is a plan view illustrating the first inner RDL pattern 3910 and the second inner RDL pattern 3920 of the stacked module 3400S. FIG. 12 is a plan view illustrating a first inner RDL pattern 3910 and a second inner RDL pattern 3920 constituting the inner RDL structure 3900 of FIG. 10 . For ease and convenience of illustration, the first inner RDL pattern 3910 and the second inner RDL pattern 3920 in FIG. 12 are illustrated as including only connecting the second set of die pads 3410 to the first electrode 3835 and the second electrode 3836 part without covering the part of the second group of die pads 3410 and the first electrode 3835 and the second electrode 3836 .

Referring to FIGS. 10 , 11 and 12 , the inner RDL structure 3900 may include a first RDL pattern 3910 and a second RDL pattern 3920 . The first inner RDL pattern 3910 may be a conductive pattern extending to connect the first electrode 3835 of the capacitor 3830 to the first die pad 3411 in the second group of die pads 3410 . The second inner RDL pattern 3920 may be a conductive pattern extending to connect the second electrode 3836 of the capacitor 3830 to the second die pad 3413 in the second group of die pads 3410 . The first die pad 3411 may be provided as a power supply terminal for applying a power supply voltage to the second semiconductor chip 3400 . The second die pad 3413 may be provided as a ground terminal for supplying a ground voltage to the second semiconductor chip 3400 .

According to the above description, the first electrode 3835 of the capacitor 3830 may be connected to the electrical path for applying the power supply voltage to the second semiconductor chip 3400, and the second electrode 3836 of the capacitor 3830 may be connected to the electric path for supplying the ground voltage to the second semiconductor chip 3400 Another electrical path for chip 3400. In this way, since the capacitor 3830 is coupled between the power terminal and the ground terminal, the capacitor 3830 may function as a decoupling capacitor of the second semiconductor chip 3400 . Therefore, the capacitor 3830 can reduce noise when the second semiconductor chip 3400 operates.

When the first RDL pattern 3910 and the second RDL pattern 3920 are formed, the overlapping pads 3930 may be formed to overlap the third die pads 3412 . The overlapping pads 3930 may be conductive pads formed simultaneously with the first inner RDL pattern 3910 and the second inner RDL pattern 3920 . The inner RDL structure 3900 may further include a first insulating layer 3941 disposed between the second semiconductor chip 3400 and the first and second RDL patterns 3910 and 3920 so that the first RDL patterns 3910 and the second The RDL pattern 3920 is insulated from the second semiconductor chip 3400 . The inner RDL structure 3900 may further include a second insulating layer 3942 formed to cover the first RDL pattern 3910 and the second RDL pattern 3920 .

Referring again to FIG. 10 , the capacitor wafer 3800 may be disposed on the first semiconductor chip 3300 to completely overlap a portion of the first semiconductor chip 3300 . The stacked module 3400S may be disposed on the first semiconductor chip 3300 . If the stacked module 3400S does not include the capacitor die 3800 , the space occupied by the capacitor die 3800 may be filled with an encapsulant material, eg, the inner encapsulant 3750 or the outer encapsulant 3700 . In this case, when the semiconductor package 30 is heated or cooled, the encapsulant material filling the space of the capacitor wafer 3800 may expand or contract relatively more than the first semiconductor chip 3300 and the second semiconductor chip 3400 . This is because the encapsulant material includes a polymer component, and the polymer component has a relatively high thermal expansion coefficient compared to the silicon material corresponding to the main components of the first semiconductor chip 3300 and the second semiconductor chip 3400 . Therefore, if the stacked module 3400S includes the encapsulant material instead of the capacitor die 3800, the semiconductor package 30 may be easily warped. However, according to the present embodiment, the stacked module 3400S includes the capacitor wafer 3800 to reduce the amount of encapsulant material. Therefore, warpage of the semiconductor package 30 can be suppressed or prevented.

13 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one of a system-in-package (SiP) and a semiconductor package according to an embodiment. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data and read out the stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one SiP or at least one semiconductor package according to an embodiment.

The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that stored data or stored data is read out in response to a read/write request from the host 7830 .

14 is a block diagram illustrating an electronic system 8710 including at least one of a SiP and a semiconductor package according to an embodiment. The electronic system 8710 may include a controller 8711 , an input/output unit 8712 and a memory 8713 . The controller 8711, the input/output unit 8712, and the memory 8713 may be coupled to each other through a bus 8715 that provides a data movement path.

In embodiments, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one of a SiP and a semiconductor package according to an embodiment of the present disclosure. The input/output unit 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 may store data and/or commands and the like to be executed by the controller 8711 .

Memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory can be installed into an information processing system such as a mobile terminal or a desktop computer. Flash memory may constitute a solid state disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from the communication network. The interface 8714 may be of wired type or wireless type. For example, interface 8714 may include an antenna, or a wired or wireless transceiver.

The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system .

If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used to use CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division) Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution) or Wibro (Wireless Broadband Internet) technology.

Embodiments of the present disclosure have been disclosed for purposes of illustration. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the appended claims.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of US Patent Application No. 16/665970, filed on October 28, 2019, and claims priority to Korean Patent Application No. 10-2019-0021453, filed on February 22, 2019, and Priority of Korean Patent Application No. 10-2020-0013339 filed on Feb. 4, 2020.

Claims (10)

1. A semiconductor package, comprising:

an external redistribution line (RDL) structure;

a first semiconductor chip disposed on the external RDL structure;

a stacked module stacked on the first semiconductor chip such that a part of the stacked module protrudes laterally from a side surface of the first semiconductor chip in a plan view; and

a bridge wafer laminated on the outer RDL structure to support a tab of the laminated module and configured to include a conductive via electrically connecting the laminated module to the outer RDL structure,

wherein the laminated module includes:

an internal RDL structure;

a second semiconductor chip disposed on the internal RDL structure such that a chip pad of the second semiconductor chip is electrically connected to the internal RDL structure;

a capacitor wafer disposed on the internal RDL structure spaced apart from the second semiconductor chip and configured to include a capacitor electrically connected to the chip pad through the internal RDL structure; and

an internal sealant formed on the internal RDL structure to cover the second semiconductor chip and the capacitor wafer.

2. The semiconductor package of claim 1, wherein the capacitor die is positioned to overlap the first semiconductor chip.

3. The semiconductor package of claim 1, wherein the capacitor comprises:

a first electrode plate formed on the body of the capacitor wafer;

a dielectric layer formed on the first electrode plate;

a second electrode plate formed on the dielectric layer; and

first and second electrodes connected to the respective first and second electrode plates.

4. The semiconductor package according to claim 3,

wherein the capacitor wafer comprises a body having a surface providing a trench; and is

Wherein the first and second electrode plates and the dielectric layer extend into the trench.

5. The semiconductor package of claim 4, wherein the body of the capacitor die is comprised of a silicon material.

6. The semiconductor package of claim 3, wherein the internal RDL structure comprises:

a first inner RDL pattern extending to connect the first electrode to a first one of the chip pads, wherein the first chip pad is a power supply terminal for applying a power supply voltage to the second semiconductor chip; and

a second inner RDL pattern extending to connect the second electrode to a second one of the chip pads, wherein the second chip pad is a ground terminal for applying a ground voltage to the second semiconductor chip.

7. The semiconductor package according to claim 1,

wherein the second semiconductor chip includes a memory semiconductor chip storing data; and is

Wherein the first semiconductor chip comprises a system-on-chip (SoC) in communication with the second semiconductor chip to receive or output data.

8. The semiconductor package of claim 1, further comprising: an adhesive layer disposed between the stacked module and the first semiconductor chip to attach the stacked module to the first semiconductor chip.

9. The semiconductor package of claim 1, wherein the conductive via is formed vertically through a body of the bridge wafer.

10. The semiconductor package of claim 1, further comprising: an external sealant disposed on the external RDL structure to cover the first semiconductor chip, the bridge wafer, and the stacked module.

Images