CN111613596B - Package structure and method for forming the same - Google Patents
Package structure and method for forming the same Download PDFInfo
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- CN111613596B CN111613596B CN201910137550.0A CN201910137550A CN111613596B CN 111613596 B CN111613596 B CN 111613596B CN 201910137550 A CN201910137550 A CN 201910137550A CN 111613596 B CN111613596 B CN 111613596B
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- 238000001465 metallisation Methods 0.000 claims abstract description 154
- 238000002161 passivation Methods 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 65
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 230000001154 acute effect Effects 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 11
- 238000009826 distribution Methods 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 3
- 208000033999 Device damage Diseases 0.000 abstract description 14
- 238000001125 extrusion Methods 0.000 abstract description 3
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- 239000000956 alloy Substances 0.000 description 14
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- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 239000004065 semiconductor Substances 0.000 description 9
- 238000005530 etching Methods 0.000 description 6
- 239000011368 organic material Substances 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 229910017944 Ag—Cu Inorganic materials 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
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- 239000004332 silver Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
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- 238000005336 cracking Methods 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000002648 laminated material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11005—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for aligning the bump connector, e.g. marks, spacers
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A package structure and a method of forming the same, the package structure comprising: the surface of the substrate is provided with an electrode, a patterned passivation layer is formed on the substrate, and a window for exposing the electrode is formed in the passivation layer; an under bump metallization layer on the exposed electrode of the window and also covering the window sidewall and a portion of the top of the passivation layer, the under bump metallization layer comprising a plurality of discrete sub-metallization layers; a conductive bump overlying the under bump metallization layer. Through setting up the UBM layer into a plurality of sub-metallization layer structures of separating to when electrically conductive lug receives the extrusion, make the clearance between the sub-metallization layer of separating decompose pressure jointly, reduce the pressure that the UBM layer bore, and then reduce the stress of passivation layer and the juncture on UBM layer, avoid passivation layer and/or UBM layer to appear the device damage that the crack caused, improve the performance of device.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a packaging structure and a forming method thereof.
Background
In forming a semiconductor wafer, integrated circuit devices, such as transistors, are first formed on a surface of a semiconductor substrate. An interconnect structure is then formed over the integrated circuit device. Metal bumps are formed on the surface of the semiconductor chip so as to contact the semiconductor circuit device.
In a typical metal bump forming process, an Under Bump Metallization (UBM) layer is first formed to electrically connect metal pads on a wafer, and then a metal bump is formed on the UBM layer, and after the metal bump is formed, an unnecessary portion of the UBM layer is removed by wet etching.
The performance of the packaged device formed by the existing packaging method needs to be improved.
Disclosure of Invention
The invention provides a packaging structure and a forming method thereof, which are used for improving the performance of a packaged device.
To solve the above problems, the present invention provides a package structure, including: the surface of the substrate is provided with an electrode, a patterned passivation layer is formed on the substrate, and a window for exposing the electrode is formed in the passivation layer; an under bump metallization layer on the exposed electrode of the window and also covering the window sidewall and a portion of the top of the passivation layer, the under bump metallization layer comprising a plurality of discrete sub-metallization layers; a conductive bump overlying the under bump metallization layer.
Correspondingly, the invention also provides a forming method of the packaging structure, which comprises the following steps: providing a substrate, wherein an electrode is formed on the surface of the substrate; forming a patterned passivation layer on the substrate, wherein a window for exposing the electrode is formed in the passivation layer; forming an under bump metallization layer on the electrode exposed by the window, on the window sidewalls and on a portion of the top of the passivation layer, wherein the under bump metallization layer comprises a plurality of discrete sub-metallization layers; forming a conductive bump overlying the underbump metallization layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
embodiments of the present invention provide a package structure and a method for forming the same, wherein the Under Bump Metallization (UBM) layer includes a plurality of discrete sub-metallization layers. Through setting up the UBM layer into a plurality of sub-metallization layer structures of separating to when electrically conductive lug receives the extrusion, make the clearance between the sub-metallization layer of separating decompose pressure jointly, reduce the pressure that the UBM layer bore, and then reduce the stress of passivation layer and the juncture on UBM layer, avoid passivation layer and/or UBM layer to appear the device damage that the crack caused, improve the performance of device.
Drawings
FIG. 1 is a schematic diagram of a package structure;
fig. 2 to fig. 3 are schematic structural diagrams of a package structure according to an embodiment of the invention;
FIG. 4 is a top view of a UBM layer in another embodiment of the present invention;
fig. 5 to 11 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a package structure of the invention.
Detailed Description
As is known from the background art, the performance of the packaged device formed by the conventional packaging method needs to be improved.
Referring to fig. 1, there is shown a structural diagram of a packaged device formed by a packaging method, wherein a passivation layer 101 has a window W' thereon to expose an electrical connection structure 102 under the passivation layer, a UBM layer 103 covering the window is disposed in the window, and a metal bump 104 is disposed on the UBM layer 103. When the metal bump 104 is pressed in the subsequent process, the stress applied to the boundary (such as the dashed-line frame in fig. 1) between the passivation layer 101 and the UBM layer 103 is correspondingly increased, which is very likely to cause cracks in the passivation layer 101 and/or the UBM layer 103, thereby causing device damage and further causing device performance degradation.
In order to solve the technical problem, an embodiment of the present invention provides a package structure and a forming method thereof, where the package structure includes: the surface of the substrate is provided with an electrode, a patterned passivation layer is formed on the substrate, and a window for exposing the electrode is formed in the passivation layer; an under bump metallization layer on the exposed electrode of the window and also covering the window sidewall and a portion of the top of the passivation layer, the under bump metallization layer comprising a plurality of discrete sub-metallization layers; a conductive bump overlying the under bump metallization layer.
Wherein the UBM layer comprises a plurality of discrete sub-metallization layers. Through setting up the UBM layer into a plurality of sub-metallization layer structures of separating to when electrically conductive lug receives the extrusion, make the clearance between the sub-metallization layer of separating decompose pressure jointly, reduce the pressure that the UBM layer bore, and then reduce the stress of passivation layer and the juncture on UBM layer, avoid passivation layer and/or UBM layer to appear the device damage that the crack caused, improve the performance of device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to fig. 3 are schematic structural diagrams of a package structure according to an embodiment of the invention, wherein fig. 2 is a cross-sectional view of the package structure according to the embodiment of the invention, and fig. 3 is a top view of a bump bottom metallization layer in fig. 2.
The package structure includes: the manufacturing method comprises the following steps of forming a substrate 200, wherein an electrode 202 is formed on the surface of the substrate 200, a patterned passivation layer 201 is formed on the substrate 200, and a window W for exposing the electrode 202 is formed in the passivation layer 201; an under bump metallization layer 203 on the electrode 202 exposed by the window W and further covering the sidewalls of the window W and a portion of the top of the passivation layer 201, the under bump metallization layer 203 comprising a plurality of discrete sub-metallization layers; a conductive bump 204 covering the underbump metallization layer 203.
In the package structure of this embodiment, the under bump metallization layer 203 includes a plurality of discrete sub-metallization layers, and by configuring the UBM layer 203 as a plurality of discrete sub-metallization layer structures, when the conductive bump 204 is pressed, a gap between the discrete sub-metallization layers jointly decomposes pressure, reduces pressure borne by the UBM layer 203, further reduces stress at a boundary between the passivation layer 201 and the UBM layer 203, avoids device damage caused by cracks in the passivation layer 201 and/or the UBM layer 203, and improves performance of the device.
The base 200 may include a substrate, active devices, and interconnect structures (not shown).
The substrate may be a semiconductor substrate such as silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like. Alternatively, the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates can be selected by those skilled in the art according to actual needs. The active device is a functional device formed on the surface of the substrate, and may be specifically a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, or the like, and is formed on the surface of the substrate through a corresponding semiconductor process. The interconnect structure is formed over the substrate and the active device for electrically connecting the active device. The interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD), and electrically connects the active devices by forming conductive features (e.g., conductive lines and vias of copper, aluminum, tungsten, etc.) to form functional circuitry within the substrate 200.
An electrode 202 is formed on the surface of the substrate 200, and in particular, the electrode 202 is formed on an interconnection structure for electrically connecting active devices through the interconnection structure in the substrate 200.
The electrode 202 may be made of a metal material such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), or tungsten (W), or an alloy material of a plurality of metal materials, and may have a single-layer structure of one material or a stacked-layer structure of a plurality of layers.
A patterned passivation layer 201 is further formed on the substrate 200, and the passivation layer 201 is used for protecting the substrate 200 and exposing the electrode 202. Specifically, the passivation layer 201 exposes the electrode 202 through the window W. In the present embodiment, a passivation layer 201 covers the interconnect structure of the substrate 200 and covers the edge portion of the electrode 202. The passivation layer 201 may be formed of a non-organic material such as silicon oxide, silicon nitride, or silicon oxynitride, or may be formed of an organic material such as polyimide, and in this embodiment, the passivation layer 201 is a photoresist material among organic materials.
In this embodiment, at the edge position of the window W, the top corner of the sidewall of the passivation layer 201 is rounded (not shown in the figure). The top angle of the side wall of the passivation layer 201 is set to be a round angle, so that the passivation layer and/or the UBM layer which are possibly caused by the sharp angle are prevented from being cracked, and the device damage caused by the cracks is avoided, and the performance of the device is improved.
In addition, at the edge position of the window W, the inclination angle of the sidewall of the passivation layer 201 is an acute angle, specifically, in this embodiment, the inclination angle of the passivation layer 201 may be 15 ° to 75 °, for example, 30 °, 45 ° or 60 °, so that the passivation layer structure is more stable, and further, cracks are not easily formed, and the performance of the device is improved. The passivation layer inclination angle refers to an included angle between a passivation layer inclined plane and a passivation layer bottom surface (in the figure, a surface close to the conductive bump 204 is a top surface, and a surface close to the substrate 200 is a bottom surface).
The Under Bump Metallization (UBM) layer 203 is used to electrically connect with the interconnect structure in the substrate 200 through the electrode 202, thereby electrically connecting the active devices in the substrate 200.
Wherein the UBM layer 203 is located on the electrode 202 exposed by the window W and also covers the sidewall of the window W and a part of the top of the passivation layer 201, and the UBM layer 203 comprises a plurality of discrete sub-metallization layers.
By arranging the UBM layer 203 into a plurality of discrete sub-metallization layer structures, when the conductive bump 204 is extruded, the pressure is jointly decomposed by gaps between the discrete sub-metallization layers, the pressure born by the UBM layer 203 is reduced, the stress at the junction of the passivation layer 201 and the UBM layer 203 is further reduced, the device damage caused by cracks of the passivation layer 201 and/or the UBM layer 203 is avoided, and the performance of the device is improved.
Specifically, the UBM layer 203 includes: a plurality of discrete first sub-metallization layers 2031 on the electrodes 202 exposed by the windows; the second sub-metallization layer 2032 is a unitary structure surrounding the plurality of discrete first sub-metallization layers 2031 and also covering the sidewalls of the window W and a portion of the top of the passivation layer 201.
The UBM layer 203 includes a plurality of discrete first sub-metallization layers 2031 disposed in the window W for increasing pressure shared by the discrete sub-metallization layers in the window W, and the second sub-metallization layer 2032 having an integral structure for forming a stable structure and protecting the passivation layer 201 on the sidewall of the window W.
In the UBM layer 203, the distribution rule of the plurality of first sub-metallization layers 2031 within the window W includes: the closer to the window center O, the larger the spacing between adjacent first sub-metallization layers 2031. Considering that the conductive bump 204 is mostly a hemisphere, when the conductive bump is squeezed, the pressure of the portion corresponding to the center O of the window is larger, and the larger the distance between the adjacent first sub-metallization layers 2031 is, the larger the pressure is shared correspondingly. Obviously, by adopting the distribution rule, the pressure shared by the first sub-metallization layer 2031 can be effectively increased, the pressure borne by the second sub-metallization layer 2032 can be reduced, and further, the stress at the boundary between the passivation layer and the UBM layer can be reduced, the device damage caused by cracks in the passivation layer 201 and/or the UBM layer 203 can be avoided, and the performance of the device can be improved.
In this embodiment, the coverage area of the first sub-metallization layer 2031 is larger as the first sub-metallization layer 2031 is closer to the window center O.
The inclination angle of the sidewall of the second sub-metallization layer 2032 facing away from the first sub-metallization layer 2031 on the surface of the passivation layer 201 is acute. Specifically, in this embodiment, the inclination angle may be 15 ° to 75 °, for example, 30 °, 45 °, or 60 °, so that the second sub-metallization layer is more stable, and can bear a larger pressure, thereby preventing the second sub-metallization layer from being damaged, and improving the performance of the device. The tilt angle of the second sub-metallization layer refers to an included angle between the inclined surface of the second sub-metallization layer and the bottom surface of the second sub-metallization layer (in the figure, a surface close to the conductive bump 204 is a top surface, and a surface close to the substrate 200 is a bottom surface).
The UBM layer 203 may be one or more of chromium (Cr), copper (Cu), titanium (Ti), nickel (Ni), or tantalum (Ta), and when a plurality of materials are selected, the UBM layer 203 may be a laminated structure, and when a laminated material is selected, each of the layers has good physical property matching properties, including having similar thermal expansion coefficients and conductivity, and the like, and no eutectic phenomenon occurs between adjacent layers, so as to ensure that the UBM layer 203 forms a firm physical connection between the substrate 200 and a subsequent conductive structure.
In this embodiment, the UBM layer 203 is a stacked structure including a copper layer and a nickel layer, wherein the nickel layer is located on the copper layer and has a thickness of 0.5 μm to 20 μm, and optionally, the thickness of the UBM layer 203 may be 4 μm, 9 μm, 14 μm, or 18 μm.
On the UBM layer 203, a conductive bump 204 is further provided for forming an electrical connection with the UBM layer 203.
Specifically, the conductive bump 204 covers the UBM layer 203.
Compared with a whole UBM layer, the UBM layer 203 below the conductive bump 204 is provided with a plurality of discrete sub-metallization layers in the window in the embodiment, so that the contact area between the conductive bump 204 and the UBM layer 203 is larger, the conductivity is better, and the performance of the device is further improved.
In the present embodiment, the conductive bump 204 may be a solder bump, which may be formed of an Sn-Ag alloy, an Sn-Cu alloy, an Sn-Ag-Cu alloy, or the like. Alternatively, in other embodiments, the conductive bump 204 may also be a copper bump, and the surface of the copper bump is covered with a cap layer (cap layer) composed of a nickel layer, a Sn-Ag alloy layer, a Sn-Cu alloy layer, a Sn-Ag-Cu alloy layer, a palladium layer or a silver layer, which can be selected by those skilled in the art based on the disclosure of the present invention.
In this embodiment, the UBM layer 203 is provided with a plurality of discrete first sub-metallization layers 2031 in the window W, so that the pressure shared by the discrete sub-metallization layers in the window W is increased, the pressure at the edge of the window W is reduced, and the second sub-metallization layers 2032 in an integrated structure can form a stable structure, thereby avoiding device damage caused by cracks in the passivation layer 201 and/or the UBM layer 203, and improving the performance of the device.
Moreover, compared with a whole UBM layer, in this embodiment, the UBM layer 203 under the conductive bump 204 is disposed as a plurality of discrete sub-metallization layers in the window, so that the contact area between the conductive bump 204 and the UBM layer 203 is larger, the conductivity is better, and the performance of the device is further improved.
In another embodiment of the present invention, a package structure is provided, and referring to fig. 4, a top view of a UBM layer in the package structure according to another embodiment of the present invention is shown.
The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the arrangement of the first sub-metallization layers 2031 is different.
Specifically, in this embodiment, the first sub-metallization layers 2031 are arranged in a matrix along the vertical row direction and the vertical column direction, the length of the first sub-metallization layers 2031 along the row direction (e.g., the Y direction in fig. 4) is greater than or equal to 20 μm, and along the direction in which the window center O points to the window sidewall, the length Y2 of the first sub-metallization layers 2031 along the row direction in any row gradually decreases according to a first preset proportion, where the first preset proportion is 95% to 60%, in this embodiment, the first preset proportion is 90%, in other embodiments, the first preset proportion may also be 80% or 70%, or the first preset proportion may also gradually change according to a corresponding rule.
In any row of the first sub-metallization layers 2031, the distance between adjacent first sub-metallization layers 2031 in the row direction is a first value y1, and the length of the first sub-metallization layer 2031 on the side of the adjacent first sub-metallization layer 2031 close to the window sidewall in the row direction is a second value y2, where the first value is equal to the second value, that is, y1 is y 2.
In this embodiment, the width of the first sub-metallization layer 2031 in the column direction (e.g., the X direction in fig. 4) is greater than or equal to 20 μm, and the width of the first sub-metallization layer 2031 in any column in the column direction gradually decreases according to a second predetermined ratio in the direction from the window center O to the window sidewall, where the second predetermined ratio is 95% to 60%. In this embodiment, the second preset proportion is 90%, in other embodiments, the second preset proportion may also be 80% or 70%, or the second preset proportion may also gradually change according to a corresponding rule.
In any column of the first sub-metallization layers 2031, a distance between adjacent ones of the first sub-metallization layers 2031 in the column direction is a third value x1, a length of a first sub-metallization layer of the adjacent first sub-metallization layers on a side close to the window sidewall in the column direction is a fourth value x2, the third value is equal to the fourth value, and x1 is equal to x 2.
Wherein a pitch y1 of adjacent first sub-metallization layers 2031 along the row direction is greater than or equal to 20 μm, and a pitch x1 of adjacent first sub-metallization layers 2031 along the column direction is greater than or equal to 20 μm. Also, in the present embodiment, the space (white portion in the figure) between adjacent rows/columns also extends into the second sub-metallization layer to maximally share the pressure.
Specifically, the length a1 in the column direction of the space extending in the X-axis direction and passing through the window center O is (d/2-40) μm, where d is the radius of the window W. In the direction that the window center O points to the window side wall, the lengths of other intervals parallel to the interval gradually decrease according to a third preset proportion, wherein the third preset proportion is 95-60%. In other embodiments, the third preset proportion may also be 80% or 70%, or the third preset proportion may also gradually change according to a corresponding rule.
The length b1 in the row direction of the space extending in the Y-axis direction and passing through the window center O is (d/2-40) μm, where d is the radius of the window W. And in the direction of pointing to the side wall of the window along the center O of the window, the lengths of other intervals parallel to the interval are gradually reduced according to a fourth preset proportion, and the third preset proportion is 95-60%. In other embodiments, the fourth preset proportion may also be 80% or 70%, or the fourth preset proportion may also gradually change according to a corresponding rule.
Through the arrangement, the pressure shared by the sub-metallization layers in the window W is increased to the greatest extent, and the pressure at the edge of the window W is reduced, so that device damage caused by cracks of the passivation layer 201 and/or the UBM layer 203 is avoided, and the performance of the device is improved.
Referring to fig. 5 to 11, an embodiment of the invention further provides a method for forming a package structure. The method comprises the following steps:
referring to fig. 5, a substrate 200 is provided, and an electrode 202 is formed on a surface of the substrate 200.
In this embodiment, the base 200 may include a substrate, active devices, and an interconnect structure (not shown).
The substrate may be a semiconductor substrate such as silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like. Alternatively, the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates can be selected by those skilled in the art according to actual needs. The active device is a functional device formed on the surface of the substrate, and may be specifically a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, or the like, and is formed on the surface of the substrate through a corresponding semiconductor process. The interconnect structure is formed over the substrate and the active device for electrically connecting the active device. The interconnect structure may include inter-layer dielectric (ILD) and/or inter-metal dielectric (IMD), and electrically connects the active devices by forming conductive features (e.g., conductive lines and vias of copper, aluminum, tungsten, etc.) to form functional circuitry within the substrate 200.
An electrode 202 is formed on the surface of the substrate 200, and in particular, the electrode 202 is formed on an interconnection structure for electrically connecting active devices through the interconnection structure in the substrate 200.
The electrode 202 may be made of a metal material such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), nickel (Ni), or tungsten (W), or an alloy material of a plurality of metal materials, and may have a single-layer structure of one material or a stacked-layer structure of a plurality of layers. In this embodiment, the electrode 202 may be formed by deposition.
Referring to fig. 6, a patterned passivation layer 201 is formed on the substrate 200, and a window exposing the electrode 202 is formed in the passivation layer 201.
The passivation layer 201 is used to protect the substrate 200 and expose the electrode 202.
Specifically, the passivation layer 201 exposes the electrode 202 through the window. In the present embodiment, a passivation layer 201 covers the interconnect structure of the substrate 200 and covers the edge portion of the electrode 202. The passivation layer 201 may be formed of a non-organic material such as silicon oxide, silicon nitride, or silicon oxynitride, or may be formed of an organic material such as polyimide, and in this embodiment, the passivation layer 201 is a photoresist material among organic materials.
In this embodiment, the specific steps of forming the patterned passivation layer 201 may include: forming a passivation layer covering the substrate 200 and the electrode 202, removing a portion of the passivation layer above the electrode, forming a window in the passivation layer exposing the electrode, and leaving the remaining passivation layer as the passivation layer 201.
Specifically, when the passivation layer is made of a photoresist material, a photolithography process may be used to remove a portion of the passivation material layer above the electrode, and in the step of removing a portion of the passivation material layer above the electrode, the method further includes forming a passivation layer sidewall with a rounded top angle at an edge position of the window. Specifically, photoetching parameters are adjusted, so that the top angle of the passivation layer at the opening position of the window is a round angle. The top angle of the passivation layer at the opening position of the window can be a round angle through the proportion of the developing solution, the developing time and/or the exposure time.
In this embodiment, at the edge position of the window, the top angle of the passivation layer 201 is a rounded corner (not shown in the figure), so as to avoid the passivation layer and/or the UBM layer from cracking and device damage caused by cracking possibly caused by the sharp corner, and improve the performance of the device.
Further, in the step of removing the passivation material layer above a portion of the electrode, the method further includes: and forming a passivation layer side wall with an acute inclination angle at the edge position of the window. Specifically, the photoetching parameters are adjusted, so that the inclination angle of the passivation layer at the edge position of the window on the surface of the electrode is an acute angle. And adjusting the proportion of a developing solution, the developing time and/or the exposure time to enable the inclination angle of the passivation layer on the surface of the electrode at the edge position of the window to be an acute angle.
At the edge position of the window, the inclination angle of the passivation layer 201 on the surface of the electrode 202 is an acute angle, and in this embodiment, the inclination angle of the passivation layer 201 may be 15 ° to 75 °, for example, 30 °, 45 °, or 60 °, so that the passivation layer structure is more stable, and further cracks are not easily formed, and the performance of the device is improved. The passivation layer inclination angle refers to an included angle between a passivation layer inclined plane and a passivation layer bottom surface (in the figure, a surface close to the conductive bump 204 is a top surface, and a surface close to the substrate 200 is a bottom surface).
Referring to fig. 7 to 10, an under bump metallization layer 203 is formed on the exposed electrodes of the windows, on the sidewalls of the windows and on a portion of the top of the passivation layer, wherein the under bump metallization layer 203 comprises a plurality of discrete sub-metallization layers.
The Under Bump Metallization (UBM) layer 203 is used to electrically connect with the interconnect structure in the substrate 200 through the electrode 202, thereby electrically connecting the active devices in the substrate 200.
By arranging the UBM layer 203 into a plurality of discrete sub-metallization layer structures, when the conductive bump 204 is extruded, the pressure is jointly decomposed by gaps between the discrete sub-metallization layers, the pressure born by the UBM layer 203 is reduced, the stress at the junction of the passivation layer 201 and the UBM layer 203 is further reduced, the device damage caused by cracks of the passivation layer 201 and/or the UBM layer 203 is avoided, and the performance of the device is improved.
Specifically, the step of forming the under bump metallization layer 203 includes:
referring to fig. 7, a patterned first mask layer 210 is formed on the electrode exposed by the window, a plurality of mask openings are formed in the first mask layer 210, and the mask openings 210 expose a portion of the electrode 202.
Specifically, the patterned first mask layer 210 may be formed using a photolithographic patterning process. The exposed portion of the first mask 210 is used to form an underbump metallization layer, wherein the plurality of mask openings are used to form sub-metallization layers within the windows.
The distribution rule of the mask openings in the window comprises: the closer to the center of the window, the greater the spacing between adjacent mask openings. By adopting the distribution rule, the formed sub-metallization layer can effectively increase the pressure shared by the sub-metallization layer, so that the stress at the junction of the passivation layer and the UBM layer is reduced, the device damage caused by cracks of the passivation layer 201 and/or the UBM layer 203 is avoided, and the performance of the device is improved.
It should be noted that, the specific arrangement of the mask openings in the windows may refer to the description in the embodiment of the package structure of the present invention, and is not described herein again.
Referring to fig. 8, an under bump metallization layer 220 is formed using the first mask layer 210 as a mask.
Specifically, the under bump metallization layer 220 may be formed by a deposition process.
The UBM layer 203 may be one or more of chromium (Cr), copper (Cu), titanium (Ti), nickel (Ni), or tantalum (Ta), and when a plurality of materials are selected, the UBM layer 203 may be a laminated structure, and when a laminated material is selected, each of the layers has good physical property matching properties, including having similar thermal expansion coefficients and conductivity, and the like, and no eutectic phenomenon occurs between adjacent layers, so as to ensure that the UBM layer 203 forms a firm physical connection between the substrate 200 and a subsequent conductive structure.
In this embodiment, the UBM layer 203 is a stacked structure including a copper layer and a nickel layer, wherein the nickel layer is located on the copper layer and has a thickness of 0.5 μm to 20 μm, and optionally, the thickness of the UBM layer 203 may be 4 μm, 9 μm, 14 μm, or 18 μm.
Referring to fig. 9, the first mask layer 210 is removed.
Specifically, the first mask layer 210 may be removed by an etching or stripping process.
Next, referring to fig. 10, a portion of the under bump metallization layer 220 on the passivation layer 201 is removed, and the under bump metallization layer 220 within the window, on the sidewalls of the window, and on a portion of the top of the passivation layer 201 is left, forming a UBM layer 203.
Specifically, a wet etching process may be used to remove a portion of the under bump metallization material layer on the passivation layer 201, so as to form the UBM layer 203. In the step of removing the under bump metallization layer 220 on the passivation layer 201 by etching, an etching parameter may be adjusted to form an inclined plane with an acute inclination angle on a sidewall of the UBM layer 203 facing away from the window. Specifically, an inclined plane with an acute inclination angle is formed on the side wall of the UBM layer 203 away from the window by adjusting the proportion of etching liquid, the etching speed and/or the etching time.
The inclination angle of the side wall of the UBM layer 203 facing away from the window is an acute angle, specifically, the acute angle may be 15 ° to 75 °, for example, 30 °, 45 °, or 60 °, so that the UBM layer 203 therein is more stable in structure, and can bear a larger pressure, thereby preventing cracks from being formed and improving the performance of the device. The inclination angle of the UBM layer refers to an angle between an inclined surface of the UBM layer and a bottom surface of the UBM layer (in the figure, a surface close to the conductive bump 204 is a top surface, and a surface close to the substrate 200 is a bottom surface).
It should be noted that this step may also be performed after the step of forming the conductive bump covering the UBM layer 203, and then the conductive bump may be directly used as a mask to directly remove the under bump metallization material 220 layer exposed by the conductive bump to form the under bump metallization layer 203, so as to simplify the process.
Next, referring to fig. 11, a conductive bump 204 is formed overlying the underbump metallization layer 203.
In the present embodiment, the conductive bump 204 may be a solder bump, which may be formed of an Sn-Ag alloy, an Sn-Cu alloy, an Sn-Ag-Cu alloy, or the like. Alternatively, in other embodiments, the conductive bump 204 may also be a copper bump, and the surface of the copper bump is covered with a cap layer (cap layer) composed of a nickel layer, a Sn-Ag alloy layer, a Sn-Cu alloy layer, a Sn-Ag-Cu alloy layer, a palladium layer or a silver layer, which can be selected by those skilled in the art based on the disclosure of the present invention.
The specific steps of forming the conductive bump 204 covering the under bump metallization layer 203 include: and forming a third mask layer exposing the bump bottom metallization layer, depositing a conductive material layer on the third mask layer, removing the third mask layer, and forming the conductive bump by adopting a reflow process.
Compared with a whole UBM layer, the UBM layer 203 below the conductive bump 204 is provided with a plurality of discrete sub-metallization layers in the window in the embodiment, so that the contact area between the conductive bump 204 and the UBM layer 203 is larger, the conductivity is better, and the performance of the device is further improved.
In the package structure of the method in this embodiment, the under bump metallization 203 in the window includes a plurality of discrete sub-metallization layers, and by configuring the UBM layer 203 as a plurality of discrete sub-metallization layer structures, when the conductive bump 204 is pressed, a pressure is jointly decomposed by a gap between the discrete sub-metallization layers, so as to reduce a pressure borne by the UBM layer 203, further reduce a stress at a boundary between the passivation layer 201 and the UBM layer 203, avoid a device damage caused by a crack occurring in the passivation layer 201 and/or the UBM layer 203, and improve a performance of the device.
It should be noted that the package structure may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. The specific descriptions of the package structure and the forming method thereof in this embodiment may be referred to each other, and are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A package structure, comprising:
the surface of the substrate is provided with an electrode, a patterned passivation layer is formed on the substrate, and a window for exposing the electrode is formed in the passivation layer;
an under bump metallization layer on the exposed electrode of the window and further covering the window sidewalls and a portion of the top of the passivation layer, the under bump metallization layer comprising a plurality of discrete sub-metallization layers, the under bump metallization layer comprising: a plurality of discrete first sub-metallization layers on the electrodes exposed by the windows; a second sub-metallization layer in a unitary structure surrounding the plurality of discrete first sub-metallization layers and further covering sidewalls of the window and a portion of the top of the passivation layer;
a conductive bump overlying the under bump metallization layer.
2. The package structure of claim 1, wherein a distribution rule of the plurality of first sub-metallization layers within the window comprises:
the closer the window center is, the larger the spacing between adjacent first sub-metallization layers is.
3. The package structure of claim 2, wherein the first sub-metallization layers are arranged in a matrix along perpendicular row and column directions, a length of the first sub-metallization layers along the row direction is greater than or equal to 20 μm, and a length of the first sub-metallization layers along the row direction is gradually smaller according to a first predetermined ratio along a direction from a center of the window to a sidewall of the window, and the first predetermined ratio is 95% to 60%.
4. The package structure of claim 3, wherein a distance between adjacent first sub-metallization layers along the row direction is a first value, a length of a first sub-metallization layer of the adjacent first sub-metallization layers adjacent to the side wall of the window along the row direction is a second value, and the first value is equal to the second value.
5. The package structure of claim 2, wherein the first sub-metallization layers are arranged in a matrix along perpendicular row and column directions, a width of the first sub-metallization layers along the column direction is greater than or equal to 20 μm, and a width of the first sub-metallization layers along the column direction is gradually smaller according to a second predetermined ratio along a direction from a center of the window to a sidewall of the window, and the second predetermined ratio is 95% to 60%.
6. The package structure of claim 5, wherein a distance between adjacent first sub-metallization layers along the column direction is a third value, a length of a first sub-metallization layer of the adjacent first sub-metallization layers adjacent to the side wall of the window along the column direction is a fourth value, and the third value is equal to the fourth value.
7. The package structure of claim 1, wherein a side wall of the second sub-metallization layer facing away from the first sub-metallization layer has an acute inclination angle at a surface of the passivation layer.
8. The package structure of claim 1, wherein a top corner of the passivation layer sidewall is rounded at an edge location of the window.
9. The package structure of claim 1, wherein an inclination of the passivation layer sidewall is acute at an edge position of the window.
10. The package structure of claim 1, wherein the underbump metallization layer comprises a copper layer and a nickel layer on the copper layer.
11. A method for forming a package structure, comprising:
providing a substrate, wherein an electrode is formed on the surface of the substrate;
forming a patterned passivation layer on the substrate, wherein a window for exposing the electrode is formed in the passivation layer;
forming an under bump metallization layer on the electrode exposed by the window, on the window sidewalls and on a portion of the top of the passivation layer, wherein the under bump metallization layer comprises a plurality of discrete sub-metallization layers, the under bump metallization layer comprising: a plurality of discrete first sub-metallization layers on the electrodes exposed by the windows; a second sub-metallization layer in a unitary structure surrounding the plurality of discrete first sub-metallization layers and further covering sidewalls of the window and a portion of the top of the passivation layer;
forming a conductive bump overlying the underbump metallization layer.
12. The method of forming in accordance with claim 11, wherein said forming an underbump metallization layer comprises:
forming a first patterned mask layer on the electrode exposed from the window, wherein a plurality of mask openings are formed in the first mask layer, and part of the electrode is exposed from the mask openings;
forming a bump bottom metallization material layer by taking the first mask layer as a mask;
removing the first mask layer;
and removing part of the under bump metallization material layer on the passivation layer, and reserving the under bump metallization material layer in the window, on the side wall of the window and on part of the top of the passivation layer to form the under bump metallization layer.
13. The method of claim 12, wherein the distribution of the plurality of mask openings within the window comprises:
the closer to the center of the window, the greater the spacing between adjacent mask openings.
14. The method of forming of claim 12, wherein the step of removing a portion of the layer of underbump metallization material on the passivation layer is performed after the step of forming a conductive bump overlying the underbump metallization layer is performed;
the step of removing part of the under bump metallization material layer on the passivation layer comprises:
and removing the bump bottom metallization material layer exposed by the conductive bump to form the bump bottom metallization layer.
15. The method of forming of claim 12, wherein the step of removing the portion of the underbump metallization material layer on the passivation layer further comprises:
and forming an inclined plane with an acute inclination angle on the side wall of the under bump metallization layer, which is away from the window.
16. The method of forming of claim 11, wherein forming a patterned passivation layer on the substrate comprises:
forming a passivation material layer covering the substrate and the electrode;
and removing part of the passivation material layer above the electrode, forming a window exposing the electrode in the passivation material layer, and keeping the rest passivation material layer as the passivation layer.
17. The method of claim 16, wherein the step of removing the passivation layer over the portion of the electrode further comprises: and forming a passivation layer side wall with a rounded vertex angle at the edge position of the window.
18. The method of claim 16, wherein the step of removing the passivation layer over the portion of the electrode further comprises: and forming a passivation layer side wall with an acute inclination angle at the edge position of the window.
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| US6959856B2 (en) * | 2003-01-10 | 2005-11-01 | Samsung Electronics Co., Ltd. | Solder bump structure and method for forming a solder bump |
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| US8916464B2 (en) * | 2008-12-29 | 2014-12-23 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
| US7989356B2 (en) * | 2009-03-24 | 2011-08-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming enhanced UBM structure for improving solder joint reliability |
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| CN1455955A (en) * | 2000-06-28 | 2003-11-12 | 英特尔公司 | Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs |
| JP2013030498A (en) * | 2009-11-12 | 2013-02-07 | Panasonic Corp | Semiconductor device |
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