CN111610676B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN111610676B CN111610676B CN202010568237.5A CN202010568237A CN111610676B CN 111610676 B CN111610676 B CN 111610676B CN 202010568237 A CN202010568237 A CN 202010568237A CN 111610676 B CN111610676 B CN 111610676B
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 230000003071 parasitic effect Effects 0.000 claims abstract description 24
- 238000010586 diagram Methods 0.000 description 18
- 230000005669 field effect Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises: a display area provided with a through hole and a non-display area surrounding the display area; the display area comprises data lines and grid lines which are arranged in a crossing manner; the non-display area comprises a control switch and a driving chip electrically connected with each data line; the data lines of which part is disconnected by the through holes and the data lines of which part is not disconnected by the through holes are electrically connected through the control switches, all the control switches are electrically connected with the driving chip, the control switches are used for storing first data signals provided by the driving chip in parasitic capacitances of the data lines of which the part is disconnected by the through holes when in an on state, the driving chip is used for providing second data signals to the data lines of which the part is not disconnected by the through holes when the control switches are in an off state, and the parasitic capacitances are used for maintaining the data lines of which the part is disconnected by the through holes at the first data signals.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a driving method thereof, and a display device.
Background
Currently, display devices such as mobile phones and tablet computers often need to reserve space for commonly used electronic devices such as front cameras, mechanical keys, fingerprint modules, and the like. In order to increase the screen ratio, a transparent non-display area (i.e. a pixel blank area) without pixels can be arranged in the display area of the display panel to accommodate the electronic device.
In the prior art, as shown in fig. 1, one of the structures of the display device is a schematic diagram, a large number of data lines V are often arranged around the pixel blank area W, so as to provide data signals for the pixels px in the area U on the side of the pixel blank area W far from the driving IC, however, more data lines result in wider frames of the pixel blank area W, thereby affecting the display quality of the display device.
It can be seen that how to improve the display quality of the display device is an extremely important technical problem.
Disclosure of Invention
The invention provides a display panel, a driving method thereof and a display device, which are used for improving the display quality of the display device.
In a first aspect, an embodiment of the present invention provides a display panel, including:
a display area provided with a through hole and a non-display area surrounding the display area;
the display area comprises data lines and grid lines which are arranged in a crossing mode;
the non-display area comprises a control switch and a driving chip electrically connected with each data line;
wherein a part of the data lines are disconnected by the via holes, the data lines which are partially disconnected by the via holes and the data lines which are not partially disconnected by the via holes are electrically connected through the control switches, and all the control switches are electrically connected with the driving chip, the control switches are used for storing first data signals provided by the driving chip in parasitic capacitances of the data lines which are partially disconnected by the via holes when in an on state, and the driving chip is used for providing second data signals to the data lines which are not partially disconnected by the via holes when the control switches are in an off state, the parasitic capacitances are used for maintaining the data lines which are partially disconnected by the via holes at the first data signals, the first data signals are used for driving first pixels on the data lines which are partially disconnected by the via holes, and the second data signals are used for driving second pixels on the data lines which are not partially disconnected by the via holes.
In one possible implementation, the data line partially disconnected by the via is electrically connected to the adjacent data line not disconnected by the via through the control switch.
In one possible implementation manner, the non-display area includes shift registers disposed on two sides of each row of the gate lines, one of the shift registers is electrically connected to one of the gate lines, and when the shift registers on two sides of the gate lines electrically connected to the first pixel and the second pixel are in an on state, the shift registers charge the first pixel according to the first data signal and charge the second pixel according to the second data signal.
In one possible implementation manner, in a charging period, a charging time length of a row gate line where the first pixel and the second pixel are located is a first time length, where the first time length at least includes an on time length of the control switch and an on time length of the shift register, and the on time length of the shift register is smaller than the first time length.
In one possible implementation manner, the shift registers on two sides of the grid line of the row where each pixel is located on the data line which is partially disconnected by the through hole are electrically connected with a redundant shift register, and the redundant shift register is used for transmitting a required row scanning signal of the grid line of the current row to the shift register which is electrically connected with the grid line of the current row.
In one possible implementation manner, in one charging period, the charging duration of the shift register on the first pixel and the second pixel is the first duration.
In a second aspect, an embodiment of the present invention provides a driving method of a display panel as described above, including:
outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
the driving chip controls the switch to be in the conducting state, and the first data signal is stored in parasitic capacitance of the data line which is partially disconnected by the through hole;
the switch is controlled to be in the cut-off state by the driving chip, the second data signal for driving the second pixel on the data line of which part is not disconnected by the through hole is output, and the data line of which part is disconnected by the through hole is maintained at the first data signal by the parasitic capacitance.
In one possible implementation, the method further includes:
when the shift registers on two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, the first pixel is charged according to the first data signal through the shift register, and the second pixel is charged according to the second data signal.
In one possible implementation manner, the charging the first pixel according to the first data signal and the charging the second pixel according to the second data signal through the shift register includes:
in a charging period, the first pixel and the second pixel are charged for a second time period through the shift register, the second time period is smaller than the first time period, and the first time period at least comprises the opening time period of the control switch and the opening time period of the shift register.
In a third aspect, an embodiment of the present invention provides a display apparatus, including:
the display panel as described above.
The beneficial effects of the invention are as follows:
the embodiment of the invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises: a display area provided with through holes and a non-display area surrounding the display area, wherein the display area comprises data lines and grid lines which are arranged in a crossing way, the non-display area comprises control switches and a driving chip which is electrically connected with each data line, the data lines which are partially disconnected by the through holes are electrically connected with the data lines which are partially disconnected by the through holes through the control switches, all the control switches are electrically connected with the driving chip, the control switches are used for storing first data signals provided by the driving chip in parasitic capacitance of the data lines which are partially disconnected by the through holes when in an on state, the driving chip is used for providing second data signals to the data lines which are partially disconnected by the through holes when in an off state when the control switches are in an off state, at the moment, the parasitic capacitance is used for maintaining the data lines which are partially disconnected by the through holes to be the first data signals, that is, the control switch disposed in the non-display area is used to control the data signals required by the pixels on the data lines which are partially disconnected by the through holes and the data lines which are partially disconnected by the through holes, on one hand, since the control switch is disposed in the non-display area and the data lines which are partially disconnected by the through holes are electrically connected with the data lines which are partially disconnected by the through holes through the control switch, the narrow frame design of the pixel blank area is ensured, and on the other hand, when the row scanning signal is outputted in the subsequent row scanning, the first pixels and the second pixels of the same scanning row can be independently controlled to perform data writing according to the data signals required by the first pixels and the second pixels of the same scanning row, so that the display quality of the display device is ensured.
Drawings
FIG. 1 is a schematic diagram of one structure of a display device in the related art;
FIG. 2 is a schematic diagram of one structure of a display device according to the related art;
FIG. 3 is a schematic diagram of one structure of a display device according to the related art;
fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 8 is a timing diagram corresponding to the control switch shown in FIG. 7 being a P-channel FET;
FIG. 9 is a timing diagram corresponding to the control switch of FIG. 7 being an N-channel FET;
fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 11 is a timing diagram of the control switch of FIG. 10 for one of the PFETs;
fig. 12 is a flowchart of a method for driving a display panel according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. And embodiments of the invention and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used in this specification, the word "comprising" or "comprises", and the like, means that the element or article preceding the word is meant to encompass the element or article listed thereafter and equivalents thereof without excluding other elements or articles.
It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present invention only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In the prior art, a structural design as shown in fig. 2 and fig. 3 may be adopted to ensure a narrow frame design of the pixel blank area a, specifically, in fig. 2, gate control signals of pixels in each row in an area U on one side of the pixel blank area W facing away from the driving IC are controlled by independent gate driving circuits (Gate Driver on Array, GOAs), routing of each independent GOA must pass through the display area X, and when the number of rows of pixels in each row on one side of the pixel blank area W facing away from the driving IC is greater, routing of each independent GOA is also increased, so that differences exist between the area U on one side of the pixel blank area W facing away from the driving IC and other areas except for the area U in the display area X during display, which results in poor display quality.
In addition, referring to fig. 3, in the area U of the pixel blank area W facing away from the driving IC, each column of pixels is electrically connected with other data lines than the data lines in the display area X, and each column of data lines is electrically connected with the driving IC through the borders on both sides of the display panel.
In view of the above, embodiments of the present invention provide a display panel, a driving method thereof, and a display device for improving display quality of the display device.
Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and specifically, the display panel includes:
a display area X provided with a through hole H and a non-display area E surrounding the display area X;
the display area X comprises a data line d and a grid line g which are arranged in a crossing way;
the non-display area E includes a control switch 10 and a driving chip 20 electrically connected to each data line d;
wherein, the data line d1 partially disconnected by the through hole H and the data line d2 partially disconnected by the through hole H are electrically connected through the control switch 10, and all the control switches 10 are electrically connected with the driving chip 20, the control switch 10 is used for storing the first data signal provided by the driving chip 20 in the parasitic capacitance of the data line d1 partially disconnected by the through hole H when in the on state, the driving chip 20 is used for providing the second data signal to the data line d2 partially disconnected by the through hole H when the control switch 10 is in the off state, the parasitic capacitance is used for maintaining the data line d1 partially disconnected by the through hole H at the first data signal, the first data signal is used for driving the first pixel PX1 on the data line d1 partially disconnected by the through hole H, and the second data signal is used for driving the second pixel PX2 on the data line d2 partially disconnected by the through hole H.
In the embodiment of the present invention, the number of data lines d in the display area X is often plural, and the number of gate lines g is often plural, wherein part of the data lines in the plurality of data lines are disconnected by the through holes H, and part of the data lines are not disconnected by the through holes H. In the implementation process, the data line d1 partially disconnected by the through hole H and the data line d2 partially not disconnected by the through hole H are electrically connected through the control switch 10, so that it is not necessary to arrange related data lines for the pixel columns partially disconnected by the through hole H at the periphery of the through hole H, thereby ensuring the narrow frame design at the periphery of the through hole H.
In the embodiment of the present invention, the data line d1 partially disconnected by the through hole H and the data line d2 partially disconnected by the through hole H are electrically connected through the control switch 10, specifically, one of the data lines d1 partially disconnected by the through hole H and one of the data lines d2 partially disconnected by the through hole H are electrically connected through a control switch 10 in one-to-one correspondence, specifically, the source electrode and the drain electrode of the control switch 10 are respectively electrically connected with the two data lines, and accordingly, the gate electrode of the control switch 10 is electrically connected with the driving chip 20. When there are a plurality of data lines d1 partially disconnected by the via hole H, each data line is electrically connected to a part of the data lines d2 partially disconnected by the via hole H through a control switch 10. For example, when there are four data lines d1 partially disconnected by the via H, electrical connection between the four data lines and four data lines of the data lines d2 partially disconnected by the via H is correspondingly achieved by the four control switches 10. As shown in fig. 4, when there are two data lines d1 partially disconnected by the through holes H, one of the two control switches 10 is provided. Of course, the person skilled in the art may set the control switch 10 according to the actual setting of the data line d1 partially disconnected by the through hole H, which is not limited herein.
In the embodiment of the present invention, the control switch 10 is configured to store the first data signal provided by the driving chip 20 in the parasitic capacitance of the data line d1 partially disconnected by the through hole H in the on state, where the first data signal is used to drive the first pixel PX1 on the data line d1 partially disconnected by the through hole H. The parasitic capacitance belongs to the self-contained capacitance of the corresponding data line, and as long as the data line is arranged, the parasitic capacitance exists correspondingly. When the control switch 10 is in the off state, the driving chip 20 is configured to supply a second data signal to the data line d2 partially not disconnected by the via hole H, wherein the second data signal is configured to drive the second pixel PX2 on the data line d2 partially not disconnected by the via hole H, and at this time, the parasitic capacitance maintains the data line d2 partially not disconnected by the via hole H at the first data signal, that is, the data line d2 partially not disconnected by the via hole H maintains its potential at the same potential as the first data signal by virtue of the parasitic capacitance thereon. Thus, by controlling the on and off of the control switch 10 provided in the non-display area E, independent control of the data signals required for the pixels on the data line d1 partially disconnected by the via hole H and the data line d2 partially not disconnected by the via hole H is achieved.
In a specific implementation process, the control switch 10 may be a thin film transistor, a field effect transistor, an N-channel thin film transistor, a P-channel thin film transistor, an N-channel field effect transistor, or a P-channel field effect transistor, which is not limited herein. When the control switch 10 is a P-channel field effect transistor, the control switch 10 is in an on state when the gate signal Ctrl supplied to the control switch 10 by the driving chip 20 is at a low potential, and the control switch 10 is in an off state when the gate signal Ctrl supplied to the control switch 10 by the driving chip 20 is at a high potential. When the control switch 10 is an N-channel field effect transistor, the control switch 10 is in an on state when the gate signal Ctrl provided to the control switch 10 by the driving chip 20 is at a high potential, and the control switch 10 is in an off state when the gate signal Ctrl provided to the control switch 10 by the driving chip 20 is at a low potential, however, in practical applications, the on and off of the control switch 10 may be controlled according to the specific situation of the selected control switch 10, which is not limited herein.
In the embodiment of the present invention, since the control switch 10 is disposed in the non-display area E, and the data line d1 partially disconnected by the through hole H and the data line d2 partially not disconnected by the through hole H are electrically connected through the control switch 10, the narrow frame design around the through hole H is ensured. In addition, when the subsequent GOA performs line scanning to output a line scanning signal, since the data signals required by the first pixel PX1 and the second pixel PX2 of the same scanning line can be independently controlled, the first pixel PX1 and the second pixel PX2 on the same scanning line can perform data writing according to the data signals required by each other, thereby ensuring the display quality of the display device.
In the embodiment of the present invention, as shown in fig. 5 and 6, one of the structural diagrams of the display panel in the embodiment of the present invention is shown, specifically, the data line d1 partially disconnected by the through hole H is electrically connected to the adjacent data line d2 not disconnected by the through hole H through the control switch 10. In this way, without longer wiring, the data line d1 which is partially disconnected by the through hole H is electrically connected to the adjacent data line d2 which is not disconnected by the through hole H through the control switch 10, so that the overall resistance is small, and the display effect of each pixel on the data line d1 after the electrical connection is ensured. In fig. 5, when there are two data lines d1 partially disconnected by the through holes H, one of the two control switches 10 is provided. As shown in fig. 6, when there are four data lines d1 partially disconnected by the through holes H, one of the four control switches 10 is provided.
In an embodiment of the present invention, as shown in fig. 7, which is a schematic diagram of one of the structures of the display panel in the embodiment of the present invention, specifically, the non-display area E includes shift registers 30 respectively disposed at two sides of each row of gate lines, one shift register 30 is electrically connected to one gate line, and when the shift registers 40 at two sides of the gate lines electrically connected to the first pixel PX1 and the second pixel PX2 are in an on state, the shift registers 40 charge the first pixel PX1 according to the first data signal and charge the second pixel PX2 according to the second data signal. In a specific implementation, when the control switch 10 is in the off state, the driving chip 20 supplies the second data signal to the data line d2 which is partially not disconnected by the through hole H, the parasitic capacitance maintains the data line d2 which is partially not disconnected by the through hole H at the first data signal, then the shift registers 40 on both sides of the gate line where the first pixel PX1 and the second pixel PX2 are located are turned on, the first pixel PX1 is charged according to the first data signal through the shift register 30, and the second pixel PX2 is charged according to the second data signal, that is, the shift registers 40 perform data writing according to the voltages required by the first pixel PX1 and the second pixel PX2, respectively. After a period of time, the shift register 40 is turned off, and the first pixel PX1 and the second pixel PX2 are charged, so that writing of data signals required by the first pixel PX1 and the second pixel PX2 is ensured.
In the embodiment of the present invention, in one charging period, the charging time period of the row gate line of the first pixel PX1 and the second pixel PX2 at least includes the on time period of the control switch 10 and the on time period of the shift register 30, where the on time period of the shift register 30 is smaller than the first time period, and since in one charging period, the data writing of the voltage required by the first pixel PX1 and the second pixel PX2 is implemented through the shift register 40, that is, the writing of the data signal required by the first pixel PX1 and the second pixel PX2 is ensured.
In the implementation process, in combination with the display panel shown in fig. 5, and the timing chart shown in fig. 8 is adopted, fig. 8 is specifically one of the timing charts when the control switch 10 is a P-channel field effect transistor, for example, the first pixel PX1 is a pixel a located on the Data line Data (n), the second pixel PX2 is a pixel a located on the Data line Data (n), and the Data line Data (n) is further provided with a pixel B, a pixel C, a pixel D, and so on, where the pixel a and the pixel a are located on the (n-1) th row gate line, the pixel B and the pixel B are located on the n-th row gate line, and n is an integer greater than 1. A pixel a, a pixel B, a pixel C, a pixel D, and the like are sequentially disposed on the Data line Data (m) adjacent to the Data line Data (n). For the Data line Data (m), the driving chip 20 sequentially supplies driving voltages to the pixel a, the pixel B, the pixel C, and the pixel D on the Data line according to the scanning frequency of the shift register 40. For the pixels on the (n-1) -th row gate line, taking the pixel a and the pixel a as examples, the Data line Data (n) needs to supply the driving voltage for both the pixel a and the pixel a. Specifically, the first Data signal required for the pixel a is output through the driving chip 20, then, when the gate signal Ctrl of the control switch 10 is adjusted to be low through the driving chip 20, the control switch 10 is in an on state at this time, so that the first Data signal is stored in the parasitic capacitance on the Data (n), then, the gate signal Ctrl of the control switch 10 is adjusted to be high through the driving chip 20, the control switch 10 is in an off state at this time, the Data line d1 of the pixel a, which is disconnected by the through hole H, maintains the potential corresponding to the first Data signal by means of the parasitic capacitance, then, the second Data signal required for the pixel a is output through the driving chip 20, then, the shift register 40 connected to the (n-1) th row gate line is turned on, i.e., G (n-1) is turned on, at this time, the pixel a is written according to the first Data signal, the pixel a is written according to the second Data signal, that is, the pixel a and the pixel a are respectively written according to the respective required voltages, after a period of time, G (n-1) is turned off, the (n-1) th row gate line charging period is ended, and as shown in fig. 8, in one charging period of the (n-1) th row, the charging period 1H of the (n-1) th row includes the on period of Ctrl signal, the on period of the shift register 30, and a partial time interval, the charging period being 1H as shown by an arrow in fig. 8. In addition, in one charging period of the (n-1) th row, the charging period for both the pixel a and the pixel a is the on period of the shift register 30.
In the implementation process, for the pixel B and the pixel B on the n-th row gate line, the signal writing to the corresponding pixels may be implemented in the same implementation manner, which will not be described in detail herein. Since the pixels on the data line d1 disconnected by the via hole H and the pixels on the data line d2 not disconnected by the via hole H can be respectively written with data according to the required voltages, the display quality of the corresponding pixels is ensured.
In the implementation process, when the control switch 10 is an N-channel field effect transistor in fig. 7, the adopted timing diagram is correspondingly different from that of fig. 8, and may be specifically shown in fig. 9, and the specific charging process will not be described in detail herein.
In an embodiment of the present invention, as shown in fig. 10, a schematic diagram of one structure of a display panel provided in the embodiment of the present invention is shown, specifically, shift registers 30 on two sides of a row gate line where each pixel is located on a data line d1, which is partially disconnected by a through hole H, are electrically connected to a redundant shift register 40, and the redundant shift register 40 is used for transmitting a required row scanning signal of a current row gate line to the shift registers 30 electrically connected to the current row gate line. In the implementation process, on one side of the through hole H away from the driving chip 20, each pixel d1 on the data line disconnected by the through hole H is located on two adjacent rows of gate lines, as shown in fig. 10, and is located on the (n-1) -th row gate line and the n-th row gate line, and a redundant shift register 40 is disposed on two sides of each gate line. In the implementation process, the redundant shift register 40 may have the same circuit structure as the shift register in the prior art, and the implementation may be referred to the implementation in the prior art, which is not described herein. In addition, for each redundant shift register 40, only the transfer of the current row scan signal is involved, and the gate control signal is not directly provided to the pixels on the current row gate line. In this way, the interval duration between the gate control signals for driving the pixels on each row of gate lines on the data line d1, the portion of which is disconnected by the through hole H, can be relatively prolonged, so that the opening duration of the gate control signals is prolonged, and the display uniformity of the display panel is further ensured.
In the embodiment of the present invention, as shown in fig. 11, one of timing diagrams corresponding to the control switch 10 being a P-channel field effect transistor in the display panel shown in fig. 10 is shown, specifically, in one charging period, the charging duration of the shift register 40 to the first pixel PX1 and the second pixel PX2 is the first duration. Taking the control switch 10 as a P-channel field effect transistor as an example, compared with fig. 8, after the redundancy shift register 40 is added, the charging time length of the row gate lines where the first pixel PX1 and the second pixel PX2 are located may be 2 times the first time length 1H, and the shift register 30 may charge both the pixel a and the pixel a with the first time length 1H, so that the opening time length of G (n-1) is further improved compared with fig. 8, and the display quality of the display panel is ensured.
Based on the same inventive concept, as shown in fig. 12, an embodiment of the present invention further provides a driving method of a display panel, including:
s101: outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
s102: the driving chip controls the switch to be in the conducting state, and the first data signal is stored in parasitic capacitance of the data line which is partially disconnected by the through hole;
s103: the switch is controlled to be in the cut-off state by the driving chip, the second data signal for driving the second pixel on the data line of which part is not disconnected by the through hole is output, and the data line of which part is disconnected by the through hole is maintained at the first data signal by the parasitic capacitance.
Since the principle of solving the problem of the driving method of the display panel provided by the embodiment of the invention is similar to that of the display panel, the implementation of the driving method can be referred to the implementation of the display panel, and the repetition is omitted.
In an embodiment of the present invention, the method further includes:
when the shift registers on two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, the first pixel is charged according to the first data signal through the shift register, and the second pixel is charged according to the second data signal.
In an embodiment of the present invention, the charging the first pixel according to the first data signal and the charging the second pixel according to the second data signal by the shift register includes:
in a charging period, the first pixel and the second pixel are charged for a second time period through the shift register, the second time period is smaller than the first time period, and the first time period at least comprises the opening time period of the control switch and the opening time period of the shift register. The principle of solving the problem of the display device is similar to that of the display panel, so that the implementation of the display device can be referred to the implementation of the display panel, and the repetition is omitted.
In a specific implementation process, the display device provided by the embodiment of the invention may be a liquid crystal (Liquid Crystal Display, LCD) display, an Organic Light-Emitting Diode (OLED) display, and specifically may be a mobile phone, or may be any product or component with a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device will be understood by those skilled in the art, and will not be described herein in detail, nor should they be considered as limiting the invention.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (4)
1. A display panel, comprising:
a display area provided with a through hole and a non-display area surrounding the display area;
the display area comprises data lines and grid lines which are arranged in a crossing mode;
the non-display area comprises a control switch and a driving chip electrically connected with each data line;
wherein a part of the data lines are disconnected by the through holes, the data lines which are partially disconnected by the through holes and the data lines which are not partially disconnected by the through holes are electrically connected through the control switches, and all the control switches are electrically connected with the driving chip, the control switches are used for storing first data signals provided by the driving chip in parasitic capacitances of the data lines which are partially disconnected by the through holes when in an on state, and the driving chip is used for providing second data signals to the data lines which are not partially disconnected by the through holes when the control switches are in an off state, the parasitic capacitances are used for maintaining the data lines which are partially disconnected by the through holes at the first data signals, the first data signals are used for driving first pixels on the data lines which are partially disconnected by the through holes, and the second data signals are used for driving second pixels on the data lines which are not partially disconnected by the through holes;
the control switches are multiple, the grid electrodes of each control switch are coupled with the same control signal end, the same signal from the driving chip is received through the control signal end, each control switch is arranged along the extending direction parallel to the grid line, and the control switches and the data lines coupled with each control switch are arranged in a non-surrounding manner; the data line which is partially disconnected by the through hole is electrically connected with the adjacent data line which is not disconnected by the through hole through the control switch;
the non-display area comprises shift registers respectively arranged at two sides of each row of grid lines, one shift register is electrically connected with one grid line, and when the shift registers at two sides of the grid lines which are electrically connected with the first pixel and the second pixel are in an open state, the shift registers charge the first pixel according to the first data signal and charge the second pixel according to the second data signal;
in a charging period, the line scanning time of the first pixel and the second pixel is a first time, and the first time at least comprises the starting time of the control switch and the starting time of the shift register, wherein the first time is 1H;
the shift registers on the two sides of the grid line of the row where each pixel is located on the data line which is partially disconnected by the through hole are electrically connected with a redundant shift register, and the redundant shift register is used for transmitting a required row scanning signal of the grid line of the current row to the shift register which is electrically connected with the grid line of the current row.
2. The display panel of claim 1, wherein a charge duration of the shift register for the first pixel and the second pixel is 1H during one charge period.
3. A driving method of the display panel according to claim 1 or 2, comprising:
outputting, by the driving chip, the first data signal for driving the first pixel on the data line partially disconnected by the via hole;
the driving chip controls the switch to be in the conducting state, and the first data signal is stored in parasitic capacitance of the data line which is partially disconnected by the through hole;
controlling the switch to be in the cut-off state by the driving chip, outputting the second data signal for driving the second pixel on the data line of which part is not disconnected by the through hole, and maintaining the data line of which part is disconnected by the through hole at the first data signal by the parasitic capacitance;
the method further comprises the steps of: when the shift registers on two sides of the grid line electrically connected with the first pixel and the second pixel are in an open state, charging the first pixel according to the first data signal through the shift register, and charging the second pixel according to the second data signal;
wherein the charging the first pixel according to the first data signal and the charging the second pixel according to the second data signal through the shift register includes:
in a charging period, the first pixel and the second pixel are charged for a second time period through the shift register, the second time period is smaller than a first time period, the first time period at least comprises the starting time period of the control switch and the starting time period of the shift register, and the first time period is 1H and H represents the line scanning time period.
4. A display device, comprising:
the display panel of claim 1 or 2.
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| WO2022088030A1 (en) * | 2020-10-30 | 2022-05-05 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display device |
| CN113450716B (en) * | 2021-09-01 | 2021-11-09 | 苇创微电子(上海)有限公司 | Method, system, storage medium and processor for real-time digital compensation of AMOLED (active matrix/organic light emitting diode) special-shaped screen crosstalk |
| CN117529768A (en) * | 2022-05-20 | 2024-02-06 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN116110342B (en) * | 2022-11-14 | 2024-12-06 | 重庆惠科金渝光电科技有限公司 | Pixel compensation circuit, display panel and driving method |
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| WO2019001043A1 (en) * | 2017-06-30 | 2019-01-03 | 京东方科技集团股份有限公司 | Array substrate and driving method therefor, and display device |
| CN109524445A (en) * | 2018-12-20 | 2019-03-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109904214A (en) * | 2019-03-29 | 2019-06-18 | 上海天马有机发光显示技术有限公司 | A kind of display panel, the display device comprising it |
| CN110060575A (en) * | 2019-04-26 | 2019-07-26 | 上海天马有机发光显示技术有限公司 | A kind of display panel, the display device comprising it |
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| CN109524445A (en) * | 2018-12-20 | 2019-03-26 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109904214A (en) * | 2019-03-29 | 2019-06-18 | 上海天马有机发光显示技术有限公司 | A kind of display panel, the display device comprising it |
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