CN111599792A - Wafer-level rewiring layer structure and manufacturing method thereof - Google Patents
Wafer-level rewiring layer structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 150000002894 organic compounds Chemical class 0.000 claims abstract description 61
- 238000002161 passivation Methods 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000002184 metal Substances 0.000 claims description 46
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 154
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 21
- 229910052802 copper Inorganic materials 0.000 description 20
- 239000010949 copper Substances 0.000 description 20
- 230000032798 delamination Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000005272 metallurgy Methods 0.000 description 2
- 241001424392 Lucia limbaria Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a wafer-level rewiring layer structure and a manufacturing method thereof, wherein the wafer-level rewiring layer structure comprises a wafer, wherein the surface of the wafer is provided with a plurality of conductive bonding pads; the wafer passivation layer is formed on the surface of the wafer; the first openings are formed in the wafer passivation layer, and expose the conductive bonding pads according to the conductive bonding pad circuit design; the first organic compound insulating layer is formed on the surface of the wafer passivation layer and covers the side wall of the first opening; a plurality of second openings formed in the first organic compound insulating layer and exposing the conductive pads; the rewiring layer is formed on the surface of the first organic compound insulating layer, covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure; and a mesh formed at a predetermined position in the rewiring layer. The invention can make the rewiring layer and the upper and lower insulating layers embedded with each other by forming the meshes on the rewiring layer, thereby enhancing the binding force of the rewiring layer and the insulating layer and fundamentally solving the problem of layering.
Description
Technical Field
The invention relates to a wafer-level rewiring layer structure and a manufacturing method thereof, and belongs to the technical field of wafer manufacturing.
Background
re-Routing (RDL) is to change the contact positions of IC circuit pads (I/O pads) of the original wafer design by wafer level metal routing process or bumping process, so that the IC can be adapted to different package types. The wafer level metal wiring process is to coat an insulating protective layer on the IC, define a new wire pattern in an exposure and development mode, and then manufacture a new metal circuit by using an electroplating technology to connect the original aluminum pad and a new bump or pad, so as to achieve the purpose of redistribution of the circuit. The rewired metal circuit is mainly sputtered copper material, and nickel gold or nickel palladium gold can be plated on the copper circuit according to the requirement. The thick copper structure is the best choice for high current and high power devices due to its advantages of low resistance, high heat dissipation and low cost.
At present, in chip products which need to be RDL (called re-wiring in a contracted manner, the same applies hereinafter), in order to meet the requirements of the electrical performance of the products, a large area of copper needs to be laid in RDL design of many products, and meanwhile, the problem of combination of a copper layer and an insulating protection layer (such as a PI layer) is brought, and when the copper layer reaches a certain area, poor combination and delamination of the copper layer and the PI layer occur. The layering of the RDL directly affects the reliability of the chip, and the layering leads to poor heat dissipation of the product, and the chip is directly damaged after continuous operation.
Disclosure of Invention
In view of the problems in the prior art, the invention provides a wafer-level rewiring layer structure, which enables a copper layer and upper and lower insulating layers to be embedded with each other by increasing mesh design, so that the binding force between the copper layer and the insulating layers is enhanced, and the problem of delamination is fundamentally solved.
In order to achieve the purpose, the invention adopts the following technical scheme: a wafer level re-routing layer structure, comprising:
the surface of the wafer is provided with a plurality of conductive bonding pads;
the wafer passivation layer is formed on the surface of the wafer;
the first openings are formed in the wafer passivation layer, and expose the conductive bonding pads according to the conductive bonding pad circuit design;
the first organic compound insulating layer is formed on the surface of the wafer passivation layer and covers the side wall of the first opening;
a plurality of second openings formed in the first organic compound insulating layer and exposing the conductive pads;
the rewiring layer is formed on the surface of the first organic compound insulating layer, covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure;
and meshes formed at predetermined positions in the rewiring layer and exposing the first organic compound insulating layer.
Preferably, the redistribution layer is a metal wiring layer, and the mesh is arranged in a region where the metal continuous area in the metal wiring layer exceeds 500 × 500 um.
Preferably, the mesh is a circular opening.
Preferably, the diameter scope of circular trompil is 100um-150um, and the interval scope between two arbitrary adjacent circular trompils is 120um-150um, arbitrary one the distance of circular trompil edge to metal wiring layer edge is not less than 50 um.
A wafer level re-routing layer structure, further comprising:
a second organic compound insulating layer formed on the surface of the rewiring layer, covering the side walls and the bottom of the mesh, and bonded to the first organic compound insulating layer at the bottom of the mesh;
a plurality of third openings formed in the second organic compound insulating layer and exposing the rewiring layer;
the under bump metal layer is formed on the surface of the second organic compound insulating layer, covers the side wall and the bottom of the third opening and is electrically connected with the rewiring layer exposed in the third opening;
and the tin bump is formed on the under bump metal layer and is electrically connected with the under bump metal layer.
Preferably, the first organic compound insulating layer and the second organic compound insulating layer are made of polyimide.
A manufacturing method of a wafer-level rewiring layer structure comprises the following steps:
providing a wafer, wherein the surface of the wafer is provided with a plurality of conductive bonding pads;
forming a wafer passivation layer on the surface of the wafer, and forming a plurality of first openings exposing the conductive bonding pads in the wafer passivation layer;
forming a first organic compound insulating layer covering the side wall of the first opening on the surface of the wafer passivation layer, and forming a plurality of second openings exposing the conductive bonding pad in the first organic compound insulating layer;
fourthly, forming a rewiring layer on the surface of the first organic compound insulating layer, wherein the rewiring layer covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure;
and step five, forming meshes for the embedded connection at preset positions in the rewiring layer.
Preferably, the redistribution layer is a metal wiring layer, and the mesh is arranged in a region where the metal continuous area in the metal wiring layer exceeds 500 × 500 um.
Preferably, the meshes are circular openings with the diameter ranging from 100um to 150um, the distance between any two adjacent circular openings ranges from 120um to 150um, and the distance from the edge of any one circular opening to the edge of the metal line layer is not less than 50 um.
A wafer level re-wiring layer structure, further comprising, after forming the mesh, the steps of:
forming a second organic compound insulating layer covering the side wall and the bottom of the mesh on the surface of the rewiring layer, and forming a plurality of third openings exposing the rewiring layer in the second organic compound insulating layer;
forming the under bump metal layer in the third opening on the surface of the second organic compound insulating layer, wherein the under bump metal layer covers the side wall and the bottom of the third opening and is electrically connected with the rewiring layer exposed at the third opening;
and forming a tin bump electrically connected with the under bump metal layer on the under bump metal layer.
Compared with the prior art, the invention increases the mesh design on the rewiring layer to enable the copper layer and the upper and lower insulating layers to be mutually embedded, thereby enhancing the bonding force of the copper layer and the insulating layer and fundamentally solving the problem of layering. The technical scheme has no increase on product cost, has no obvious difficulty in technical operation, and obviously improves the RDL layering phenomenon.
Drawings
FIG. 1 is a schematic view of the present invention;
FIG. 2 is a product of a wafer level re-routing layer structure;
FIG. 3 is a scan of the circled portion of FIG. 2;
fig. 4 is a schematic view of the mesh design of fig. 2;
fig. 5 is a scan of the circled portion in fig. 4.
Detailed Description
The technical solutions in the implementation of the present invention will be made clear and fully described below with reference to the accompanying drawings, and the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Example 1:
the invention provides a wafer-level rewiring layer structure, as shown in fig. 1, which comprises a wafer 1, a wafer passivation layer 3, a plurality of first openings 7, a first organic compound insulating layer 4, a plurality of second openings 8, a rewiring layer 6 and meshes 5, wherein a plurality of conductive bonding pads 2 are arranged on the surface of the wafer 1; the wafer passivation layer 3 is formed on the surface of the wafer 1 to avoid a conductive bonding pad area; the first opening 7 is formed in the wafer passivation layer 3 and exposes the conductive pad 2 according to a conductive pad circuit design; the first organic compound insulating layer 4 is formed on the surface of the wafer passivation layer 3 and covers the side wall of the first opening 7; the second opening 8 is formed in the first organic compound insulating layer 4 and exposes the conductive pad 2; the rewiring layer 6 is formed on the surface of the first organic compound insulating layer 4, covers the side wall and the bottom of the second opening 8, and is electrically connected with the conductive pad 2 in a physical structure; the mesh 5 is formed at a predetermined position in the rewiring layer 6 and exposes the first organic compound insulating layer 4; that is, the mesh is a fitting passage reserved in the rewiring layer 6 for the rewiring layer 6 and the two organic compound insulating layers above and below the rewiring layer. In other words, the rewiring layer 6 is covered by the second organic compound insulating layer, the mesh position is filled with the organic compound insulating material, and the opening is formed in the second organic compound insulating layer to expose the copper layer according to the circuit design requirement, thereby facilitating the subsequent bump formation process. Wherein the first organic compound insulating layer 4 may function as a buffer for facilitating connection reliability of the re-wiring layer 6 to be formed later and the conductive pad 2. As an example, the first organic compound insulating layer 4 is polyimide (abbreviated as PI).
Specifically, the redistribution layer is used for redistributing the positions of the conductive pads, the redistribution layer is a metal circuit layer, as an example, a copper layer is preferably adopted, and in consideration of the fact that delamination is not easy to occur in a region with a small copper layer continuous area, the meshes are arranged in a region with the copper layer continuous area exceeding 500 × 500um in the copper layer, namely, the region with the copper layer continuous area exceeding 500 × 500um is provided with meshes, and then the occurrence of delamination is reduced.
Specifically, the meshes are circular openings. Of course, the mesh may be a square opening, but considering that the PI liquid and the position of the opening have better wettability when the first organic compound insulating layer or the second organic compound insulating layer is formed, the four corners of the square opening generate tension and are easy to generate bubbles, and therefore, the effect of the circular opening is better than that of the opening with other shapes such as a square shape.
When the round holes are too small, the processing and the manufacturing are not easy, and the delamination is easy to occur; when the circular trompil is too big, the effect of rewiring layer is not good enough, and the diameter range of circular trompil is 100um-150um comprehensively considering. If the distance between any two adjacent circular openings is too small, the two adjacent circular openings are possibly connected together due to machining and manufacturing tolerances in the machining and manufacturing process, so that the shapes of the openings with different specifications are easy to generate, and the subsequent filling or the characteristics of a copper layer are influenced; if the distance between any two adjacent circular openings is too large, the risk of layering exists; therefore, the spacing between any two adjacent circular openings ranges from 120um to 150 um. The distance between any one circular opening and the edge of the metal circuit layer is not less than 50um, and if the circular opening is too close to the edge of the copper layer, the characteristics of the copper layer are affected when the manufacturing tolerance is larger.
In another embodiment, the redistribution layer structure further includes a second organic compound insulating layer 11, a plurality of third openings 12, an under bump metal layer 10, and a tin bump 9, where the second organic compound insulating layer 11 is formed on the surface of the redistribution layer 6, covers the sidewalls and the bottom of the mesh 5, and is bonded to the first organic compound insulating layer 4 at the bottom of the mesh; the third opening 12 is formed in the second organic compound insulating layer 11, and exposes the rewiring layer 6; the under bump metal layer 10 is formed on the surface of the second organic compound insulating layer 11, covers the sidewall and the bottom of the third opening 12, and forms an electrical connection with the rewiring layer 6 exposed at the third opening 12; the tin bump 9 is formed on the under bump metallurgy 10 and electrically connected to the under bump metallurgy 10. As an example, the second organic compound insulating layer 6 is polyimide (abbreviated as PI).
Example 2:
a manufacturing method of a wafer-level rewiring layer structure comprises the following steps:
providing a wafer, wherein the surface of the wafer is provided with a plurality of conductive bonding pads;
forming a wafer passivation layer on the surface of the wafer, and forming a plurality of first openings exposing the conductive bonding pads in the wafer passivation layer according to the conductive bonding pad circuit design;
forming a first organic compound insulating layer covering the side wall of the first opening on the surface of the wafer passivation layer, and forming a plurality of second openings exposing the conductive bonding pad in the first organic compound insulating layer;
fourthly, forming a rewiring layer on the surface of the first organic compound insulating layer, wherein the rewiring layer covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure;
and step five, forming meshes exposing the first organic compound insulating layer and used for embedding connection at preset positions in the rewiring layer.
As an example, the redistribution layer is a metal wiring layer, and the mesh is arranged in a region where a metal continuous area in the metal wiring layer exceeds 500 × 500 um.
Preferably, the meshes are circular openings with the diameter ranging from 100um to 150um, the distance between any two adjacent circular openings ranges from 120um to 150um, and the distance from the edge of any one circular opening to the edge of the metal line layer is not less than 50 um.
In another embodiment, after the mesh is formed, the following operations may be further performed:
forming a second organic compound insulating layer covering the side wall and the bottom of the mesh on the surface of the rewiring layer, and forming a plurality of third openings exposing the rewiring layer in the second organic compound insulating layer;
forming the under bump metal layer in the third opening on the surface of the second organic compound insulating layer, wherein the under bump metal layer covers the side wall and the bottom of the third opening and is electrically connected with the rewiring layer exposed at the third opening;
and forming a tin bump electrically connected with the under bump metal layer on the under bump metal layer.
It can also be seen from comparing fig. 2 to 4 that, in the same design, when the mesh design is added to the rewiring layer, the delamination effect is significantly reduced.
In summary, the invention adds mesh design to the rewiring layer to make the copper layer of the rewiring layer and the upper and lower insulating layers embedded with each other, thereby enhancing the bonding force between the copper layer and the insulating layer and fundamentally solving the problem of delamination. The technical scheme has no increase on product cost, has no obvious difficulty in technical operation, and obviously improves the RDL layering phenomenon.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the embodiments may be appropriately combined to form other embodiments understood by those skilled in the art.
Claims (10)
1. A wafer level re-routing layer structure, comprising:
the surface of the wafer is provided with a plurality of conductive bonding pads;
the wafer passivation layer is formed on the surface of the wafer;
the first openings are formed in the wafer passivation layer, and expose the conductive bonding pads according to the conductive bonding pad circuit design;
the first organic compound insulating layer is formed on the surface of the wafer passivation layer and covers the side wall of the first opening;
a plurality of second openings formed in the first organic compound insulating layer and exposing the conductive pads;
the rewiring layer is formed on the surface of the first organic compound insulating layer, covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure;
and meshes formed at predetermined positions in the rewiring layer and exposing the first organic compound insulating layer.
2. The wafer level redistribution layer structure of claim 1 wherein said redistribution layer is a metal trace layer, and said mesh is disposed in a region of said metal trace layer where the metal continuous area exceeds 500 x 500 um.
3. The wafer level redistribution layer structure of claim 2 wherein said mesh is a circular opening.
4. The wafer level re-wiring layer structure as claimed in claim 3, wherein the diameter of the circular openings ranges from 100um to 150um, the distance between any two adjacent circular openings ranges from 120um to 150um, and the distance from the edge of any one circular opening to the edge of the metal circuit layer is not less than 50 um.
5. The wafer level redistribution layer structure of claim 1, further comprising:
a second organic compound insulating layer formed on the surface of the rewiring layer, covering the side walls and the bottom of the mesh, and bonded to the first organic compound insulating layer at the bottom of the mesh;
a plurality of third openings formed in the second organic compound insulating layer and exposing the rewiring layer;
the under bump metal layer is formed on the surface of the second organic compound insulating layer, covers the side wall and the bottom of the third opening and is electrically connected with the rewiring layer exposed in the third opening;
and the tin bump is formed on the under bump metal layer and is electrically connected with the under bump metal layer.
6. The wafer level re-wiring layer structure as claimed in claim 5, wherein the first organic compound insulating layer and the second organic compound insulating layer are made of polyimide.
7. A manufacturing method of a wafer-level rewiring layer structure is characterized by comprising the following steps:
providing a wafer, wherein the surface of the wafer is provided with a plurality of conductive bonding pads;
forming a wafer passivation layer on the surface of the wafer, and forming a plurality of first openings exposing the conductive bonding pads in the wafer passivation layer;
forming a first organic compound insulating layer covering the side wall of the first opening on the surface of the wafer passivation layer, and forming a plurality of second openings exposing the conductive bonding pad in the first organic compound insulating layer;
fourthly, forming a rewiring layer on the surface of the first organic compound insulating layer, wherein the rewiring layer covers the side wall and the bottom of the second opening and is electrically connected with the conductive bonding pad in a physical structure;
and step five, forming meshes for the embedded connection at preset positions in the rewiring layer.
8. The method as claimed in claim 7, wherein the redistribution layer is a metal wiring layer, and the mesh is disposed in a region of the metal wiring layer where the metal continuous area exceeds 500 x 500 um.
9. The wafer level re-wiring layer structure as claimed in claim 7, wherein the mesh is a circular opening with a diameter ranging from 100um to 150um, a distance between any two adjacent circular openings ranges from 120um to 150um, and a distance from an edge of any one circular opening to an edge of the metal wiring layer is not less than 50 um.
10. A wafer level redistribution layer structure as claimed in any one of claims 7-9, further comprising the following steps after forming said mesh:
forming a second organic compound insulating layer covering the side wall and the bottom of the mesh on the surface of the rewiring layer, and forming a plurality of third openings exposing the rewiring layer in the second organic compound insulating layer;
forming the under bump metal layer in the third opening on the surface of the second organic compound insulating layer, wherein the under bump metal layer covers the side wall and the bottom of the third opening and is electrically connected with the rewiring layer exposed at the third opening;
and forming a tin bump electrically connected with the under bump metal layer on the under bump metal layer.
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| CN202010476957.9A CN111599792A (en) | 2020-05-29 | 2020-05-29 | Wafer-level rewiring layer structure and manufacturing method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140077356A1 (en) * | 2012-09-14 | 2014-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post Passivation Interconnect Structures and Methods for Forming the Same |
| CN106024751A (en) * | 2015-03-27 | 2016-10-12 | 南茂科技股份有限公司 | Semiconductor structure |
| CN107481986A (en) * | 2016-06-07 | 2017-12-15 | 南茂科技股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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- 2020-05-29 CN CN202010476957.9A patent/CN111599792A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140077356A1 (en) * | 2012-09-14 | 2014-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post Passivation Interconnect Structures and Methods for Forming the Same |
| CN106024751A (en) * | 2015-03-27 | 2016-10-12 | 南茂科技股份有限公司 | Semiconductor structure |
| CN107481986A (en) * | 2016-06-07 | 2017-12-15 | 南茂科技股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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