CN111599753A - Thin wafer heat sink and manufacturing process thereof - Google Patents
Thin wafer heat sink and manufacturing process thereof Download PDFInfo
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- CN111599753A CN111599753A CN202010478956.8A CN202010478956A CN111599753A CN 111599753 A CN111599753 A CN 111599753A CN 202010478956 A CN202010478956 A CN 202010478956A CN 111599753 A CN111599753 A CN 111599753A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
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- Materials Engineering (AREA)
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Abstract
The invention discloses a thin wafer heat sink and a manufacturing process thereof, belonging to the technical field of chip production and comprising the following steps: s1: bonding the front surface of the wafer with the glass carrier plate by using an adhesive after the front surface process of the wafer is finished; s2: grinding and etching the back of the wafer; s3: coating photoresist, and performing a yellow light process and an ion implantation process; s4: generating an adhesion layer and a barrier layer; s5: generating a copper seed layer on the barrier layer; s6: performing a yellow light process, and developing to generate a mask plate pattern; s7: performing an electrochemical plating process, and plating a thick copper film on the copper seed layer; s8: removing the photoresist layer; s9: etching and removing the metal layers of copper, nickel and titanium on the inter-grain cutting path; s10: etching the cutting path between the crystal grains; s11: cleaning residues and polymers; s12: attached to the blue film frame; s13: removing the glass carrier plate from the wafer; s14: cleaning the adhesive; the scheme solves the problem that the radiating fins with enough thickness cannot be arranged on the thin wafer in the prior art.
Description
Technical Field
The invention relates to the technical field of chip production, in particular to a thin wafer heat sink and a manufacturing process thereof.
Background
Semiconductor technology has developed according to the moore's theorem, with integrated circuits having higher and lower densities and smaller dimensions. All integrated circuits generate heat during operation, and as the temperature of elements increases, the performance of semiconductor components and devices decreases, even chip damage is caused. In a general electric circuit, the power consumption of the circuit is small, and the heat dissipation problem of a chip is not considered under the normal heat dissipation condition. However, in a high-voltage high-current or high-speed circuit, the power consumption of the chip is large, and heat dissipation factors need to be considered to ensure that the temperature of the chip does not exceed the allowable working temperature.
The thin thick copper film is plated on the back of the wafer to form the radiating fin, so that the radiating fin has a radiating function, can be applied to general semiconductor components, and still has the limitation on how to form the thicker radiating fin on the ultrathin wafer for power elements requiring higher radiating efficiency. Because the thick copper radiating fins are plated on the ultrathin wafer, the warping degree of the wafer is larger, and the crystal grain cutting cannot be carried out, the crystal grain cutting can only be completed after the thin copper radiating fins are plated on the wafer with the thickness of more than 150um in the prior art.
Therefore, a thin wafer heat sink and its manufacturing process are provided, wherein the die is cut and then electroplated, so that the die separation can be completed only after 10-30 um thick copper film is electroplated on the ultra-thin wafer.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a thin wafer heat sink and a manufacturing process thereof, and solves the problem that the heat sink with enough thickness cannot be arranged on a thin wafer in the prior art.
The purpose of the invention can be realized by the following technical scheme:
a manufacturing process of a thin wafer heat sink comprises the following steps:
s1: bonding the front surface of the wafer with the glass carrier plate by using an adhesive after the front surface process of the wafer is finished;
s2: grinding and etching the back of the wafer;
s3: coating photoresist on the back of the wafer, and performing a yellow light process and an ion implantation process on the back of the wafer;
s4: sequentially generating an adhesion layer and a barrier layer on the back surface of the wafer through one of a sputtering process or an evaporation process;
s5: generating a copper seed layer on the barrier layer by one of sputtering process or evaporation process;
s6: coating a photoresist layer on the back of the wafer, performing a yellow light process, developing to generate a mask plate pattern, and protecting the inter-wafer cutting channel in a photoresist coating mode;
s7: carrying out an electrochemical plating process on the back of the wafer, and plating a thick copper film on the copper seed layer;
s8: removing the photoresist layer on the dicing streets on the back surface of the wafer by using oxygen plasma to expose the streets between the wafers;
s9: removing the metal layers of copper, nickel and titanium on the inter-grain cutting path by wet etching by taking the thick copper film as a mask, and stopping etching on the surface of the silicon wafer;
s10: etching the scribe lines between the grains using sulfur fluoride or other fluorine-containing plasma with the thick copper film as a mask, the etching being stopped at the adhesive layer;
s11: cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine photoresist remover;
s12: turning over the chip to make the back of the wafer attached to the blue film frame;
s13: the viscidity of the adhesive layer release layer is dissociated through ultraviolet irradiation or heat treatment or laser mode, and the glass carrier plate is removed from the wafer;
s14: and cleaning the adhesive layer on the wafer by using an organic solvent to complete the production of the crystal grain with the copper radiating fin.
In a preferred embodiment of the present invention, in step S2, the wafer thickness after the wafer grinding is 30-300 μm.
In a preferred embodiment of the present invention, in step S4, the adhesion layer is a titanium layer, the titanium layer has a thickness of 1-2 microns, the barrier layer is a nickel layer, and the nickel layer has a thickness of 1-2 microns.
In a preferred embodiment of the present invention, in step S7, the thick copper film has a thickness of 5 to 50 μm.
In a preferred embodiment of the present invention, in step S8, the photoresist layer on the inter-grain scribe line on the back surface of the wafer is removed by using an organic solvent.
As a preferable scheme of the invention, the thin wafer heat sink is manufactured by adopting the manufacturing process of the thin wafer heat sink.
The invention has the beneficial effects that:
the invention can safely and nondestructively cut the thin wafer with the copper heat dissipation junction structure; the invention uses the thick copper film as the mask plate, can directly etch, the thickness of the thick copper film is far greater than the thickness of the copper seed layer, the adhesion layer and the barrier layer, and the loss of the thick copper film is very little after the etching of the copper seed layer, the adhesion layer and the barrier layer is finished; and the etching ratio of the thick copper mold to the wafer is about 1: 100, the thick copper film can be directly used as a mask for wafer etching to cut crystal grains, so that the process flow is saved, and the production efficiency and the yield are improved.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a forming structure of step S6 in this embodiment;
FIG. 2 is an enlarged view taken at A in FIG. 1;
FIG. 3 is a schematic view of the forming structure of step S7 in this embodiment;
FIG. 4 is a schematic view of the forming structure of step S8 in this embodiment;
FIG. 5 is a schematic view of the forming structure of step S9 in this embodiment;
FIG. 6 is a schematic view of the forming structure of step S10 in this embodiment;
FIG. 7 is a schematic view of the forming structure of step S12 in this embodiment;
FIG. 8 is a schematic view of the forming structure of step S13 in this embodiment;
fig. 9 is a schematic diagram of the forming structure in step S14 of this embodiment.
The reference numbers in the figures illustrate:
1. a glass carrier plate; 2. a wafer; 3. an adhesive layer; 4. a photoresist layer; 5. an adhesion layer; 6. a barrier layer; 7. a copper seed layer; 8. a thick copper film; 9. a blue film frame.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in the figure, a thin wafer heat sink manufacturing process:
the method comprises the following steps:
s1: after the front surface process of the wafer 2 is finished, bonding the front surface of the wafer 2 with the glass carrier plate 1 by using an adhesive;
s2: grinding and etching the back of the wafer 2;
s3: coating a photoresist on the back surface of the wafer 2, and performing a yellow light process and an ion implantation process on the back surface of the wafer 2;
s4: sequentially generating an adhesion layer 5 and a barrier layer 6 on the back surface of the wafer 2 by one of sputtering process or evaporation process;
s5: forming a copper seed layer 7 on the barrier layer 6 by one of a sputtering process or an evaporation process;
s6: coating a photoresist layer 4 on the back surface of the wafer 2, performing a yellow light process, developing to generate a mask plate pattern, and protecting inter-wafer cutting channels in a photoresist coating mode;
s7: carrying out an electrochemical plating (ECP) process on the back surface of the wafer 2, and plating a thick copper film 8 on the copper seed layer 7;
s8: removing the photoresist layer 4 on the inter-grain scribe lines on the back surface of the wafer 2 by using oxygen plasma to expose the inter-grain scribe lines;
s9: taking the thick copper film 8 as a mask (HardMask), removing the metal layers of copper, nickel and titanium on the inter-grain cutting path by wet etching (WetEtch), and stopping etching on the surface of the silicon wafer;
s10: etching the scribe lines between the grains using (SF6) sulfurous fluoride or other fluorine-containing plasma with the thick copper film 8 as a mask (HardMask), the etching being stopped at the adhesive layer 3;
s11: cleaning residues and polymers remained on the surface of the wafer 2 after etching by using a hydroxylamine photoresist remover;
s12: turning the chip over to make the back of the wafer 2 attached to the blue film frame 9;
s13: the adhesive layer 3 is dissociated by ultraviolet irradiation or heat treatment or laser mode to release the viscosity of the layer, and the glass carrier plate 1 is removed from the wafer 2;
s14: the adhesive layer 3 on the wafer 2 is cleaned with an organic solvent to complete the production of the die with the copper heat sink.
In step S2, after the wafer 2 is polished, the thickness of the wafer 2 is 30-300 μm.
In step S4, the adhesion layer is a titanium layer, the titanium layer has a thickness of 1-2 microns, the barrier layer is a nickel layer, and the nickel layer has a thickness of 1-2 microns.
In step S7, the thick copper film 8 has a thickness of 5 to 50 μm.
In step S8, the photoresist layer 4 on the inter-grain scribe line on the back surface of the wafer 2 is removed by using an organic solvent.
The thin wafer cooling fin manufactured by the thin wafer cooling fin manufacturing process is adopted.
The scheme can safely and nondestructively cut the thin wafer with the copper heat dissipation junction structure; according to the scheme, the thick copper film is used as a mask plate and can be directly etched, the thickness of the thick copper film is far greater than that of the copper seed layer, the adhesion layer and the barrier layer, and the loss of the thick copper film is very little after the copper seed layer, the adhesion layer and the barrier layer are etched during etching; and the etching ratio of the thick copper mold to the wafer is about 1: 100, the thick copper film can be directly used as a mask for wafer etching to cut crystal grains, so that the process flow is saved, and the production efficiency and the yield are improved. The scheme solves the problem that the radiating fins with enough thickness cannot be arranged on the thin wafer in the prior art.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (6)
1. A manufacturing process of a thin wafer heat sink is characterized in that:
the method comprises the following steps:
s1: bonding the front surface of the wafer with the glass carrier plate by using an adhesive after the front surface process of the wafer is finished;
s2: grinding and etching the back of the wafer;
s3: coating photoresist on the back of the wafer, and performing a yellow light process and an ion implantation process on the back of the wafer;
s4: sequentially generating an adhesion layer and a barrier layer on the back surface of the wafer through one of a sputtering process or an evaporation process;
s5: generating a copper seed layer on the barrier layer by one of sputtering process or evaporation process;
s6: coating a photoresist layer on the back of the wafer, performing a yellow light process, developing to generate a mask plate pattern, and protecting the inter-wafer cutting channel in a photoresist coating mode;
s7: carrying out an electrochemical plating process on the back of the wafer, and plating a thick copper film on the copper seed layer;
s8: removing the photoresist layer on the dicing streets on the back surface of the wafer by using oxygen plasma to expose the streets between the wafers;
s9: removing the metal layers of copper, nickel and titanium on the inter-grain cutting path by wet etching by taking the thick copper film as a mask, and stopping etching on the surface of the silicon wafer;
s10: etching the scribe lines between the grains using sulfur fluoride or other fluorine-containing plasma with the thick copper film as a mask, the etching being stopped at the adhesive layer;
s11: cleaning residues and polymers remained on the surface of the wafer after etching by using a hydroxylamine photoresist remover;
s12: turning over the chip to make the back of the wafer attached to the blue film frame;
s13: the viscidity of the adhesive layer release layer is dissociated through ultraviolet irradiation or heat treatment or laser mode, and the glass carrier plate is removed from the wafer;
s14: and cleaning the adhesive layer on the wafer by using an organic solvent to complete the production of the crystal grain with the copper radiating fin.
2. The process of claim 1, wherein: in step S2, the wafer thickness is 30-300 μm after the wafer is ground.
3. The process of claim 1, wherein: in step S4, the adhesion layer is a titanium layer, the titanium layer has a thickness of 1-2 microns, the barrier layer is a nickel layer, and the nickel layer has a thickness of 1-2 microns.
4. The process of claim 1, wherein: in step S7, the thick copper film has a thickness of 5-50 microns.
5. The process of claim 1, wherein: in step S8, the photoresist layer on the inter-wafer scribe line on the back side of the wafer is removed by using an organic solvent.
6. The thin wafer heat sink manufactured by the thin wafer heat sink manufacturing process according to any one of claims 1 to 5.
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| CN202010478956.8A CN111599753B (en) | 2020-05-29 | 2020-05-29 | Thin wafer cooling fin and manufacturing process thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658857A (en) * | 2021-08-16 | 2021-11-16 | 上海新微半导体有限公司 | Process method for realizing cutting channels on back of thin wafer |
| CN117936393A (en) * | 2024-03-21 | 2024-04-26 | 成都电科星拓科技有限公司 | Method for manufacturing heat dissipation cover on back of single chip and packaging method |
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| CN107087350A (en) * | 2017-04-07 | 2017-08-22 | 江门崇达电路技术有限公司 | A kind of preparation method of high heat sink |
| US10490480B1 (en) * | 2018-08-21 | 2019-11-26 | International Business Machines Corporation | Copper microcooler structure and fabrication |
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| US4080722A (en) * | 1976-03-22 | 1978-03-28 | Rca Corporation | Method of manufacturing semiconductor devices having a copper heat capacitor and/or copper heat sink |
| US20030148653A1 (en) * | 2002-01-03 | 2003-08-07 | Bernd Thyzel | Power electronics unit |
| US20050026395A1 (en) * | 2002-01-16 | 2005-02-03 | Micron Technology, Inc. | Fabrication of stacked microelectronic devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113658857A (en) * | 2021-08-16 | 2021-11-16 | 上海新微半导体有限公司 | Process method for realizing cutting channels on back of thin wafer |
| CN117936393A (en) * | 2024-03-21 | 2024-04-26 | 成都电科星拓科技有限公司 | Method for manufacturing heat dissipation cover on back of single chip and packaging method |
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| CN111599753B (en) | 2023-10-13 |
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