CN111584521B - Array substrate, manufacturing method thereof and display panel - Google Patents

Abstract

The invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate provided by the invention includes a substrate and a thin film transistor arranged on the substrate. The thin film transistor includes a gate electrode, a gate insulating layer, a source electrode and a metal oxide pattern. The source electrode and the metal oxide pattern are arranged in the same layer, and the metal oxide There are overlapping portions between the physical pattern and the source electrode, and the gate insulating layer is provided between the gate electrode and the source electrode in the stacking direction of the array substrate; wherein, the metal oxide pattern includes a first portion located in the middle area and a first portion located in the first portion. The second part on both sides, the source electrode and the second part are in contact, the first part is semiconductorized to form an active layer, and the second part serves as a pixel electrode. The thin film transistor in the array substrate provided by the present invention has better performance, and the production process of the array substrate is relatively simple and the production cost is low.

Description

Array substrate and manufacturing method thereof, display panel

Technical field

The present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.

Background technique

With the development of display technology, flat display devices such as Liquid Crystal Display (LCD) are widely used in mobile phones, TVs, and personal computers due to their advantages such as high image quality, power saving, thin body, and no radiation. It has become the mainstream display device in various consumer electronic products such as digital assistants and notebook computers.

A liquid crystal display panel usually consists of an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate. By applying a driving voltage between the array substrate and the color filter substrate, the rotation of the liquid crystal molecules can be controlled. , thereby refracting the light from the backlight module to produce a picture. Among them, the array substrate usually includes a glass substrate and a thin film transistor disposed on the glass substrate. The thin film transistor includes a gate electrode, a source electrode, a drain electrode, a semiconductor layer and a pixel electrode; the source electrode, drain electrode and semiconductor layer are usually located in the same layer. The source and drain are located on both sides of the semiconductor layer, and the source and drain are connected through the semiconductor layer. The three form an active island pattern; the gate electrode and the active island pattern are set on different layers, and the layer where the gate electrode is located is connected to the active island pattern. The layers where the island patterns are located are separated by a gate insulating layer; the pixel electrodes can be placed on the same layer or in different layers as the active island patterns, and the pixel electrodes are connected to the drain electrodes.

However, in array substrates in the prior art, metal ions in the source electrode will diffuse to the semiconductor layer, which will affect the semiconductor layer, thereby affecting the characteristics of the thin film transistor.

Contents of the invention

The invention provides an array substrate, a manufacturing method thereof, and a display panel. The thin film transistors in the array substrate have better performance, and the production process of the array substrate is relatively simple and the production cost is low.

In a first aspect, the present invention provides an array substrate. The array substrate includes a substrate and a thin film transistor arranged on the substrate. The thin film transistor includes a gate electrode, a gate insulating layer, a source electrode and a metal oxide pattern. The source electrode and the metal oxide The patterns are arranged on the same layer, and the metal oxide pattern and the source electrode have overlapping parts. The gate insulating layer is arranged between the gate electrode and the source electrode in the stacking direction of the array substrate; wherein, the metal oxide pattern includes a layer located in the middle The first part of the region opposite to the gate electrode and the second part located on both sides of the first part, the first part is semiconductorized to form an active layer, the source electrode and the second part close to the source electrode have overlapping parts, and the part far from the source electrode The second part serves as the pixel electrode.

In a possible implementation, the gate electrode is disposed on the substrate, the gate insulating layer covers the substrate and the gate electrode, and the source electrode and the metal oxide pattern are disposed on the gate insulating layer.

In a possible implementation, a passivation layer is also included, the passivation layer is provided on the gate insulating layer, and the passivation layer covers the source electrode and the metal oxide pattern; wherein, the passivation layer includes layers stacked on the gate insulating layer in sequence. A first passivation layer and a second passivation layer, the first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.

In a possible implementation, the source electrode and the metal oxide pattern are disposed on the substrate, the gate insulating layer covers the substrate and the source electrode and the metal oxide pattern, and the gate electrode is disposed on the gate insulating layer.

In a possible implementation, the array substrate further includes an insulating substrate layer, the insulating substrate layer is provided between the substrate and the gate insulating layer, the source electrode and the metal oxide pattern are provided on the insulating substrate layer; wherein the insulating substrate layer includes A first insulating substrate layer and a second insulating substrate layer are sequentially stacked on the substrate. The first insulating substrate layer is a silicon nitride layer, and the second insulating substrate layer is a silicon oxide layer.

In a possible implementation, the array substrate further includes a drain electrode, and the second part of the metal oxide pattern away from the source electrode includes a first section and a second section, the first section is connected to the first section, and the second section is connected to the second section. There is a gap between one section and the drain electrode is connected between the first section and the second section, and the second section serves as the pixel electrode.

In a second aspect, the present invention provides a method for manufacturing an array substrate. The manufacturing method includes the following steps:

forming a gate on the substrate;

A gate insulating layer is formed on the substrate, and the gate insulating layer covers the gate electrode;

Forming a source electrode and a metal oxide pattern on the gate insulating layer; wherein the metal oxide pattern includes a first part located in the middle area and a second part located on both sides of the first part, between the source electrode and a second part close to the source electrode There are mutually overlapping parts, and the second part away from the source electrode serves as the pixel electrode;

Semiconducting the first portion of the metal oxide pattern to form an active layer;

A passivation layer is formed on the gate insulating layer, and the passivation layer covers the source electrode and the metal oxide pattern.

In a third aspect, the present invention provides a method for manufacturing an array substrate. The manufacturing method includes the following steps:

forming an insulating substrate layer on the substrate;

Forming a source electrode and a metal oxide pattern on the insulating substrate layer; wherein the metal oxide pattern includes a first part located in the middle area and a second part located on both sides of the first part, between the source electrode and a second part close to the source electrode There are mutually overlapping parts, and the second part away from the source electrode serves as the pixel electrode;

Semiconducting the first portion of the metal oxide pattern to form an active layer;

A gate insulating layer is formed on the insulating substrate layer, and the gate insulating layer covers the source electrode and the metal oxide pattern;

A gate electrode is formed on the gate insulating layer.

In a possible implementation, forming the source electrode and metal oxide pattern specifically includes:

Depositing a source metal layer on the gate insulating layer or insulating substrate layer;

Perform photolithography process on the source metal layer to form the source;

Deposit a metal oxide layer on the gate insulating layer or insulating substrate layer, and the metal oxide layer covers the source electrode;

A photolithography process is performed on the metal oxide layer to form a metal oxide pattern; wherein the metal oxide pattern includes a first part located in the middle area and a second part located on both sides of the first part, between the source electrode and a second part close to the source electrode. have overlapping parts.

In a possible implementation, forming the source electrode and metal oxide pattern specifically includes:

Deposit source and drain metal layers on the gate insulating layer or insulating substrate layer;

A photolithography process is performed on the source and drain metal layers to form source and drain electrodes; wherein, there is a gap between the source and drain electrodes;

Deposit a metal oxide layer on the gate insulating layer or insulating substrate layer, and the metal oxide layer covers the source and drain electrodes;

A photolithography process is performed on the metal oxide layer to form a metal oxide pattern; wherein the metal oxide pattern includes a first part located in the middle area and a second part located on both sides of the first part, between the source electrode and a second part close to the source electrode. There are mutually overlapping parts. The second part away from the source includes a first section and a second section. The first section is connected to the first section. There is a gap between the second section and the first section. The drain is connected to the first section. between the second paragraph.

In a fourth aspect, the present invention provides a display panel, which includes the array substrate as described above.

The present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate is provided with a source electrode and a metal oxide pattern in the same structural layer, and the metal oxide pattern and the source electrode have overlapping portions, wherein, The metal oxide pattern includes a first part and a second part. The first part is located in the middle area of the metal oxide pattern, and the second part is located on both sides of the first part. The source electrode is in contact with the second part corresponding to it; by connecting the metal oxide pattern The second part serves as the pixel electrode, and the first part of the metal oxide pattern is semiconductorized, and the first part is used as the active layer, so that the source can transmit the electrical signal to the pixel electrode through the active layer; at the same time, because There are second parts on both sides of the active layer, that is, the second part separates the source and the active layer, so the metal ions in the source will not diffuse to the active layer and will not affect the semiconductor of the active layer. characteristics, which can improve the performance of thin film transistors; in addition, the production process of the array substrate is relatively simple and the production cost is low.

Description of the drawings

In order to more clearly illustrate the technical solutions of the present invention or the prior art, a brief introduction will be made below to the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are the drawings of the present invention. For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting any creative effort.

Figure 1 is a schematic structural diagram of an array substrate provided in Embodiment 1 of the present invention;

Figure 2 is a schematic structural diagram of a second array substrate provided by Embodiment 1 of the present invention;

Figure 3 is a schematic structural diagram of a third array substrate provided by Embodiment 1 of the present invention;

Figure 4 is a schematic structural diagram of a fourth array substrate provided in Embodiment 1 of the present invention;

Figure 5 is a schematic flow chart of a method for manufacturing an array substrate provided in Embodiment 2 of the present invention;

Figure 6 is a schematic structural diagram of forming a gate electrode on a substrate according to Embodiment 2 of the present invention;

Figure 7 is a schematic structural diagram of forming a gate insulating layer on a gate according to Embodiment 2 of the present invention;

Figure 8 is a schematic structural diagram of forming a source electrode and a metal oxide pattern on a gate insulating layer according to Embodiment 2 of the present invention;

Figure 9 is a schematic structural diagram of forming a passivation layer on a source electrode and a metal oxide pattern according to Embodiment 2 of the present invention;

Figure 10 is a schematic flow chart of another method for manufacturing an array substrate provided in Embodiment 3 of the present invention;

Figure 11 is a schematic structural diagram of forming an insulating substrate layer on a substrate according to Embodiment 3 of the present invention;

Figure 12 is a schematic structural diagram of forming source electrodes and metal oxide patterns on an insulating substrate layer according to Embodiment 3 of the present invention;

Figure 13 is a schematic structural diagram of forming a gate insulating layer on a source electrode and a metal oxide pattern according to Embodiment 3 of the present invention;

Figure 14 is a schematic structural diagram of forming a gate electrode on a gate insulating layer according to Embodiment 3 of the present invention;

Figure 15 is a flow chart for forming source electrodes and metal oxide patterns according to Embodiment 4 of the present invention;

FIG. 16 is another flow chart for forming source electrodes and metal oxide patterns provided in Embodiment 4 of the present invention.

Explanation of reference symbols:

100-array substrate; 110-substrate; 120-gate; 130-gate insulating layer; 131-first gate insulating layer; 132-second gate insulating layer; 140-source; 150-metal oxide pattern; 151- First part; 151a-active layer; 152-second part; 152a-pixel electrode; 1521-first section; 1522-second section; 160-passivation layer; 161-first passivation layer; 162-second Passivation layer; 170-insulating substrate layer; 171-first insulating substrate layer; 172-second insulating substrate layer; 180-drain; a-first metal layer; b-second metal layer.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention. , not all examples. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

Embodiment 1

Figure 1 is a schematic structural diagram of an array substrate provided in Embodiment 1 of the present invention; Figure 2 is a schematic structural diagram of a second array substrate provided in Embodiment 1 of the present invention; Figure 3 is a third array substrate provided in Embodiment 1 of the present invention. A schematic structural diagram of an array substrate; FIG. 4 is a schematic structural diagram of a fourth array substrate provided in Embodiment 1 of the present invention.

As shown in FIGS. 1 to 4 , this embodiment provides an array substrate 100 . The array substrate 100 includes a substrate 110 and a thin film transistor disposed on the substrate 110 . The thin film transistor includes a gate electrode 120 , a gate insulating layer 130 , and a source electrode. 140 and the metal oxide pattern 150, the source electrode 140 and the metal oxide pattern 150 are arranged in the same layer, and there are overlapping portions between the metal oxide pattern 150 and the source electrode 140. The gate insulating layer 130 is in the stacking direction of the array substrate 100. is provided between the gate electrode 120 and the source electrode 140; wherein, the metal oxide pattern 150 includes a first part 151 located in the middle area opposite to the gate electrode 120 and a second part 152 located on both sides of the first part 151. The first part 151 is a semiconductor The active layer 151a is formed, the source electrode 140 and the second portion 152 close to the source electrode 140 have overlapping portions, and the second portion 152 far away from the source electrode 140 serves as the pixel electrode 152a.

As shown in FIGS. 1 to 4 , the array substrate 100 includes a substrate 110 . The substrate 110 serves as the basic carrying structure of the array substrate 100 . The remaining hierarchical structures of the array substrate 100 are formed on the substrate 110 . The substrate 110 may be quartz or quartz. Glass base board.

In this embodiment, it should be understood that for the array substrate 100 used in the liquid crystal display panel, multiple data lines and scan lines are usually provided in the pixel area of the array substrate 100. The multiple data lines and the multiple scan lines connect the pixels to each other. The area is divided into a plurality of sub-pixels, and at least one thin film transistor is provided in each sub-pixel.

Specifically, multiple data lines are arranged in parallel and spaced apart from each other, multiple scanning lines are arranged in parallel and spaced apart from each other, and the data lines and scanning lines are arranged in a criss-cross direction in space. Taking the shape of the array substrate 100 as a rectangle as an example, the data lines can extend along the width direction of the array substrate 100, and the scan lines can extend along the length direction of the array substrate 100. Through the interlacing of the data lines and scan lines, on the array substrate 100 Multiple sub-pixels arranged in a matrix are formed.

Among them, the driving method of the thin film transistors by the data lines and scanning lines can adopt existing driving methods such as progressive scanning, which will not be described again here.

As shown in FIGS. 1 to 4 , in the array substrate 100 provided by this embodiment, the thin film transistor is disposed on the substrate 110 . The thin film transistor (abbreviation: TFT device) includes a gate electrode 120 , a gate insulating layer 130 , a source electrode 140 and a metal Oxide graphics150. Among them, the metal oxide pattern 150 includes a pixel electrode 152a and an active layer 151a.

Specifically, the source electrode 140 and the metal oxide pattern 150 are arranged in the same layer, and the gate electrode 120 is spaced apart from the source electrode 140 and the metal oxide pattern 150 in different structural layers, wherein the gate insulating layer 130 is spaced between the source electrode 140 and the gate electrode 140 . between the gate electrode 120, so that the gate electrode 120 and the source electrode 140 can be insulated from each other.

In practical applications, for each sub-pixel, the source 140 can be set corresponding to the data line, that is, the source 140 and the data line are set on the same layer. The source 140 can be a branch connected to the data line, and each sub-pixel has a source. 140; Similarly, the gate 120 can be arranged corresponding to the scanning line, that is, the gate 120 and the scanning line are arranged on the same layer. The gate 120 can be a branch connected to the scanning line, and each sub-pixel has a gate 120.

It can be understood that after the scan line is energized to generate an electrical signal, the electrical signal is transmitted to the gate 120. The gate 120 is charged to conduct the active layer 151a spaced therefrom through the gate insulating layer 130, so that the active layer 151a can The electrical signal on the source electrode 140 is transmitted to the pixel electrode 152a; when the scan line is not energized, the active layer 151a maintains its semiconductor characteristics.

In this embodiment, the metal oxide pattern 150 and the source electrode 140 have overlapping portions, that is, the opposite sides of the metal oxide pattern 150 and the source electrode 140 are overlapped with each other, so that the source electrode 140 can conduct electricity. The signal is passed to metal oxide pattern 150. The metal oxide pattern 150 includes a first part 151 and a second part 152. The first part 151 is located in the middle area of the metal oxide pattern 150, and both sides of the first part 151 are the second parts 152 of the metal oxide pattern 150.

Specifically, the second part 152 of the metal oxide pattern 150 opposite to the source electrode 140 is in contact with the source electrode 140, and the second part 152 of the metal oxide pattern 150 away from the source electrode 140 can serve as the pixel electrode 152a, and is located on the metal oxide The first part 151 of the middle area of the object pattern 150 forms the active layer 151a, so that the source electrode 140 transmits the electrical signal to the active layer 151a, and transmits the electrical signal to the metal oxide pattern serving as the pixel electrode 152a through the active layer 151a. The second part 152 of 150 realizes charging and discharging the pixel electrode 152a in this way.

The metal oxide pattern 150 serves as a conductor. If the first portion 151 of the metal oxide pattern 150 is to form the active layer 151a, this can be achieved by semiconductorizing the first portion 151. For example, the first part 151 may be semiconductorized by irradiating the first part 151 with ultraviolet light or plasma implantation.

In the prior art, the active layer 151a is usually in direct contact with the source electrode 140. For example, one side of the source electrode 140 covers the active layer 151a, or one side of the active layer 151a covers the source electrode 140. For this structure, metal ions such as Cu and Al in the source electrode 140 will directly diffuse to the active layer 151a in contact with it. After absorbing these metal ions, the active layer 151a may become a conductor, which will affect the active layer 151a. The semiconductor properties of layer 151a further affect the characteristics of the TFT device.

As shown in Figure 1, in this embodiment, the first part 151 of the metal oxide pattern 150 located in the middle area is semiconductorized to form an active layer 151a, and the source electrode 140 is in contact with the second part 152 of the metal oxide pattern 150. That is, the active layer 151a and the source electrode 140 are separated by the second part 152, so that the metal ions such as Cu and Al in the source electrode 140 can only diffuse to the second part 152 in contact with it, and the second part 152 will absorb the ions from the second part 152. The metal ions diffused from the source 140.

In this way, the metal ions in the source electrode 140 cannot diffuse to the active layer 151a, and thus will not affect the active layer 151a. The second portion 152 of the metal oxide pattern 150 is spaced between the source electrode 140 and the active layer 151a. In this way, the active layer 151a can be protected, so that the active layer 151a can maintain good semiconductor characteristics, thereby improving the performance of the TFT device.

For example, the material forming the metal oxide pattern 150 may be indium tin oxide (ITO), that is, the metal oxide pattern 150 is an ITO transparent conductive layer. Among them, the second portion 152 of the ITO transparent conductive layer away from the source electrode 140 serves as the pixel electrode 152a. In some other embodiments, the metal oxide pattern 150 can also be formed using other metal oxide materials, which is not limited in this embodiment.

In this embodiment, the metal oxide pattern 150 is divided into a first part 151 and a second part 152. The first part 151 is located in the middle area, and the second part 152 is located on both sides of the first part 151. The second part 152 opposite to the source electrode 140 and There are mutually overlapping regions between the source electrodes 140. The second portion 152 away from the source electrode 140 serves as the pixel electrode 152a, and the first portion 151 is semiconductorized to form the active layer 151a. In this way, not only can the source electrode 140 transmit electrical signals to the pixel electrode 152a through the active layer 151a, thereby charging and discharging the pixel electrode 152a; at the same time, the active layer 151a and the source electrode 140 can be separated by the second part 152. The diffusion of metal ions in the source electrode 140 to the active layer 151a is hindered to protect the semiconductor properties of the active layer 151a, thereby improving the performance of the TFT device.

In addition, in this embodiment, only three photolithography processes are required to form each hierarchical structure of the array substrate 100 . Specifically, forming the gate electrode 120 on the substrate 110 requires a photolithography process, forming the source electrode 140 requires a photolithography process, and forming the metal oxide pattern 150 requires a photolithography process.

Compared with the formation process of the array substrate 100 in the prior art, the array substrate 100 of this embodiment undergoes fewer photolithography processes and has a simpler production process, which can reduce the production cost of the array substrate 100 .

It should be understood that in this embodiment, three photolithography processes are required to form each hierarchical structure of the array substrate 100. However, if the TFT device is to be driven, the array substrate 100 also needs to be provided with an external device that overlaps with the external device. For example, a reserved hole that can expose the gate electrode 120 and the source electrode 140 needs to be reserved in the array substrate 100, and the reserved hole connected to the outside is provided on the gate electrode 120 and the source electrode 140 to connect the external The electrical signal is conducted to the array substrate 100 to realize driving of the TFT device.

Since reserved holes need to be provided on the gate electrode 120 and the source electrode 140 , it is inevitable to add a process of etching the reserved holes, and therefore also need to add a photolithography process.

As shown in FIGS. 1 and 3 , in some embodiments, in the array substrate 100 in this embodiment, in the hierarchical structure where the source electrode 140 and the metal oxide pattern 150 are located, only the source electrode 140 may be provided, and no source electrode 140 may be provided. The drain electrode 180 and the active layer 151a formed by semiconductorizing the first part 151 of the metal oxide pattern 150 directly contact the second part 152 serving as the pixel electrode 152a, so the electrical signal of the source electrode 140 is directly transmitted to the pixel electrode 152a through the semiconductor layer. .

As shown in FIGS. 2 and 4 , in some other implementations, in the array substrate 100 of this embodiment, a drain electrode 180 may also be provided in the hierarchical structure where the source electrode 140 and the metal oxide pattern 150 are located. 180 is spaced apart from the source electrode 140, and the electrical signal is transmitted to the pixel electrode 152a through the drain electrode 180.

For a structure in which the drain electrode 180 is provided in the array substrate 100 , the metal oxide pattern 150 provided may include a portion located between the source electrode 140 and the drain electrode 180 and a portion adjacent to one side of the drain electrode 180 . Among them, the first portion 151 of the metal oxide pattern 150 that is semiconductorized into the active layer 151a is located in the interval between the source electrode 140 and the drain electrode 180, and is located in the interval as well as the second portions on both sides of the first portion 151. 152, the source 140 and the second part 152 have mutually overlapping areas; the second part 152 includes a first section 1521 and a second section 1522. The first section 1521 is a region corresponding to the two sides connected to the first part 151, and the second section 152 1522 is disposed on one side of the drain electrode 180, and there is a gap between the second section 1522 and the first section 1521. The drain electrode 180 is located between the first section 1521 and the second section 1522 connected to the first part 151, so that The second section 1522 serves as the pixel electrode 152a.

For a structure with a drain electrode 180, the electrical signal is transmitted from the source electrode 140 to the active layer 151a. The active layer 151a transmits the electrical signal to the drain electrode 180, and the drain electrode 180 then transmits the electrical signal to the pixel electrode 152a. In this way to charge and discharge the pixel electrode 152a.

In addition, in this embodiment, for the array substrate 100 provided with the drain electrode 180, the drain electrode 180 and the source electrode 140 can be formed through the same photolithography process, and although the second part 152 of the metal oxide pattern 150 includes the first segment 1521 and the second section 1522, but the metal oxide pattern 150 also only needs one photolithography process to form, so it does not increase the number of photolithography processes for the array substrate 100. The manufacturing process of the array substrate 100 is the same as that of the array substrate 100 without the drain electrode 180. The manufacturing process is the same, the production process is also relatively simple, and the production cost of the array substrate 100 is low.

The following takes the hierarchical structure of the array substrate 100 without the drain electrode 180 as an example. For the substrate 110 with the drain electrode 180 , the following embodiments are also applicable and will not be described again here.

As shown in FIGS. 1 and 2 , in this embodiment, the TFT device in the array substrate 100 may have a bottom gate structure. For the array substrate 100 of the bottom gate structure, the gate electrode 120 may be disposed on the substrate 110 , the gate insulating layer 130 covers the substrate 110 and the gate electrode 120 , and the source electrode 140 and the metal oxide pattern 150 are disposed on the gate insulating layer 130 .

In a possible implementation, a passivation layer 160 may also be provided on the gate insulating layer 130 , and the passivation layer 160 covers the source electrode 140 and the metal oxide pattern 150 . The passivation layer 160 is used to protect the source electrode 140 below it and the pixel electrode 152a and the active layer 151a in the metal oxide pattern 150. The passivation layer 160 can be used as the outermost structure of the array substrate 100 and can be used as an array substrate. 100% protective layer structure.

Specifically, the passivation layer 160 may include a first passivation layer 161 and a second passivation layer 162 sequentially stacked on the gate insulating layer 130. The first passivation layer 161 may be a silicon oxide layer, and the second passivation layer 162 It can be a silicon nitride layer. The first passivation layer 161 directly covers the source electrode 140 and the metal oxide pattern 150, and the second passivation layer 162 covers the first passivation layer 161. By setting the first passivation layer 161 and the second passivation layer 162 to The source electrode 140 and the metal oxide pattern 150 have better protection.

The first passivation layer 161 in the passivation layer 160 is a silicon oxide layer, and the second passivation layer 162 is a silicon nitride layer. The second passivation layer 162 can be used as the outermost structure of the array substrate 100, or the second passivation layer 162 is closer to the outer surface of the array substrate 100. By setting the second passivation layer 162 as a silicon nitride layer, it can Isolate external water vapor to prevent the water vapor from affecting the metal oxide pattern 150 and the source electrode 140; the first passivation layer 161 directly covers the metal oxide pattern 150 and the source electrode 140. By setting the first passivation layer 161 to The denser silicon oxide layer, the oxygen atoms rich in the silicon oxide layer can diffuse into the active layer 151a of the metal oxide pattern 150, supplement the oxygen atoms in the active layer 151a, and maintain the semiconductor properties of the active layer 151a characteristic.

As shown in FIGS. 3 and 4 , in this embodiment, the TFT device in the array substrate 100 may also have a top-gate structure. For the array substrate 100 with a top gate structure, the source electrode 140 and the metal oxide pattern 150 may be disposed on the substrate 110 , the gate insulating layer 130 may cover the substrate 110 and the source electrode 140 and the metal oxide pattern 150 , and the gate electrode 120 may be disposed on the gate on the insulating layer 130.

For a TFT device with a top gate structure, the gate electrode 120 may be located above the source electrode 140 and the metal oxide pattern 150. The gate insulating layer 130 covers the source electrode 140 and the metal oxide pattern 150. The gate electrode 120 is disposed on the gate insulating layer. 130 on. Among them, the source electrode 140 and the metal oxide pattern 150 can be directly disposed on the substrate 110. In the stacking direction of the array substrate 100, the substrate 110, the source electrode 140 and the metal oxide pattern 150, the gate insulating layer 130, and the gate electrode are in sequence. 120.

Regardless of whether it is a bottom gate structure or a top gate structure, similar to the protective effect of the passivation layer 160 on the source electrode 140 and the metal oxide pattern 150 , the gate insulating layer 130 may include a first gate insulating layer 131 and a second gate insulating layer 132 , the first gate insulating layer 131 is relatively located outside the array substrate 100; wherein, for the bottom gate structure, the first gate insulating layer 131 is closer to the substrate 110, and for the top gate structure, the first gate insulating layer 131 is closer to the gate electrode 120; The second gate insulating layer 132 is relatively close to the source electrode 140 and the structural layer where the metal oxide pattern 150 is located; wherein, for the bottom gate structure, the second gate insulating layer 132 can cover the first gate insulating layer 131, and for the top gate structure Structure, the second gate insulating layer 132 directly covers the source electrode 140 and the metal oxide pattern 150, and the first gate insulating layer 131 covers the second gate insulating layer 132.

Among them, the first gate insulating layer 131 is a silicon nitride layer. The silicon nitride layer has a good effect of isolating water vapor. It can isolate the water vapor outside the array substrate 100 or from the substrate 110 and prevent water vapor from entering the active layer 151a. The active layer 151a is protected from moisture.

The second gate insulating layer 132 is a silicon oxide layer. The silicon oxide layer is denser and contains more oxygen elements. If the oxygen atoms in the active layer 151a combine with the metal ions in the source electrode 140 or the free hydrogen ions present in the passivation layer 160, thereby causing the active layer 151a to lose oxygen atoms and become a conductor, the active layer 151a If the semiconductor properties are lost, the oxygen atoms in the second gate insulating layer 132 can diffuse into the active layer 151a, supplementing the oxygen atoms in the active layer 151a, so that the active layer 151a maintains its semiconductor properties.

As a passive light-emitting device, the liquid crystal display panel needs to be provided with a backlight source on the back of the display screen. If the source electrode 140 and the metal oxide pattern 150 are directly placed on the substrate 110, the light from the backlight source will pass through the substrate 110 and illuminate the metal oxide pattern 150. , when light irradiates the active layer 151a in the metal oxide pattern 150, photogenerated carriers will be generated on the active layer 151a, which will affect the semiconductor characteristics of the active layer 151a, and in turn affect the off-state current of the TFT device. characteristic.

Therefore, in order to prevent the light from the backlight from directly irradiating the active layer 151a formed in the metal oxide pattern 150, in this embodiment, for the top gate structure, an insulating substrate layer 170 is also provided on the substrate 110. The insulating substrate layer 170 Located between the substrate 110 and the gate insulating layer 130, the source electrode 140 and the metal oxide pattern 150 are provided on the insulating substrate layer 170.

As shown in FIGS. 3 and 4 , by disposing the insulating substrate layer 170 on the substrate 110 , the source electrode 140 and the metal oxide pattern 150 are disposed on the insulating substrate layer 170 , so that the insulating substrate layer 170 is spaced between the substrate 110 and the metal oxide layer 170 . between the active layers 151a in the object pattern 150. The light from the backlight source passes through the substrate 110 and first irradiates to the insulating substrate layer 170. The insulating substrate layer 170 has a certain refractive index, which can scatter, diffusely reflect or reflect the light, and can attenuate the light energy, so that the light from the backlight source The irradiation will not be concentrated on the active layer 151a, thereby protecting the semiconductor characteristics of the active layer 151a and ensuring the off-state current characteristics of the thin film transistor.

As shown in FIGS. 3 and 4 , similar to the gate insulating layer 130 , the insulating substrate layer 170 may include a first insulating substrate layer 171 and a second insulating substrate layer 172 that are sequentially stacked on the substrate 110 . The first insulating substrate layer 171 is a silicon nitride layer, and the second insulating substrate layer 172 is a silicon oxide layer.

By disposing a silicon nitride layer as the first insulating substrate layer 171 on the substrate 110, the silicon nitride layer can isolate water vapor from outside the array substrate 100 or the substrate 110, and protect the active layer 151a in the metal oxide pattern 150 from water vapor. Impact: By covering the first insulating substrate layer 171 with a silicon oxide layer as the second insulating substrate layer 172, the source electrode 140 and the metal oxide pattern 150 are directly formed on the silicon oxide layer, and the density of the silicon oxide layer is better, where It is rich in oxygen elements, which can supplement the oxygen atoms in the active layer 151a, so that the active layer 151a maintains its semiconductor characteristics.

In addition, it should be noted that, as shown in FIGS. 1 to 4 , in this embodiment, whether it is a bottom gate structure or a top gate structure, in this embodiment, the source electrode 140 , the drain electrode 180 and the gate electrode 120 can all be composed of It consists of a stacked first metal layer a and a second metal layer b, wherein the metal in the first metal layer a at the bottom includes at least one of titanium and molybdenum, and the metal in the second metal layer b at the top includes At least one of copper and aluminum.

By providing two metal layers, the first metal layer a and the second metal layer b, as the source electrode 140, the drain electrode 180 and the gate electrode 120, the second metal layer b is stacked on the first metal layer a, and the first metal layer a It is a single metal layer or a composite metal layer such as titanium or molybdenum, and the second metal layer b is a single metal layer or a composite metal layer such as copper or aluminum. Among them, the first metal layer a located at the bottom is mainly used to make the source electrode 140, the drain electrode 180 or the gate electrode 120 more firmly connected to its underlying structure, and to enhance the connection between the source electrode 140, the drain electrode 180 or the gate electrode 120 and its underlying structure. Connection strength; the second metal layer b located on the top layer is mainly used to exert the conductivity of the source electrode 140, the drain electrode 180 and the gate electrode 120 to ensure the performance of the TFT device.

In the array substrate provided by this embodiment, the source electrode and the metal oxide pattern are provided in the same structural layer, and the metal oxide pattern and the source electrode have overlapping parts, wherein the metal oxide pattern includes a first part and a third part. Two parts, the first part is located in the middle area of the metal oxide pattern, the second part is located on both sides of the first part, the source electrode is in contact with the second part corresponding to it; by using the second part of the metal oxide pattern as the pixel electrode, and The first part of the metal oxide pattern is semiconductorized and used as the active layer, so that the source can transmit the electrical signal to the pixel electrode through the active layer; at the same time, since both sides of the active layer are The second part separates the source electrode from the active layer, so the metal ions in the source electrode will not diffuse to the active layer and will not affect the semiconductor properties of the active layer, thereby improving the performance of the thin film transistor. ; In addition, the production process of the array substrate is relatively simple and the production cost is low.

Embodiment 2

Figure 5 is a schematic flow diagram of a method for manufacturing an array substrate provided in Embodiment 2 of the present invention; Figure 6 is a schematic structural diagram of forming a gate electrode on a substrate provided in Embodiment 2 of the present invention; Figure 7 is provided in Embodiment 2 of the present invention Figure 8 is a schematic structural diagram of forming a gate insulating layer on a gate electrode; Figure 8 is a schematic structural diagram of forming a source electrode and a metal oxide pattern on a gate insulating layer according to Embodiment 2 of the present invention; Figure 9 is a schematic diagram of a structure provided by Embodiment 2 of the present invention. Schematic diagram of the structure of forming a passivation layer on the source electrode and metal oxide pattern.

This embodiment provides a method for manufacturing an array substrate 100, which is used to manufacture the array substrate 100 with the bottom gate structure described in Embodiment 1. The structure, function and working principle of the array substrate 100 are introduced in detail in Embodiment 1 and will not be described again here.

As shown in Figure 5, for an array substrate 100 with a bottom gate structure, the manufacturing method of the array substrate 100 includes the following steps:

S1a. Form the gate 120 on the substrate 110.

As shown in FIG. 6 , the gate electrode 120120 is first formed on the substrate 110110 . Specifically, a gate metal layer is first deposited on the substrate 110, and then the gate metal layer is formed into a patterned gate electrode 120 through a photolithography process. Wherein, depositing the gate metal layer includes sequentially depositing a first metal layer a and a second metal layer b on the substrate 110. The first metal layer a can be a single metal layer such as Ti or Mo or a composite metal layer, and the second metal layer b It can be a single metal layer such as Cu or Al or a composite metal layer.

The gate metal layer is subjected to a photolithography process to form the gate 120. The specific process may be as follows: first, a layer of photoresist is coated on the gate metal layer, and a mask is set above the gate metal layer. The mask is provided with In the light-transmitting area and the light-impermeable area, ultraviolet light irradiates the surface of the photoresist layer through the mask, causing a chemical reaction in the photoresist in the exposed area of the photoresist layer, and then dissolves and removes the photoresist in the exposed area through development technology. (positive photoresist) or photoresist in unexposed areas (negative photoresist); in this way, the remaining photoresist in the photoresist layer only covers the area corresponding to the gate electrode 120 in the gate metal layer, and the gate electrode Other areas of the metal layer are exposed. At this time, the exposed area of the gate metal layer is etched until only the gate 120 is left. Finally, the photoresist covering the gate 120 is removed, and then the substrate 110 can be formed. A gate 120 is formed thereon.

It can be understood that the exposure and development process of using ultraviolet light to illuminate the photoresist layer through the mask is to transfer the mask pattern on the mask to the photoresist layer to form the photoresist layer pattern, and to form the photoresist. The process of etching the areas not covered by the photoresist layer after layer patterning is the same as or similar to the above-mentioned process flow. The exposure, development and etching processes that occur after this embodiment will not be described again one by one.

S2a. Form a gate insulating layer 130 on the substrate 110, and the gate insulating layer 130 covers the gate electrode 120.

As shown in FIG. 7 , after the gate electrode 120 is formed on the substrate 110 , a gate insulating layer 130 is deposited on the substrate 110 . The gate insulating layer 130 can cover the entire substrate 110 ; wherein, the gate insulating layer 130 covers the gate electrode 120 . Depositing the gate insulating layer 130 includes sequentially depositing a first gate insulating layer 131 and a second gate insulating layer 132 on the substrate 110 .

S3a. Form the source electrode 140 and the metal oxide pattern 150 on the gate insulating layer 130; wherein the metal oxide pattern 150 includes a first part 151 located in the middle area and a second part 152 located on both sides of the first part 151. The source electrode 140 There is an overlapping portion with the second portion 152 close to the source electrode 140, and the second portion 152 far away from the source electrode 140 serves as the pixel electrode 152a.

As shown in FIG. 8 , after the gate insulating layer 130 is deposited on the substrate 110 , the source electrode 140 and the metal oxide pattern 150 are formed on the gate insulating layer 130 .

In a possible implementation, a source metal layer can be deposited on the gate insulating layer 130 first, and then a photolithography process is performed on the source metal layer to form a patterned source 140; and then a metal layer is deposited on the gate insulating layer 130. The metal oxide layer covers the source electrode 140, and a photolithography process is performed on the metal oxide layer to form a metal oxide pattern 150. Among them, the metal oxide pattern 150 includes a first part 151 and a second part 152 located on both sides of the first part 151. The second part 152 close to the source electrode 140 covers the source electrode 140, and the second part 152 far away from the source electrode 140 serves as a Pixel electrode 152a.

In another possible implementation, a metal oxide layer can be deposited on the gate insulating layer 130 first, and then a photolithography process is performed on the metal oxide layer to form the metal oxide pattern 150; and then a source is deposited on the gate insulating layer 130. The source metal layer covers the metal oxide pattern 150, and then a photolithography process is performed on the source metal layer to form a patterned source 140. In this way, the source electrode 140 covers the second portion 152 of the metal oxide pattern adjacent thereto.

S4a: Semiconducting the first portion 151 of the metal oxide pattern 150 to form an active layer 151a.

As shown in FIG. 8 , after the metal oxide pattern 150 is formed, the first part 151 of the metal oxide pattern 150 is irradiated with ultraviolet light or plasma implanted to semiconductorize the first part 151 to form an active layer 151 a.

For example, the first part 151 of the metal oxide pattern 150 is semiconductorized by plasma implantation. Specifically, the ashed photoresist pattern is used as a mask to semiconductorize the first part 151 of the metal oxide pattern 150 . , to form the active layer 151a.

Since the area corresponding to the active layer 151a in the ashed photoresist pattern is exposed and the rest is covered by the photoresist, the ashed photoresist pattern is used as a mask to perform the semiconductorization process, for example By performing ion implantation, the active layer 151a can be formed in the region where the active layer 151a is to be formed.

In the above scheme, the above-mentioned ashed photoresist pattern is used as a mask to perform ion implantation on the area of the metal oxide pattern 150 corresponding to the first part 151. In the ion implantation equipment, the vacuum degree of the ion implantation reaction chamber is It is 3×10 ^-4 Pa～8×10 ^-4 Pa, and the vacuum time is 30～50s. At a set chamber temperature, such as a temperature of 200°C to 300°C, the ion implantation energy is greater than or equal to 200KeV, and the implantation depth can be the same as the thickness of the metal oxide pattern 150 to serve as the second part of the pixel electrode 152a 152 is separated from the second portion 152 in contact with the source 140 .

The gas can be carbon source gas, etc. The ion implantation component contains at least one of Cr and HF, so that the ions have an injection energy of about 50KeV to change the atomic arrangement on the conductor surface and continuously recombine. The time of ion implantation is not limited. For example, if the thickness of the metal oxide pattern 150 is 40-90 nm, the implantation time may be 200-250 s.

As described above, ion implantation is performed and high-temperature annealing is performed. The annealing temperature may be, for example, 250° C. to 400° C., and the first portion 151 on the metal oxide pattern 150 can be semiconductorized into the active layer 151 a.

S5a. Form a passivation layer 160 on the gate insulating layer 130, and the passivation layer 160 covers the source electrode 140 and the metal oxide pattern 150.

As shown in FIG. 9 , after the source electrode 140 and the metal oxide pattern 150 are formed, and the first part 151 of the metal oxide pattern 150 forms the active layer 151a, a passivation layer 160 is deposited on the gate insulating layer 130 to passivate the Layer 160 covers source 140 and metal oxide pattern 150 . Wherein, depositing the passivation layer 160 on the gate insulating layer 130 includes sequentially depositing the first passivation layer 161 and the second passivation layer 162 on the gate insulating layer 130 .

Embodiment 3

Figure 10 is a schematic flow diagram of another method for manufacturing an array substrate 100 provided in the third embodiment of the present invention; Figure 11 is a schematic structural diagram of forming an insulating substrate layer 170 on the substrate 110 provided in the third embodiment of the present invention; Figure 12 is a schematic diagram of this method. The third embodiment of the invention provides a schematic structural diagram of forming the source electrode 140 and the metal oxide pattern 150 on the insulating substrate layer 170; FIG. 13 shows the formation of the gate insulation on the source electrode 140 and the metal oxide pattern 150 according to the third embodiment of the invention. A schematic structural diagram of layer 130; FIG. 14 is a schematic structural diagram of forming gate electrode 120 on gate insulating layer 130 according to Embodiment 3 of the present invention.

This embodiment provides another method for manufacturing the array substrate 100, which is used to manufacture the array substrate 100 with the top gate structure described in Embodiment 1.

As shown in Figure 10, for an array substrate 100 with a top gate structure, the manufacturing method of the array substrate 100 includes the following steps:

S1b. Form the insulating substrate layer 170 on the substrate 110.

As shown in FIG. 11 , an insulating substrate layer 170 is first deposited on the substrate 110 , and the insulating substrate layer 170 can cover the entire substrate 110 . Wherein, depositing the insulating substrate layer 170 includes sequentially depositing the first insulating substrate layer 171 and the second insulating substrate layer 172 on the substrate 110 .

S2b. Form the source electrode 140 and the metal oxide pattern 150 on the insulating substrate layer 170; wherein the metal oxide pattern 150 includes a first part 151 located in the middle area and a second part 152 located on both sides of the first part 151. The source electrode 140 There is an overlapping portion with the second portion 152 close to the source electrode 140, and the second portion 152 far away from the source electrode 140 serves as the pixel electrode 152a.

As shown in FIG. 12 , after the insulating substrate layer 170 is deposited on the substrate 110 , the source electrode 140 and the metal oxide pattern 150 are formed on the insulating substrate layer 170 .

In a possible implementation, a source metal layer can be deposited on the insulating substrate layer 170 first, and then a photolithography process is performed on the source metal layer to form the patterned source electrode 140; and then a metal layer is deposited on the insulating substrate layer 170. The metal oxide layer covers the source electrode 140, and a photolithography process is performed on the metal oxide layer to form a metal oxide pattern 150. Among them, the metal oxide pattern 150 includes a first part 151 and a second part 152 located on both sides of the first part 151. The second part 152 close to the source electrode 140 covers the source electrode 140, and the second part 152 far away from the source electrode 140 serves as a Pixel electrode 152a.

In another possible implementation, a metal oxide layer can be deposited on the insulating substrate layer 170 first, and then a photolithography process is performed on the metal oxide layer to form the metal oxide pattern 150; and then the source is deposited on the insulating substrate layer 170. The source metal layer covers the metal oxide pattern 150, and then a photolithography process is performed on the source metal layer to form a patterned source 140. In this way, the source electrode 140 covers the second portion 152 of the metal oxide pattern adjacent thereto.

S3b. Semiconducting the first portion 151 of the metal oxide pattern 150 to form an active layer 151a.

As shown in FIG. 12 , after the metal oxide pattern 150 is formed, the first part 151 of the metal oxide pattern 150 is irradiated with ultraviolet light or plasma implanted to semiconductorize the first part 151 to form an active layer 151 a.

S4b. Form a gate insulating layer 130 on the insulating substrate layer 170, and the gate insulating layer 130 covers the source electrode 140 and the metal oxide pattern 150.

As shown in FIG. 13, after the source electrode 140 and the metal oxide pattern 150 are formed, and the first part 151 of the metal oxide pattern 150 forms the active layer 151a, the gate insulating layer 130 is deposited on the insulating substrate layer 170 to insulate the gate. Layer 130 covers source 140 and metal oxide pattern 150 . Wherein, depositing the gate insulating layer 130 includes sequentially depositing the second gate insulating layer 132 and the first gate insulating layer 131 on the insulating substrate layer 170 .

S5b. Form the gate electrode 120 on the gate insulating layer 130.

As shown in FIG. 14 , after the gate insulating layer 130 is formed, a gate metal layer is deposited on the gate insulating layer 130 , and then the gate metal layer is formed into a patterned gate electrode 120 through a photolithography process.

Embodiment 4

FIG. 15 is a flow chart for forming the source electrode 140 and the metal oxide pattern 150 according to the fourth embodiment of the present invention; FIG. 16 is another method for forming the source electrode 140 and the metal oxide pattern 150 according to the fourth embodiment of the present invention. flow chart.

As shown in FIGS. 15 and 16 , regardless of whether the array substrate 100 has a bottom gate structure or a top gate structure, the drain electrode 180 may be provided in the array substrate 100 , or the drain electrode 180 may not be provided in the array substrate 100 . In this embodiment, the process of forming the source electrode 140 and the metal oxide pattern 150 for two array substrates 100 with and without the drain electrode 180 is described.

As shown in Figure 15, for the array substrate 100 without the drain electrode 180, in one possible implementation, forming the source electrode 140 and the metal oxide pattern 150 may specifically include the following steps:

S10a. Deposit a source metal layer on the gate insulating layer 130 (insulating substrate layer 170).

S20a. Perform a photolithography process on the source metal layer to form the source electrode 140.

S30a. Deposit a metal oxide layer on the gate insulating layer 130 (insulating substrate layer 170), and the metal oxide layer covers the source electrode 140.

S40a. Perform a photolithography process on the metal oxide layer to form a metal oxide pattern 150.

The formed metal oxide pattern 150 includes a first part 151 and a second part 152. The second part 152 is located on both sides of the first part 151. The second part 152 close to the source electrode 140 covers part of the source electrode 140 and is far away from the source electrode. The second portion 152 of 140 may serve as the pixel electrode 152a.

As shown in Figure 16, for the array substrate 100 provided with the drain electrode 180, in a possible implementation, forming the source electrode 140 and the metal oxide pattern 150 may specifically include the following steps:

S10b. Deposit the source and drain 180 metal layers on the gate insulating layer 130 (insulating substrate layer 170).

S20b. Perform a photolithography process on the metal layer of the source and drain electrodes 180 to form the source electrode 140 and the drain electrode 180; wherein there is a gap between the source electrode 140 and the drain electrode 180.

S30b. Deposit a metal oxide layer on the gate insulating layer 130 (insulating substrate layer 170), and the metal oxide covers the source electrode 140 and the drain electrode 180.

S40b. Perform a photolithography process on the metal oxide layer to form a metal oxide pattern 150.

The formed metal oxide pattern 150 includes a first part 151 and a second part 152. The second part 152 is located on both sides of the first part 151. The second part 152 close to the source electrode 140 covers part of the source electrode 140 and is far away from the source electrode. The second part 152 of 140 includes a first section 1521 and a second section 1522. The first section 1521 is connected to the first section 151 and is located in the interval between the source electrode 140 and the drain electrode 180. The second section 1522 is connected to the first section 1521. There is a gap therebetween, the second section 1522 is located on the other side of the drain electrode 180 , and part of the second section 1522 covers the drain electrode 180 .

Embodiment 5

This embodiment provides a display panel, which includes a color filter substrate, a liquid crystal layer, and the array substrate 100 described in Embodiment 1. Among them, the array substrate 100 and the color filter substrate are arranged oppositely, and the liquid crystal layer is sandwiched between the array substrate 100 and the color filter substrate. By applying an electric field between the array substrate 100 and the color filter substrate, the voltage in the electric field can control the arrangement of liquid crystal molecules in the liquid crystal layer, thereby achieving the purpose of light shielding and light transmission, so that the display panel displays images.

The structure, function and working principle of the array substrate 100 are introduced in detail in Embodiment 1 and will not be described again here.

Another aspect of this embodiment also provides a display device, which includes the above-mentioned display panel. For example, in this embodiment, the display device may be an LCD TV, a notebook computer, a tablet computer, electronic paper, etc.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention. scope.

Claims (9)

1. An array substrate is characterized by comprising a substrate and a thin film transistor arranged on the substrate, wherein the thin film transistor comprises a grid electrode, a grid insulating layer, a source electrode and a metal oxide pattern, the source electrode and the metal oxide pattern are arranged on the same layer, a part which is overlapped with each other is arranged between the metal oxide pattern and the source electrode, and the grid insulating layer is arranged between the grid electrode and the source electrode in the stacking direction of the array substrate; the metal oxide pattern comprises a first part and second parts, wherein the first part is located in the middle area and opposite to the grid electrode, the second parts are located on two sides of the first part, the first part is semiconducting to form an active layer, a part which is overlapped with each other is arranged between the source electrode and the second parts which are close to the source electrode, the source electrode and the active layer are separated through the second parts which are close to the source electrode, the second parts which are far from the source electrode are used as pixel electrodes, and the first parts are in direct contact with the second parts located on two sides of the first parts.

2. The array substrate of claim 1, wherein the gate electrode is disposed on the substrate, the gate insulating layer covers the substrate and the gate electrode, and the source electrode and the metal oxide pattern are disposed on the gate insulating layer.

3. The array substrate of claim 2, further comprising a passivation layer disposed on the gate insulating layer, the passivation layer covering the source electrode and the metal oxide pattern; the passivation layer comprises a first passivation layer and a second passivation layer which are sequentially laminated on the gate insulating layer, wherein the first passivation layer is a silicon oxide layer, and the second passivation layer is a silicon nitride layer.

4. The array substrate according to claim 1, wherein the source electrode and the metal oxide pattern are disposed on the substrate, the gate insulating layer covers the substrate and the source electrode and the metal oxide pattern, and the gate electrode is disposed on the gate insulating layer.

5. The array substrate of claim 4, further comprising an insulating substrate layer disposed between the substrate and the gate insulating layer, the source electrode and the metal oxide pattern being disposed on the insulating substrate layer; the insulating substrate layer comprises a first insulating substrate layer and a second insulating substrate layer which are sequentially laminated on the substrate, wherein the first insulating substrate layer is a silicon nitride layer, and the second insulating substrate layer is a silicon oxide layer.

6. The manufacturing method of the array substrate is characterized by comprising the following steps of:

forming a gate electrode on a substrate;

forming a gate insulating layer on a substrate, the gate insulating layer covering the gate electrode;

forming a source electrode and a metal oxide pattern on the gate insulating layer; wherein the metal oxide pattern includes a first portion located in a middle region and second portions located at both sides of the first portion, the source electrode and the second portion adjacent to the source electrode having a portion overlapping each other therebetween so as to space the source electrode from the first portion by the second portion adjacent to the source electrode, the second portion remote from the source electrode serving as a pixel electrode; wherein the first portion is in direct contact with second portions located on both sides of the first portion;

semiconducting the first portion of the metal oxide pattern to form an active layer;

and forming a passivation layer on the gate insulating layer, wherein the passivation layer covers the source electrode and the metal oxide pattern.

7. The manufacturing method of the array substrate is characterized by comprising the following steps of:

forming an insulating substrate layer on a substrate;

forming a source electrode and a metal oxide pattern on the insulating substrate layer; wherein the metal oxide pattern includes a first portion located in a middle region and second portions located at both sides of the first portion, the source electrode and the second portion adjacent to the source electrode having a portion overlapping each other therebetween so as to space the source electrode from the first portion by the second portion adjacent to the source electrode, the second portion remote from the source electrode serving as a pixel electrode; wherein the first portion is in direct contact with second portions located on both sides of the first portion;

Semiconducting the first portion of the metal oxide pattern to form an active layer;

forming a gate insulating layer on the insulating substrate layer, the gate insulating layer covering the source electrode and the metal oxide pattern;

and forming a gate electrode on the gate insulating layer.

8. The method for manufacturing an array substrate according to claim 6 or 7, wherein the forming source electrode and metal oxide patterns specifically includes:

depositing a source metal layer on the gate insulating layer or the insulating substrate layer;

performing a photoetching process on the source electrode metal layer to form a source electrode;

depositing a metal oxide layer on the gate insulating layer or the insulating substrate layer, the metal oxide layer covering the source electrode;

performing a photoetching process on the metal oxide layer to form a metal oxide pattern; the metal oxide pattern comprises a first part positioned in the middle area and a second part positioned at two sides of the first part, and a part which is overlapped with each other is arranged between the source electrode and the second part which is close to the source electrode.

9. A display panel comprising the array substrate of any one of claims 1-5.