CN111569963B - Horizontal nano-channel array, micro-nano fluidic chip and manufacturing method thereof - Google Patents
Horizontal nano-channel array, micro-nano fluidic chip and manufacturing method thereof Download PDFInfo
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- 239000002090 nanochannel Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000002070 nanowire Substances 0.000 claims abstract description 30
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 64
- 238000005530 etching Methods 0.000 claims description 42
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 6
- 238000009623 Bosch process Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000000609 electron-beam lithography Methods 0.000 claims description 4
- 239000011241 protective layer Substances 0.000 claims description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 4
- 238000003491 array Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 14
- 239000012530 fluid Substances 0.000 description 6
- 238000010923 batch production Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000001712 DNA sequencing Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000002331 protein detection Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000237509 Patinopecten sp. Species 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000020637 scallop Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- 238000003860 storage Methods 0.000 description 1
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- B01L3/00—Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
- B01L3/50—Containers for the purpose of retaining a material to be analysed, e.g. test tubes
- B01L3/502—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
- B01L3/5027—Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
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- B82Y40/00—Manufacture or treatment of nanostructures
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- B01L2200/10—Integrating sample preparation and analysis in single entity, e.g. lab-on-a-chip concept
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B01—PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
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- B01L2300/0861—Configuration of multiple channels and/or chambers in a single devices
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Abstract
一种水平纳米通道阵列、微纳流控芯片及其制作方法，所述制作方法包括如下步骤：步骤1：在衬底上形成图形化的掩膜层；步骤2：以图形化的掩膜层为掩膜，对衬底进行刻蚀形成若干个扇贝状柱；步骤3：利用自限制氧化，在扇贝状柱上形成水平纳米线阵列；步骤4：对衬底的被刻蚀区域进行填充；步骤5：采用湿法腐蚀释放水平纳米线阵列，形成水平纳米通道阵列。本发明提出了一种工艺简单，与集成电路工艺相兼容且适宜批量生产的硅基水平纳米通道阵列制作方法。
A horizontal nanochannel array, a micro-nanofluidic chip and a manufacturing method thereof, the manufacturing method comprises the following steps: step 1: forming a patterned mask layer on a substrate; step 2: using the patterned mask layer As a mask, the substrate is etched to form several scallop-shaped columns; step 3: using self-limited oxidation to form a horizontal nanowire array on the scallop-shaped columns; step 4: filling the etched area of the substrate; Step 5: using wet etching to release the horizontal nanowire array to form a horizontal nanochannel array. The present invention provides a silicon-based horizontal nano-channel array fabrication method which is simple in process, compatible with integrated circuit process and suitable for mass production.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a horizontal nanochannel array, a micro-nanofluidic chip and a manufacturing method thereof.
Background
The Micro-nano fluidic chip integrates some functional components on a chip with the size of a coin to form a Micro-nano channel network for controlling fluid to penetrate through the whole system, so that partial functions of a conventional chemical or biological laboratory are realized. When the size of the flow channel features integrated on the micro-nano fluidic chip is reduced to the micro-scale or even nano-scale, the fluid passing through the flow channel can generate fluid features different from the macro-scale under the combined influence of van der waals force, electrostatic force, capillary force and the like. The characteristics have important influence on the application of the micro-nano fluidic chip in the aspects of fluid control, biosensing, protein detection, DNA sequencing and the like. Therefore, in order to explore the special properties of the fluid in the micro-nano fluidic system, a suitable micro-nano fluidic system with specific nano channels needs to be established.
At present, the main structural forms of the micro-nano flow control chip based on the nano channel include a horizontal channel and a vertical channel, wherein the nano channel of the horizontal nano flow control chip is positioned in the horizontal direction and is connected with micro liquid storage tanks at two sides. The micro-nano flow control channel with the structure form still has certain problems in the process technology at present. For example, the manufacturing method for manufacturing the micro-nano flow channel chip with the horizontal structure is complex, the process is incompatible with the integrated circuit process, the electron beam lithography technology has low lithography efficiency, and batch production cannot be realized.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a horizontal nanochannel array, a micro-nanofluidic chip and a manufacturing method thereof, so as to at least partially solve at least one of the above-mentioned technical problems.
In order to achieve the purpose, the scheme of the invention is as follows:
as an aspect of the present invention, there is provided a method for fabricating a horizontal nanochannel array, comprising the steps of:
step 1: forming a patterned mask layer on a substrate;
step 2: etching the substrate by taking the patterned mask layer as a mask to form a plurality of scallop-shaped columns;
and step 3: forming a horizontal nanowire array on the scallop-shaped column by self-limiting oxidation;
and 4, step 4: filling the etched area of the substrate;
and 5: and releasing the horizontal nano-wire array by adopting wet etching to form a horizontal nano-channel array.
As another aspect of the present invention, there is also provided a horizontal nanochannel array produced by the method for producing a horizontal nanochannel array as described above.
As a further aspect of the present invention, there is also provided a micro-nanofluidic chip comprising the horizontal nanochannel array as described above.
Based on the technical scheme, compared with the prior art, the invention has at least one or one part of the following beneficial effects:
the method adopts a conventional silicon-based material as a substrate, scalloped columns are formed by etching, a horizontal nano-wire array is formed by self-limiting oxidation, and a horizontal nano-channel array is formed by wet corrosion release; in summary, the invention provides a method for manufacturing a silicon-based horizontal nano-channel array, which has simple process, is compatible with integrated circuit process and is suitable for batch production;
(1) the invention adopts a cycle etching method of anisotropic etching-oxidation-isotropic etching or Bosch process to form one or more scallop columns, and then controls the minimum size and precision by a self-limiting oxidation mode to form a horizontal nanowire array without completely depending on the photoetching technology;
(2) the patterned mask layer can be formed by adopting film growth and electron beam patterning or by adopting a side wall transfer mode, and the side wall transfer mode is favorable for realizing the small-size patterned mask layer;
(3) the invention adopts the double-layer structure of the silicon oxide layer and the silicon nitride layer as the mask, which is beneficial to ensuring the circular shape of the etched and self-limited oxidized nanowire.
Drawings
FIG. 1 is a schematic flow chart illustrating the fabrication of horizontal nanochannel arrays according to examples 1-3 of the present invention;
FIG. 2 is a schematic view of a horizontal nanochannel array of example 1 of the present invention;
fig. 3 is a schematic process diagram of the patterned mask layer formed in step 1 in embodiment 1 of the present invention;
fig. 4 is a schematic process diagram of the patterned mask layer formed in step 1 in embodiment 3 of the present invention;
FIG. 5 is a schematic view of a scallop-shaped column formed in step 2 in example 1 of the present invention;
FIG. 6 is a top view of a real object of a scallop-shaped column of example 1 of the invention;
FIG. 7 is a side view of a real object of a scallop-shaped column of example 1 of the invention;
FIG. 8 is a schematic view of an array of horizontal nanowires formed in step 3 of example 1;
FIG. 9 is a schematic side view of an array of self-limiting oxidized horizontal nanowires of example 1 of the invention;
FIG. 10 is a schematic representation of a filled sample formed in step 4 of example 1 of the present invention.
In the above figures, the reference numerals have the following meanings:
1. a substrate; 2. a patterned mask layer; 21. a silicon oxide layer; 22. a silicon nitride layer; 23. a silicon layer; 3. a scallop-shaped column; 31. a vertical portion; 32. an inner concave portion; 4. a horizontal nanowire array; 5. a horizontal nanochannel array.
Detailed Description
The invention provides a silicon-based nano-channel technology which is simple in process, compatible with an integrated circuit process and suitable for batch production. The invention adopts a conventional silicon substrate, manufactures silicon nanowires through film growth and common photoetching (or electron beams) and special etching technology, and then releases the silicon nanowires to form one or more horizontal nano-channel arrays.
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
Example 1
In a first exemplary embodiment of the present invention, a method for fabricating a horizontal nanochannel array is provided, as shown in fig. 1, comprising the steps of:
step 1: forming a patterned mask layer 2 on a substrate 1;
step 2: etching the substrate 1 by taking the patterned mask layer 2 as a mask to form a plurality of scallop-shaped columns 3;
and step 3: forming a horizontal nanowire array 4 on the scallop-shaped column 3 by self-limiting oxidation;
and 4, step 4: filling the etched area of the substrate 1;
and 5: and (3) releasing the horizontal nano-wire array 4 by adopting wet etching to form a horizontal nano-channel array 5.
In the embodiment of the present invention, as shown in fig. 3, step 1 specifically includes the following sub-steps:
substep 111: forming a mask layer on a substrate 1;
more specifically, the mask layer includes a silicon oxide layer 21 and a silicon nitride layer 22 from bottom to top, the silicon oxide layer 21 may be grown by a chemical vapor deposition method or a thermal oxidation method, and the silicon nitride layer 22 may be grown by a chemical vapor deposition method.
Substep 112: forming a pattern on the mask layer by adopting electron beam lithography;
in other embodiments of the present invention, the mask layer is not limited thereto, and the mask layer may be the silicon nitride layer 22 alone, but when only the silicon nitride layer 22 is used as the mask, the first nanowire after self-limiting oxidation is triangular, and when the mask layer with a double-layer structure is used as the mask, the nanowire is more favorable to form a circular shape.
In the embodiment of the invention, in the step 2, the specific steps of etching the substrate 1 to form the plurality of scalloped pillars 3 are to repeatedly and alternately perform anisotropic etching, oxidation and isotropic etching on the substrate 1 to form the plurality of scalloped pillars 3 as shown in fig. 5;
in the embodiment of the invention, the single-period anisotropic etching, oxidation and isotropic etching specifically comprises the following sub-steps:
substep 211: removing an oxide layer on the surface of the substrate 1;
substep 212: forming a vertical portion 31 on the substrate 1 by anisotropic etching;
substep 213: oxidizing the surface of the vertical portion 31 to form a protective layer;
substep 214: removing the protective layer on the surface of the substrate 1;
substep 215: forming an inner concave portion 32 on the substrate 1 by isotropic etching;
substep 216: oxidizing the surface of the inner recess 32;
the anisotropic etching specifically comprises the following steps: the upper radio frequency power is 500W-5000W, and the lower radio frequency power is 10W-200W; etching by adopting fluorine-based gas; the etching time is 1-100 s;
more specifically, the fluorine-based gas may be CF4、CHF3Or SF6Preferably SF6A gas;
the isotropic etching specifically comprises the following steps: only starting an upper radio frequency source, wherein the upper radio frequency power is 500-5000W; etching by adopting fluorine-based gas; the etching time is 1 s-100 s; fluorine radicalThe gas may be CF4、CHF3Or SF6Preferably SF6A gas;
wherein, the oxidation is specifically as follows: only starting an upper radio frequency source, wherein the upper radio frequency power is 500-5000W; by the use of O2Oxidizing by using fluorine-based gas; the oxidation time is 1 s-100 s; the fluorine-based gas may be CF4、CHF3Or SF6Preferably SF6A gas.
In an embodiment of the present invention, the anisotropic etching-oxidation-isotropic etching process is performed cyclically, the number of cycles being related to the number of nanowires formed. In example 1 of the present invention, the number of cycles of anisotropic etch-oxidation-isotropic etch is three.
In the embodiment of the present invention, as shown in fig. 6 and 7, the scallop-shaped pillar shape and the size rule obtained by the method for manufacturing the horizontal nano-channel array of the present invention are controllable.
In the embodiment of the present invention, as shown in fig. 8, in step 3, the self-limiting oxidation means that the oxidation stops automatically when the oxidation is completed to a certain degree, so as to form the nanowire structure wrapped by the oxide layer.
Wherein, the self-limiting oxidation adopts high-temperature furnace tube oxidation or rapid thermal annealing oxidation;
wherein the self-limiting oxidation temperature is 800-1100 ℃, and the time is 10 min-5 h.
Wherein the cross-sectional shape of the single horizontal nanowire is circular or elliptical.
In the embodiment of the present invention, as shown in fig. 9, the nanowire array obtained by the method for manufacturing a horizontal nanochannel array of the present invention has controllable nanowire morphology and size rules.
In the embodiment of the invention, in step 4, the etched area of the substrate 1 is filled by adopting a chemical vapor deposition method, and then the surface is mechanically flattened;
the fill dielectric comprises silicon oxide or silicon nitride, preferably silicon oxide.
In an embodiment of the invention, the silicon oxide is filled, and the substrate 1 is filled with HARP (high Aspect Ratio Process)The grooves have good HARP filling capacity, and mainly use large flow of tetraethyl orthosilicate (TEOS) and O3Carrying out thermochemical reaction to form; chemical mechanical planarization is then used to the surface of the mask layer, resulting in the filled sample shown in fig. 10.
In the embodiment of the invention, in step 5, the horizontal nanowire array 4 is released by wet etching to form the horizontal nanochannel array 5 as shown in fig. 2;
in the step 5, the etching solution adopted by the wet etching comprises tetramethyl ammonium hydroxide or potassium hydroxide; the material of the substrate 1 includes monocrystalline silicon, silicon carbide, silicon germanium or glass silicon.
Thus, a method for fabricating a horizontal nanochannel array according to the first exemplary embodiment of the present invention has been described.
Example 2
In a second exemplary embodiment of the present invention, a method for fabricating a horizontal nanochannel array is provided, wherein this embodiment differs from embodiment 1 in that: in the step 2, the substrate 1 is etched to form a plurality of scalloped columns 3, and the substrate 1 is etched to form a plurality of scalloped columns 3 by adopting a bosch process;
wherein the Boshi process specifically adopts C4F8And SF6The gas repeatedly and alternately deposits and etches the substrate 1 to form a plurality of scallop-shaped columns 3;
wherein the number of etching cycles is the same as the number of nanowires in the horizontal nanowire array 4.
Thus, a method for fabricating a horizontal nanochannel array according to a second exemplary embodiment of the present invention is described.
Example 3
In a third exemplary embodiment of the present invention, a method for fabricating a horizontal nanochannel array is provided, wherein this embodiment differs from embodiment 1 in that: as shown in fig. 4, step 1 includes the following sub-steps:
substep 121: forming a silicon oxide layer 21 and a silicon layer 23 in this order on the substrate 1;
substep 122: performing anisotropic etching on the silicon layer 23 to form a silicon step;
substep 123: forming a silicon nitride layer 22 on the silicon oxide layer 21 having the silicon step;
substep 124: forming a silicon nitride side wall by adopting self-aligned etching;
substep 125: removing the silicon steps and the exposed silicon oxide layer 21 in sequence by adopting wet etching to form a patterned mask layer 2;
wherein, the silicon layer 23 is a polysilicon layer or an amorphous silicon layer;
in the embodiment of the invention, the silicon step is in a smooth and steep shape by anisotropic etching, and then the silicon nitride layer 22 is deposited, and the thickness of the silicon nitride layer 22 determines the size of the subsequent scallop-shaped column 3. The mask layer is manufactured in a side wall transfer mode, so that the horizontal nanowire array can be made denser under the condition of not depending on photoetching.
More specifically, the structure of the patterned mask layer 2 includes a plurality of arrayed cuboids, and the width of a single cuboid is 10nm to 500 nm.
Thus, a method for fabricating a horizontal nanochannel array according to a third exemplary embodiment of the present invention is described.
Example 4
In a fourth exemplary embodiment of the present invention, as shown in fig. 2, there is provided a horizontal nanochannel array fabricated by the method of fabricating a horizontal nanochannel array as described above.
In an embodiment of the present invention, the structure of the horizontal nanochannel array of the present invention is specifically that its channels extend in the horizontal direction, its cross-section is circular or elliptical, and a plurality of horizontal nanochannels are arrayed in the vertical direction to form one group, and include 1 group or more groups in the horizontal direction, which can be adjusted according to the actual situation.
To this end, a horizontal nanochannel array according to a fourth exemplary embodiment of the present invention has been described.
Example 5
In a fifth exemplary embodiment of the invention, a micro nanofluidic chip is provided, comprising a horizontal nanochannel array 5 as described above. More specifically, the micro-nanofluidic chip with the horizontal nanochannel array 5 can be applied to aspects of fluid manipulation, biosensing, protein detection, DNA sequencing and the like, and in addition, the horizontal nanochannel array 5 can also be applied to a cell screener.
So far, the introduction of the micro-nanofluidic chip according to the fifth exemplary embodiment of the present invention is completed.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
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