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CN111564457A - Array substrate and preparation method thereof, and display panel - Google Patents

Array substrate and preparation method thereof, and display panel Download PDF

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Publication number
CN111564457A
CN111564457A CN202010470538.4A CN202010470538A CN111564457A CN 111564457 A CN111564457 A CN 111564457A CN 202010470538 A CN202010470538 A CN 202010470538A CN 111564457 A CN111564457 A CN 111564457A
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layer
hole
conductive layer
via hole
metal wire
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CN111564457B (en
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付恒野
蔡惠洁
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441Interconnections, e.g. scanning lines
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412Digitisers structurally integrated in a display
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Position Input By Displaying (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention relates to an array substrate, a preparation method thereof and a display panel. And transmitting a signal of a part of the first conductive layer opposite to the metal wire layer to another part of the first conductive layer opposite to the side wall of the through hole by using the second conductive layer. When the first conducting layer generates cracks at the included angle between the surface of the metal wire layer and the side wall of the through hole, signals of the metal wire layer can still be transmitted through the first conducting layer, the increase of lap joint impedance is avoided, and the abnormal touch phenomenon is avoided.

Description

一种阵列基板及其制备方法、显示面板Array substrate and preparation method thereof, and display panel

技术领域technical field

本发明涉及显示技术领域,具体涉及一种阵列基板及其制备方法、显示面板。The present invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel.

背景技术Background technique

显示装置可以把计算机的数据变换成各种文字、数字、符号或直观的图像显示出来,并且可以利用键盘等输入工具把命令或数据输入计算机,借助系统的硬件和软件随时增添、删改、变换显示内容。显示装置根据所用之显示器件分为等离子、液晶、发光二极管和阴极射线管等类型。The display device can convert the data of the computer into various characters, numbers, symbols or intuitive images for display, and can use input tools such as keyboards to input commands or data into the computer, and add, delete, and change the display at any time with the help of the hardware and software of the system. content. Display devices are classified into plasma, liquid crystal, light emitting diode, and cathode ray tube types according to the display device used.

TFT(Thin Film Transistor)是薄膜晶体管的缩写。TFT式显示屏是各类笔记本电脑和台式机上的主流显示设备,该类显示屏上的每个液晶像素点都是由集成在像素点后面的薄膜晶体管来驱动,因此TFT式显示屏也是一类有源矩阵液晶显示设备。TFT式显示屏是最好的LCD彩色显示器之一,TFT式显示器具有高响应度、高亮度、高对比度等优点,其显示效果接近CRT式显示器。TFT (Thin Film Transistor) is an abbreviation for Thin Film Transistor. TFT display is the mainstream display device on various laptops and desktops. Each liquid crystal pixel on this type of display is driven by a thin film transistor integrated behind the pixel, so TFT display is also a type of display. Active matrix liquid crystal display device. The TFT-type display is one of the best LCD color displays. The TFT-type display has the advantages of high responsivity, high brightness, and high contrast, and its display effect is close to that of the CRT-type display.

高分辨率产品的TFT基板在IC附近的拉线区(fanout)走线密集,其中包含实现TP触控的信号线。为了将金属线层的信号通过第一导电层传递至公共电极处,我们需要在平坦层上设置通孔。The TFT substrate of high-resolution products is densely traced in the fanout area near the IC, including signal lines for TP touch control. In order to transmit the signal of the metal line layer to the common electrode through the first conductive layer, we need to set a through hole on the flat layer.

如图1所示,在常规的通孔7设计中,第一导电层4通过通孔7搭接到金属线层2上,由于第一导电层4的材质采用ITO,且ITO为硬质膜,金属线层2表面与通孔7侧壁的夹角近似为直角,第一导电层4容易在该夹角处产生裂缝9,进而使搭接阻抗增大,导致金属线层2的信号无法通过第一导电层4传递至公共电极处,进而产生触控异常现象。现有技术中的第一导电层4在金属线层2表面与通孔侧壁的夹角处产生裂缝9的现象难以检测,甚至于到整机状态下才会被发现,损失重大。因此需要寻求一种新型的阵列基板以解决上述问题。As shown in FIG. 1, in the conventional design of the through hole 7, the first conductive layer 4 is lapped onto the metal wire layer 2 through the through hole 7. Since the material of the first conductive layer 4 is ITO, and ITO is a hard film , the angle between the surface of the metal wire layer 2 and the side wall of the through hole 7 is approximately a right angle, and the first conductive layer 4 is prone to cracks 9 at this angle, thereby increasing the lap resistance, resulting in the signal of the metal wire layer 2 cannot be It is transmitted to the common electrode through the first conductive layer 4 , thereby causing abnormal touch phenomenon. In the prior art, it is difficult to detect cracks 9 in the first conductive layer 4 at the included angle between the surface of the metal wire layer 2 and the sidewall of the through hole, and it is not even discovered until the whole machine is in the state, and the loss is heavy. Therefore, it is necessary to seek a new type of array substrate to solve the above problems.

发明内容SUMMARY OF THE INVENTION

本发明的目的是提供一种阵列基板及其制备方法、显示面板,其能够解决现有的阵列基板中存在的第一导电层容易在金属线层表面与通孔侧壁的夹角处产生裂缝,进而使搭接阻抗增大,导致金属线层的信号无法通过第一导电层传递至公共电极处,进而产生触控异常现象等问题。The purpose of the present invention is to provide an array substrate, a preparation method thereof, and a display panel, which can solve the problem that the first conductive layer existing in the existing array substrate is prone to cracks at the angle between the surface of the metal wire layer and the sidewall of the through hole. , thereby increasing the lap resistance, so that the signal of the metal wire layer cannot be transmitted to the common electrode through the first conductive layer, thereby causing problems such as abnormal touch.

为了解决上述问题,本发明提供了一种阵列基板,其包括:基底;金属线层,设置于所述基底上;平坦层,设置于所述金属线层及所述基底上;通孔,贯穿所述平坦层,且与所述金属线层相对设置;第一导电层,设置于所述平坦层上,且延伸至所述通孔内,贴附至所述通孔的侧壁,且连接至所述金属线层上;钝化层,设置于所述第一导电层上,且延伸至所述通孔内;过孔,贯穿所述钝化层,且与所述通孔的侧壁和/或所述金属线层相对设置;以及第二导电层,设置于所述过孔内,连接至所述第一导电层中与所述金属线层相对的一部分,且连接至所述第一导电层中与所述通孔的侧壁相对的另一部分。In order to solve the above problems, the present invention provides an array substrate, which includes: a base; a metal wire layer, disposed on the base; a flat layer, disposed on the metal wire layer and the base; The flat layer is arranged opposite to the metal wire layer; the first conductive layer is arranged on the flat layer, extends into the through hole, is attached to the sidewall of the through hole, and is connected to the metal wire layer; a passivation layer, disposed on the first conductive layer, and extending into the through hole; a via hole, penetrating the passivation layer, and connected to the sidewall of the through hole and/or the metal wire layers are oppositely arranged; and a second conductive layer is arranged in the via hole, connected to a part of the first conductive layer opposite to the metal wire layer, and connected to the first conductive layer Another part of a conductive layer opposite to the sidewall of the through hole.

进一步的,其中所述过孔的数量为两个以上;一个过孔与所述金属线层相对设置;另一个过孔与所述通孔的侧壁相对设置。Further, the number of the via holes is more than two; one via hole is arranged opposite to the metal line layer; the other via hole is arranged opposite to the side wall of the through hole.

进一步的,其中所述第二导电层穿过一个过孔连接至所述第一导电层,且穿过另一个过孔连接至所述第一导电层。Further, the second conductive layer is connected to the first conductive layer through one via hole, and is connected to the first conductive layer through another via hole.

进一步的,其中所述过孔与所述通孔的侧壁及所述金属线层相对设置。Further, the via hole is disposed opposite to the sidewall of the through hole and the metal line layer.

进一步的,其中所述第二导电层设置于所述过孔内,贴附至所述第一导电层,从所述过孔一侧的孔壁延伸至另一侧的孔壁。Further, the second conductive layer is disposed in the via hole, attached to the first conductive layer, and extends from the hole wall on one side of the via hole to the hole wall on the other side.

为了解决上述问题,本发明还提供了一种阵列基板的制备方法,其包括以下步骤:提供一基底;在所述基底上制备金属线层;在所述金属线层及所述基底上制备平坦层;贯穿所述平坦层形成通孔,且所述通孔与所述金属线层相对设置;在所述平坦层上制备第一导电层,且所述第一导电层延伸至所述通孔内,贴附至所述通孔的侧壁,且连接至所述金属线层上;在所述第一导电层上制备钝化层,且所述第一导电层延伸至所述通孔内;贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置;以及在所述过孔内制备第二导电层,所述第二导电层连接至所述第一导电层中与所述金属线层相对的一部分,且连接至所述第一导电层中与所述通孔的侧壁相对的另一部分。In order to solve the above problems, the present invention also provides a method for preparing an array substrate, which includes the following steps: providing a substrate; preparing a metal wire layer on the substrate; preparing a flat layer on the metal wire layer and the substrate A through hole is formed through the flat layer, and the through hole is arranged opposite to the metal line layer; a first conductive layer is prepared on the flat layer, and the first conductive layer extends to the through hole inside, attached to the sidewall of the through hole, and connected to the metal wire layer; a passivation layer is prepared on the first conductive layer, and the first conductive layer extends into the through hole forming a via hole through the passivation layer, and the via hole is disposed opposite to the sidewall of the via hole and/or the metal wire layer; and preparing a second conductive layer in the via hole, the The second conductive layer is connected to a portion of the first conductive layer opposite to the metal wire layer, and is connected to another portion of the first conductive layer opposite to the sidewall of the through hole.

进一步的,在贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置的步骤中包括:贯穿所述钝化层形成两个以上过孔;一个过孔与所述金属线层相对设置;另一个过孔与所述通孔的侧壁相对设置。Further, in the step of forming a via hole through the passivation layer, and the via hole is disposed opposite to the sidewall of the through hole and/or the metal wire layer, the step includes: forming two holes through the passivation layer. There are more than one via hole; one via hole is arranged opposite to the metal line layer; the other via hole is arranged opposite to the side wall of the through hole.

进一步的,在贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置的步骤中,所述过孔与所述通孔的侧壁及所述金属线层相对设置。Further, in the step of forming a via hole through the passivation layer, and the via hole and the sidewall of the via hole and/or the metal wire layer are disposed opposite to each other, the via hole and the through hole are The sidewalls and the metal wire layer are arranged opposite to each other.

进一步的,其中所述通孔及过孔均通过蚀刻方式形成。Further, the through holes and the via holes are formed by etching.

为了解决上述问题,本发明还提供了一种显示面板,包括本发明所涉及的阵列基板。In order to solve the above problems, the present invention also provides a display panel including the array substrate involved in the present invention.

本发明的优点是:本发明涉及一种阵列基板及其制备方法、显示面板,阵列基板中的第二导电层连接至所述第一导电层中与所述金属线层相对的一部分,且连接至所述第一导电层中与所述通孔的侧壁相对的另一部分。利用第二导电层将第一导电层中与所述金属线层相对的一部分的信号传递至所述第一导电层中与所述通孔的侧壁相对的另一部分上。当第一导电层在金属线层表面与通孔侧壁的夹角处产生裂缝时,金属线层的信号仍然能通过第一导电层进行传递,避免增大搭接阻抗,避免产生触控异常现象。The advantages of the present invention are as follows: the present invention relates to an array substrate, a preparation method thereof, and a display panel, wherein the second conductive layer in the array substrate is connected to a portion of the first conductive layer opposite to the metal wire layer, and is connected to to another portion of the first conductive layer opposite to the sidewall of the through hole. Using the second conductive layer, the signal of a part of the first conductive layer opposite to the metal line layer is transmitted to another part of the first conductive layer opposite to the sidewall of the through hole. When a crack occurs in the first conductive layer at the angle between the surface of the metal wire layer and the sidewall of the through hole, the signal of the metal wire layer can still be transmitted through the first conductive layer, so as to avoid increasing the lap resistance and avoid abnormal touch control. Phenomenon.

附图说明Description of drawings

为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

图1为现有技术的阵列基板结构示意图。FIG. 1 is a schematic structural diagram of an array substrate in the prior art.

图2为实施例1的阵列基板的结构示意图。FIG. 2 is a schematic structural diagram of the array substrate of Example 1. FIG.

图3为实施例1的阵列基板中的通孔示意图。FIG. 3 is a schematic diagram of through holes in the array substrate of Example 1. FIG.

图4为实施例1的阵列基板中的过孔的结构示意图。FIG. 4 is a schematic structural diagram of a via hole in the array substrate of Embodiment 1. FIG.

图5为实施例1的阵列基板的制备步骤图。FIG. 5 is a diagram showing the preparation steps of the array substrate of Example 1. FIG.

图6为实施例2的阵列基板的结构示意图。FIG. 6 is a schematic structural diagram of the array substrate of Example 2. FIG.

图7为实施例2的阵列基板中的过孔的结构示意图。FIG. 7 is a schematic structural diagram of a via hole in the array substrate of Embodiment 2. FIG.

图8为实施例2的阵列基板的制备步骤图。FIG. 8 is a diagram showing the preparation steps of the array substrate of Example 2. FIG.

图中部件标识如下:The parts in the figure are marked as follows:

100、阵列基板100. Array substrate

1、基底 2、金属线层1. Substrate 2. Metal Wire Layer

3、平坦层 4、第一导电层3. Flat layer 4. The first conductive layer

5、钝化层 6、第二导电层5. Passivation layer 6. Second conductive layer

7、通孔 8、过孔7. Through hole 8. Via hole

9、裂缝9. Cracks

81、第一过孔 82、第二过孔81. The first via 82. The second via

83、第三过孔83. The third via

具体实施方式Detailed ways

以下结合说明书附图详细说明本发明的优选实施例,以向本领域中的技术人员完整介绍本发明的技术内容,以举例证明本发明可以实施,使得本发明公开的技术内容更加清楚,使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现,本发明的保护范围并非仅限于文中提到的实施例,下文实施例的说明并非用来限制本发明的范围。The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, so as to fully introduce the technical content of the present invention to those skilled in the art, to exemplify the implementation of the present invention, to make the technical content disclosed in the present invention clearer, and to make the present invention clearer. Those skilled in the art will more readily understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, the protection scope of the present invention is not limited to the embodiments mentioned herein, and the description of the following embodiments is not intended to limit the scope of the present invention.

本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是附图中的方向,本文所使用的方向用语是用来解释和说明本发明,而不是用来限定本发明的保护范围。The directional terms mentioned in the present invention, such as "up", "down", "front", "rear", "left", "right", "inside", "outside", "side", etc., are only attached The directions in the drawings and the directional terms used herein are used to explain and describe the present invention, rather than to limit the protection scope of the present invention.

在附图中,结构相同的部件以相同数字标号表示,各处结构或功能相似的组件以相似数字标号表示。此外,为了便于理解和描述,附图所示的每一组件的尺寸和厚度是任意示出的,本发明并没有限定每个组件的尺寸和厚度。In the drawings, structurally identical components are denoted by the same numerals, and structurally or functionally similar components are denoted by like numerals throughout. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

当某些组件,被描述为“在”另一组件“上”时,所述组件可以直接置于所述另一组件上;也可以存在一中间组件,所述组件置于所述中间组件上,且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时,二者可以理解为直接“安装”或“连接”,或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。When certain components are described as being "on" another component, the component can be directly on the other component; an intervening component may also be present and the component is placed on the intervening component , and the intermediate component is placed on another component. When one component is described as being "mounted to" or "connected to" another component, both can be understood as being "mounted" or "connected" directly, or one component being "mounted to" or "connected to" through an intervening component another component.

实施例1Example 1

本实施例提供了一种显示面板,包括阵列基板100。This embodiment provides a display panel including an array substrate 100 .

如图2所示,阵列基板100包括:基底1、金属线层2、平坦层3、第一导电层4、钝化层5以及第二导电层6。As shown in FIG. 2 , the array substrate 100 includes: a substrate 1 , a metal wire layer 2 , a planarization layer 3 , a first conductive layer 4 , a passivation layer 5 and a second conductive layer 6 .

其中所述基底1中包括基板,所述基板可以采用柔性基板,具有阻隔水氧作用,基板可具有较好的抗冲击能力,可以有效保护阵列基板100。基板的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。The base 1 includes a substrate, and the substrate can be a flexible substrate, which has the function of blocking water and oxygen, and the substrate can have good impact resistance, which can effectively protect the array substrate 100 . The material of the substrate includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.

如图2所示,金属线层2设置于所述基底1上;所述金属线层2的材质为金属,如铜Cu或钼Mo。As shown in FIG. 2 , the metal wire layer 2 is disposed on the substrate 1 ; the material of the metal wire layer 2 is metal, such as copper Cu or molybdenum Mo.

如图2所示,平坦层3设置于所述金属线层2及所述基底1上。所述平坦层3可以为其上的第一导电层4的制备提供一平整的表面。As shown in FIG. 2 , the flat layer 3 is disposed on the metal wire layer 2 and the substrate 1 . The flat layer 3 can provide a flat surface for the preparation of the first conductive layer 4 thereon.

如图2、图3所示,平坦层3中设有通孔7,所述通孔7贯穿所述平坦层3,且与所述金属线层2相对设置。所述通孔7主要是用于第一导电层4与金属走线层2的连接,实现金属走线层2内的信号传递至第一导电层4的效果。As shown in FIGS. 2 and 3 , the flat layer 3 is provided with a through hole 7 , and the through hole 7 penetrates through the flat layer 3 and is disposed opposite to the metal wire layer 2 . The through holes 7 are mainly used for the connection between the first conductive layer 4 and the metal wiring layer 2 , so as to realize the effect of transmitting the signal in the metal wiring layer 2 to the first conductive layer 4 .

如图2所示,第一导电层4设置于所述平坦层3上,且延伸至所述通孔7内,贴附至所述通孔7的侧壁,且连接至所述金属线层2上。由此第一导电层4与金属线层2形成接触,实现金属走线层2内的信号传递至第一导电层4的效果。由于ITO(氧化铟锡)具有很好的导电性和透明性,可以切断对人体有害的电子辐射、紫外线及远红外线,因此,本实施例中,第一导电层4的材质优选ITO。As shown in FIG. 2 , the first conductive layer 4 is disposed on the flat layer 3 , extends into the through hole 7 , is attached to the sidewall of the through hole 7 , and is connected to the metal wire layer 2 on. In this way, the first conductive layer 4 is in contact with the metal wire layer 2 , so as to achieve the effect of transmitting the signal in the metal wire layer 2 to the first conductive layer 4 . Since ITO (indium tin oxide) has good conductivity and transparency, it can cut off electron radiation, ultraviolet rays and far infrared rays that are harmful to the human body. Therefore, in this embodiment, the material of the first conductive layer 4 is preferably ITO.

如图2所示,钝化层5设置于所述第一导电层4上,且延伸至所述通孔7内。As shown in FIG. 2 , the passivation layer 5 is disposed on the first conductive layer 4 and extends into the through hole 7 .

如图2、图4所示,钝化层5中设有过孔8,所述过孔8贯穿所述钝化层5,且与所述通孔7的侧壁和/或所述金属线层2相对设置。As shown in FIG. 2 and FIG. 4 , the passivation layer 5 is provided with a via hole 8 , the via hole 8 penetrates the passivation layer 5 and is connected with the sidewall of the via hole 7 and/or the metal wire Layer 2 is set relatively.

如图2、图4所示,本实施例中,所述过孔8包括两个以上的数量。本实施例中的过孔8包括第一过孔81、第二过孔82和第三过孔83。第一过孔81与所述金属线层2相对设置;第二过孔82与所述通孔7的一侧侧壁相对设置;第三过孔83与所述通孔7的另一侧侧壁相对设置。通过在钝化层5上形成过孔8,便于第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。As shown in FIG. 2 and FIG. 4 , in this embodiment, the number of the via holes 8 includes more than two. The via hole 8 in this embodiment includes a first via hole 81 , a second via hole 82 and a third via hole 83 . The first via hole 81 is arranged opposite to the metal wire layer 2 ; the second via hole 82 is arranged opposite to one side wall of the through hole 7 ; the third via hole 83 is arranged opposite to the other side side of the through hole 7 The walls are arranged opposite. By forming the via hole 8 on the passivation layer 5, it is convenient for the second conductive layer 6 to transmit the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 and the The other part of the side wall of the through hole 7 is opposite.

如图2所示,第二导电层6设置于所述过孔8内,连接至所述第一导电层4中与所述金属线层2相对的一部分,且连接至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。As shown in FIG. 2 , the second conductive layer 6 is disposed in the via hole 8 , is connected to a portion of the first conductive layer 4 opposite to the metal wire layer 2 , and is connected to the first conductive layer 4 and the other part opposite to the side wall of the through hole 7 .

如图2所示,本实施例中,所述第二导电层6穿过第一过孔81连接至所述第一导电层4,且穿过第二过孔82连接至所述第一导电层4,以及穿过第三过孔83连接至所述第一导电层4。由于ITO(氧化铟锡)具有很好的导电性和透明性,可以切断对人体有害的电子辐射、紫外线及远红外线,因此,本实施例中,第二导电层6的材质优选ITO。As shown in FIG. 2 , in this embodiment, the second conductive layer 6 is connected to the first conductive layer 4 through a first via hole 81 , and is connected to the first conductive layer through a second via hole 82 layer 4 , and is connected to the first conductive layer 4 through the third via hole 83 . Since ITO (indium tin oxide) has good conductivity and transparency, it can cut off electron radiation, ultraviolet rays and far infrared rays that are harmful to the human body. Therefore, in this embodiment, the material of the second conductive layer 6 is preferably ITO.

由此,所述第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。当第一导电层4在金属线层2表面与通孔7侧壁的夹角处产生裂缝时,金属线层2的信号仍然能通过第一导电层4进行传递,避免增大搭接阻抗,避免产生触控异常现象。Thus, the second conductive layer 6 transmits the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 opposite to the sidewall of the through hole 7 another part. When a crack occurs in the first conductive layer 4 at the angle between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4 to avoid increasing the lap impedance, Avoid abnormal touch.

如图5所示,本实施例还提供了本实施例所涉及的阵列基板100的制备方法,其包括以下步骤:S1,提供一基底1;S2,在所述基底1上制备金属线层2;S3,在所述金属线层2及所述基底1上制备平坦层3;S4,贯穿所述平坦层3形成通孔7,且所述通孔7与所述金属线层2相对设置;S5,在所述平坦层3上制备第一导电层4,且所述第一导电层4延伸至所述通孔7内,贴附至所述通孔7的侧壁,且连接至所述金属线层2上;S6,在所述第一导电层4上制备钝化层5,且所述第一导电层4延伸至所述通孔7内;S7,贯穿所述钝化层5形成两个以上过孔8;一个过孔8与所述金属线层2相对设置;另一个过孔8与所述通孔7的侧壁相对设置;以及S8,在所述过孔8内制备第二导电层6,所述第二导电层6连接至所述第一导电层4中与所述金属线层2相对的一部分,且连接至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。As shown in FIG. 5 , this embodiment also provides a method for preparing the array substrate 100 involved in this embodiment, which includes the following steps: S1 , providing a substrate 1 ; S2 , preparing a metal wire layer 2 on the substrate 1 . ; S3, preparing a flat layer 3 on the metal wire layer 2 and the substrate 1; S4, forming a through hole 7 through the flat layer 3, and the through hole 7 and the metal wire layer 2 are arranged opposite; S5, a first conductive layer 4 is prepared on the flat layer 3, and the first conductive layer 4 extends into the through hole 7, is attached to the sidewall of the through hole 7, and is connected to the through hole 7 On the metal wire layer 2; S6, prepare a passivation layer 5 on the first conductive layer 4, and the first conductive layer 4 extends into the through hole 7; S7, form through the passivation layer 5 Two or more via holes 8 ; one via hole 8 is arranged opposite to the metal wire layer 2 ; the other via hole 8 is arranged opposite to the side wall of the through hole 7 ; Two conductive layers 6, the second conductive layer 6 is connected to a part of the first conductive layer 4 opposite to the metal wire layer 2, and is connected to the through hole 7 in the first conductive layer 4 the opposite part of the side wall.

S8中所述第二导电层6穿过一个过孔8连接至所述第一导电层4,且穿过另一个过孔8连接至所述第一导电层4。In S8 , the second conductive layer 6 is connected to the first conductive layer 4 through one via hole 8 , and is connected to the first conductive layer 4 through another via hole 8 .

其中所述通孔7及过孔8均通过蚀刻方式形成。The through holes 7 and the via holes 8 are formed by etching.

通过上述方法制备形成的阵列基板100中的第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。当第一导电层4在金属线层2表面与通孔7侧壁的夹角处产生裂缝时,金属线层2的信号仍然能通过第一导电层4进行传递,避免增大搭接阻抗,避免产生触控异常现象。The second conductive layer 6 in the array substrate 100 prepared by the above method transmits the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 and the through hole 7 the other part of the side wall opposite. When a crack occurs in the first conductive layer 4 at the angle between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4 to avoid increasing the lap impedance, Avoid abnormal touch.

实施例2Example 2

本实施例提供了一种显示面板,包括阵列基板100。This embodiment provides a display panel including an array substrate 100 .

如图6所示,阵列基板100包括:基底1、金属线层2、平坦层3、第一导电层4、钝化层5以及第二导电层6。As shown in FIG. 6 , the array substrate 100 includes: a substrate 1 , a metal wire layer 2 , a planarization layer 3 , a first conductive layer 4 , a passivation layer 5 and a second conductive layer 6 .

其中所述基底1中包括基板,所述基板可以采用柔性基板,具有阻隔水氧作用,基板可具有较好的抗冲击能力,可以有效保护阵列基板100。基板的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。The base 1 includes a substrate, and the substrate can be a flexible substrate, which has the function of blocking water and oxygen, and the substrate can have good impact resistance, which can effectively protect the array substrate 100 . The material of the substrate includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.

如图6所示,金属线层2设置于所述基底1上;所述金属线层2的材质为金属,如铜Cu或钼Mo。As shown in FIG. 6 , the metal wire layer 2 is disposed on the substrate 1 ; the material of the metal wire layer 2 is metal, such as copper Cu or molybdenum Mo.

如图6所示,平坦层3设置于所述金属线层2及所述基底1上。所述平坦层3可以为其上的第一导电层4的制备提供一平整的表面。As shown in FIG. 6 , the flat layer 3 is disposed on the metal wire layer 2 and the substrate 1 . The flat layer 3 can provide a flat surface for the preparation of the first conductive layer 4 thereon.

如图6所示,平坦层3中设有通孔7,所述通孔7贯穿所述平坦层3,且与所述金属线层2相对设置。所述通孔7主要是用于第一导电层4与金属走线层2的连接,实现金属走线层2内的信号传递至第一导电层4的效果。As shown in FIG. 6 , a through hole 7 is provided in the flat layer 3 , and the through hole 7 penetrates through the flat layer 3 and is disposed opposite to the metal wire layer 2 . The through holes 7 are mainly used for the connection between the first conductive layer 4 and the metal wiring layer 2 , so as to realize the effect of transmitting the signal in the metal wiring layer 2 to the first conductive layer 4 .

如图6所示,第一导电层4设置于所述平坦层3上,且延伸至所述通孔7内,贴附至所述通孔7的侧壁,且连接至所述金属线层2上。由此第一导电层4与金属线层2形成接触,实现金属走线层2内的信号传递至第一导电层4的效果。由于ITO(氧化铟锡)具有很好的导电性和透明性,可以切断对人体有害的电子辐射、紫外线及远红外线,因此,本实施例中,第一导电层4的材质优选ITO。As shown in FIG. 6 , the first conductive layer 4 is disposed on the flat layer 3 , extends into the through hole 7 , is attached to the sidewall of the through hole 7 , and is connected to the metal wire layer 2 on. In this way, the first conductive layer 4 is in contact with the metal wire layer 2 , so as to achieve the effect of transmitting the signal in the metal wire layer 2 to the first conductive layer 4 . Since ITO (indium tin oxide) has good conductivity and transparency, it can cut off electron radiation, ultraviolet rays and far infrared rays that are harmful to the human body. Therefore, in this embodiment, the material of the first conductive layer 4 is preferably ITO.

如图6所示,钝化层5设置于所述第一导电层4上,且延伸至所述通孔7内。As shown in FIG. 6 , the passivation layer 5 is disposed on the first conductive layer 4 and extends into the through hole 7 .

如图6、图7所示,钝化层5中设有过孔8,所述过孔8贯穿所述钝化层5,且与所述通孔7的侧壁和/或所述金属线层2相对设置。As shown in FIG. 6 and FIG. 7 , the passivation layer 5 is provided with a via hole 8 , the via hole 8 penetrates the passivation layer 5 and is connected to the sidewall of the via hole 7 and/or the metal line Layer 2 is set relatively.

如图6、图7所示,本实施例中,所述过孔8的数量为一个。所述过孔8与所述通孔7的侧壁及所述金属线层2相对设置。通过在钝化层5上形成过孔8,便于第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。As shown in FIG. 6 and FIG. 7 , in this embodiment, the number of the via hole 8 is one. The via hole 8 is disposed opposite to the sidewall of the through hole 7 and the metal wire layer 2 . By forming the via hole 8 on the passivation layer 5, it is convenient for the second conductive layer 6 to transmit the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 and the The other part of the side wall of the through hole 7 is opposite.

如图6所示,第二导电层6设置于所述过孔8内,贴附至所述第一导电层4,从所述过孔8一侧的孔壁延伸至另一侧的孔壁。由于ITO(氧化铟锡)具有很好的导电性和透明性,可以切断对人体有害的电子辐射、紫外线及远红外线,因此,本实施例中,第二导电层6的材质优选ITO。As shown in FIG. 6 , the second conductive layer 6 is disposed in the via hole 8 , attached to the first conductive layer 4 , and extends from the hole wall on one side of the via hole 8 to the hole wall on the other side . Since ITO (indium tin oxide) has good conductivity and transparency, it can cut off electron radiation, ultraviolet rays and far infrared rays that are harmful to the human body. Therefore, in this embodiment, the material of the second conductive layer 6 is preferably ITO.

由此,所述第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。当第一导电层4在金属线层2表面与通孔7侧壁的夹角处产生裂缝时,金属线层2的信号仍然能通过第一导电层4进行传递,避免增大搭接阻抗,避免产生触控异常现象。Thus, the second conductive layer 6 transmits the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 opposite to the sidewall of the through hole 7 another part. When a crack occurs in the first conductive layer 4 at the angle between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4 to avoid increasing the lap impedance, Avoid abnormal touch.

如图8所示,本实施例还提供了本实施例所涉及的阵列基板100的制备方法,其包括以下步骤:S1,提供一基底1;S2,在所述基底1上制备金属线层2;S3,在所述金属线层2及所述基底1上制备平坦层3;S4,贯穿所述平坦层3形成通孔7,且所述通孔7与所述金属线层2相对设置;S5,在所述平坦层3上制备第一导电层4,且所述第一导电层4延伸至所述通孔7内,贴附至所述通孔7的侧壁,且连接至所述金属线层2上;S6,在所述第一导电层4上制备钝化层5,且所述第一导电层4延伸至所述通孔7内;S7,贯穿所述钝化层5形成一个过孔8,所述过孔8与所述金属线层2及所述通孔7的侧壁相对设置;以及S8,在所述过孔8内制备第二导电层6,所述第二导电层6连接至所述第一导电层4中与所述金属线层2相对的一部分,且连接至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。As shown in FIG. 8 , this embodiment also provides a method for preparing the array substrate 100 involved in this embodiment, which includes the following steps: S1 , providing a substrate 1 ; S2 , preparing a metal wire layer 2 on the substrate 1 ; S3, preparing a flat layer 3 on the metal wire layer 2 and the substrate 1; S4, forming a through hole 7 through the flat layer 3, and the through hole 7 and the metal wire layer 2 are arranged opposite; S5, a first conductive layer 4 is prepared on the flat layer 3, and the first conductive layer 4 extends into the through hole 7, is attached to the sidewall of the through hole 7, and is connected to the through hole 7 On the metal wire layer 2; S6, prepare a passivation layer 5 on the first conductive layer 4, and the first conductive layer 4 extends into the through hole 7; S7, form through the passivation layer 5 A via hole 8, the via hole 8 is disposed opposite to the metal wire layer 2 and the sidewall of the through hole 7; and S8, a second conductive layer 6 is prepared in the via hole 8, the second conductive layer 6 is formed in the via hole 8 The conductive layer 6 is connected to a portion of the first conductive layer 4 opposite to the metal wire layer 2 , and is connected to another portion of the first conductive layer 4 opposite to the sidewall of the through hole 7 .

S8中所述第二导电层6设置于所述过孔8内,贴附至所述第一导电层4,从所述过孔8一侧的孔壁延伸至另一侧的孔壁。In S8, the second conductive layer 6 is disposed in the via hole 8, attached to the first conductive layer 4, and extends from the hole wall on one side of the via hole 8 to the hole wall on the other side.

其中所述通孔7及过孔8均通过蚀刻方式形成。The through holes 7 and the via holes 8 are formed by etching.

通过上述方法制备形成的阵列基板100中的第二导电层6将第一导电层4中与所述金属线层2相对的一部分的信号传递至所述第一导电层4中与所述通孔7的侧壁相对的另一部分。当第一导电层4在金属线层2表面与通孔7侧壁的夹角处产生裂缝时,金属线层2的信号仍然能通过第一导电层4进行传递,避免增大搭接阻抗,避免产生触控异常现象。The second conductive layer 6 in the array substrate 100 prepared by the above method transmits the signal of a part of the first conductive layer 4 opposite to the metal wire layer 2 to the first conductive layer 4 and the through hole 7 the other part of the side wall opposite. When a crack occurs in the first conductive layer 4 at the angle between the surface of the metal wire layer 2 and the side wall of the through hole 7, the signal of the metal wire layer 2 can still be transmitted through the first conductive layer 4 to avoid increasing the lap impedance, Avoid abnormal touch.

以上对本申请所提供的阵列基板及其制备方法、显示面板进行了详细介绍,本文中应用了具体个例对本申请的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。The array substrate, its preparation method, and the display panel provided by the present application have been introduced in detail above. The principles and implementations of the present application are described with specific examples in this article. The descriptions of the above embodiments are only used to help understand the present application. Those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some of the technical features; and these modifications or replacements, and The essence of the corresponding technical solutions is not deviated from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1.一种阵列基板,其特征在于,包括:1. An array substrate, characterized in that, comprising: 基底;base; 金属线层,设置于所述基底上;a metal wire layer disposed on the substrate; 平坦层,设置于所述金属线层及所述基底上;a flat layer, disposed on the metal wire layer and the substrate; 通孔,贯穿所述平坦层,且与所述金属线层相对设置;a through hole, penetrating through the flat layer, and disposed opposite to the metal line layer; 第一导电层,设置于所述平坦层上,且延伸至所述通孔内,贴附至所述通孔的侧壁,且连接至所述金属线层上;a first conductive layer, disposed on the flat layer, extending into the through hole, attached to the sidewall of the through hole, and connected to the metal wire layer; 钝化层,设置于所述第一导电层上,且延伸至所述通孔内;a passivation layer, disposed on the first conductive layer and extending into the through hole; 过孔,贯穿所述钝化层,且与所述通孔的侧壁和/或所述金属线层相对设置;以及a via hole, penetrating the passivation layer, and disposed opposite to the sidewall of the via hole and/or the metal line layer; and 第二导电层,设置于所述过孔内,连接至所述第一导电层中与所述金属线层相对的一部分,且连接至所述第一导电层中与所述通孔的侧壁相对的另一部分。A second conductive layer, disposed in the via hole, connected to a portion of the first conductive layer opposite to the metal wire layer, and connected to the sidewall of the first conductive layer and the via hole the opposite part. 2.根据权利要求1所述的阵列基板,其特征在于,所述过孔的数量为两个以上;2. The array substrate according to claim 1, wherein the number of the via holes is two or more; 一个过孔与所述金属线层相对设置;a via hole is arranged opposite to the metal line layer; 另一个过孔与所述通孔的侧壁相对设置。Another via hole is disposed opposite to the side wall of the through hole. 3.根据权利要求2所述的阵列基板,其特征在于,所述第二导电层穿过一个过孔连接至所述第一导电层,且穿过另一个过孔连接至所述第一导电层。3 . The array substrate according to claim 2 , wherein the second conductive layer is connected to the first conductive layer through one via hole, and is connected to the first conductive layer through another via hole. 4 . Floor. 4.根据权利要求1所述的阵列基板,其特征在于,所述过孔与所述通孔的侧壁及所述金属线层相对设置。4 . The array substrate of claim 1 , wherein the via hole is disposed opposite to the sidewall of the through hole and the metal wire layer. 5 . 5.根据权利要求4所述的阵列基板,其特征在于,所述第二导电层设置于所述过孔内,贴附至所述第一导电层,从所述过孔一侧的孔壁延伸至另一侧的孔壁。5 . The array substrate according to claim 4 , wherein the second conductive layer is disposed in the via hole, and is attached to the first conductive layer, from a hole wall on one side of the via hole. 6 . extends to the hole wall on the other side. 6.一种阵列基板的制备方法,其特征在于,包括以下步骤:6. A method for preparing an array substrate, comprising the following steps: 提供一基底;provide a base; 在所述基底上制备金属线层;preparing a metal wire layer on the substrate; 在所述金属线层及所述基底上制备平坦层;preparing a planarization layer on the metal wire layer and the substrate; 贯穿所述平坦层形成通孔,且所述通孔与所述金属线层相对设置;A through hole is formed through the flat layer, and the through hole is disposed opposite to the metal line layer; 在所述平坦层上制备第一导电层,且所述第一导电层延伸至所述通孔内,贴附至所述通孔的侧壁,且连接至所述金属线层上;A first conductive layer is prepared on the flat layer, and the first conductive layer extends into the through hole, is attached to the sidewall of the through hole, and is connected to the metal wire layer; 在所述第一导电层上制备钝化层,且所述第一导电层延伸至所述通孔内;preparing a passivation layer on the first conductive layer, and the first conductive layer extends into the through hole; 贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置;以及forming a via hole through the passivation layer, and the via hole is disposed opposite to the sidewall of the via hole and/or the metal line layer; and 在所述过孔内制备第二导电层,所述第二导电层连接至所述第一导电层中与所述金属线层相对的一部分,且连接至所述第一导电层中与所述通孔的侧壁相对的另一部分。A second conductive layer is prepared in the via hole, the second conductive layer is connected to a portion of the first conductive layer opposite to the metal wire layer, and is connected to the first conductive layer and the Another part of the side wall of the through hole opposite. 7.根据权利要求6所述的阵列基板的制备方法,其特征在于,在贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置的步骤中包括:贯穿所述钝化层形成两个以上过孔;7 . The manufacturing method of an array substrate according to claim 6 , wherein a via hole is formed through the passivation layer, and the via hole is connected to the sidewall of the via hole and/or the metal wire. 8 . The step of arranging the layers oppositely includes: forming more than two via holes through the passivation layer; 一个过孔与所述金属线层相对设置;a via hole is arranged opposite to the metal line layer; 另一个过孔与所述通孔的侧壁相对设置。Another via hole is disposed opposite to the side wall of the through hole. 8.根据权利要求6所述的阵列基板的制备方法,其特征在于,在贯穿所述钝化层形成过孔,且所述过孔与所述通孔的侧壁和/或所述金属线层相对设置的步骤中,所述过孔与所述通孔的侧壁及所述金属线层相对设置。8 . The method for manufacturing an array substrate according to claim 6 , wherein a via hole is formed through the passivation layer, and the via hole is connected to the sidewall of the via hole and/or the metal wire. 9 . In the step of arranging the layers oppositely, the via hole is arranged opposite to the sidewall of the through hole and the metal wire layer. 9.根据权利要求6所述的阵列基板的制备方法,其特征在于,所述通孔及过孔均通过蚀刻方式形成。9 . The method for manufacturing an array substrate according to claim 6 , wherein the through holes and the via holes are formed by etching. 10 . 10.一种显示面板,包括权利要求1-5中任一项所述的阵列基板。10. A display panel comprising the array substrate of any one of claims 1-5.
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