CN111555901B - A chip configuration network system that flexibly supports mixed bus protocols - Google Patents

Abstract

The invention belongs to the technical field of chip configuration networks, and in particular relates to a chip configuration network system that flexibly supports mixed bus protocols, including a configuration network master-slave interface, a protocol parsing and address mapping module and a core interconnection network; at the configuration network master-slave interface The protocol analysis and address mapping modules are respectively added; the protocol analysis and address mapping modules are used to realize the conversion between the bus read-write request/read-write response address and the network ID, and the read-write request or read-write response of different bus protocols It is converted into the form of data packets according to a unified format and injected into the core interconnection network, or the data packets received from the core interconnection network are converted into corresponding bus signal timings according to different bus protocols. The invention can flexibly support network interconnection and protocol bridging of the same or different bus protocols, greatly reduce the design complexity and technical threshold of the chip configuration network, and has good scalability and reusability.

Description

A chip configuration network system that flexibly supports mixed bus protocols

technical field

The invention belongs to the technical field of chip configuration networks, in particular to a chip configuration network system that flexibly supports mixed bus protocols.

Background technique

The chip configuration network is mainly used to support the configuration and management of the relevant registers or RAM space inside the chip by each main configuration interface (such as I2C, JTAG, PCIE, etc.) in the chip, and provide a basic guarantee for the realization of chip functions and performance. With the continuous increase of the chip design scale, the design scale and design complexity of the internal configuration network of the chip also increase. On the one hand, the scale of master (Master) and slave (Slave) interfaces supported by the configuration network is getting larger and larger, and the number of master-slave interfaces for large-scale system-on-chip configuration networks has exceeded 100; on the other hand, in order to shorten the time to market, the chip A variety of commercial IPs (intellectual property cores) are usually integrated internally. These commercial IPs may be located in the chip at the master port (Master) position of the configuration network, and also at the slave port (Slave) position of the configuration network, or even both slave ports. The interface also has a primary interface connected to the configuration network. In addition, different commercial IPs may use different bus protocols (such as AXI, AHB, APB, etc.), so that there may be multiple bus configuration requirements of different protocol types inside the chip at the same time, which leads to a sharp increase in design complexity.

Take the configuration network design of an SRIO switch chip as an example, as shown in Figure 1. According to the overall design requirements, the scale of the master-slave interface of the internal configuration network of the SRIO switch chip reaches nearly 100, and at the same time there are many different bus protocols such as AXI bus, AHB bus, SRIO maintenance package (bus read and write request), and Localbus bus. type. In order to meet the configuration requirements of the chip, the traditional design idea is to integrate multiple bus interconnection matrices of corresponding protocols (for multi-master and multi-slave communication scenarios) and bridge modules of different protocols inside the chip to achieve the same Data forwarding between master and slave interfaces of bus protocol and protocol conversion between different bus protocols. As shown in Figure 1, AXI_Matrix is used to realize the communication between multiple AXI protocol master-slave interfaces, AHB_Matrix is used to realize the communication between multiple AHB protocol master-slave interfaces, and AXI_To_AHB_Bridge is used to realize the communication between AXI protocol and AHB protocol. Conversion, AHB_To_Localbus_Bridge is used to realize the conversion between AHB protocol and Localbus bus, SRIO MPM (Maintenance Processing Module) is used to realize the conversion between SRIO maintenance package configuration request and AXI bus protocol, etc. In view of the complexity and compatibility of bus protocol processing, the integration of a large number of bus interconnection Matrix and Bridge modules in the configuration network will bring great challenges to its design and verification.

Under the application communication requirements of numerous master-slave interfaces and mixed bus protocols, the design methods of bus interconnection Matrix and bus bridge widely used in existing configuration network design usually have the following shortcomings:

(1) The design is difficult and the technical threshold is high. The design of bus interconnection Matrix and bus bridge is usually for signal-level processing of read and write address signals, data signals, and read and write response signals. Designers are not only required to be familiar with the dependencies and processing flow between the signals of the bus protocol, but also to Mastering the design method of the corresponding protocol interconnection Matrix and the realization of the conversion between different bus protocols is difficult to design and has a high technical threshold.

(2) It is difficult to guarantee the compatibility and consistency of the conversion of different bus protocols. The design of bus interconnection Matrix and bus bridge needs to strictly follow the corresponding bus protocol, and the compatibility and consistency of different bus protocol conversions are difficult to guarantee. Improper design can easily cause network deadlock, and even affect the function and performance of the entire chip. .

(3) Poor scalability and reusability. Once the design of the bus interconnection Matrix and the bus bridge is determined, a small change in the network scale or the change in the bus interface protocol will introduce a large workload of design modification and verification, and it is difficult to flexibly expand to different communication scales and application communication scenarios. Scalability and reusability are poor.

SUMMARY OF THE INVENTION

In order to solve the problems existing in the prior art, the present invention provides a chip configuration network system that flexibly supports mixed bus protocols, which can flexibly support not only commonly used AMBA buses (such as AXI/AHB/APB, etc.), processor secondary The network interconnection and protocol bridging of various bus protocols such as bus (such as Localbus, etc.), SRIO maintenance package configuration bus, user-defined bus, etc., can also greatly reduce the design complexity and technical threshold of the chip configuration network, and have good performance. Scalability and reusability.

In order to solve the above-mentioned technical problems, the present invention adopts the following technical solutions:

A chip configuration network system that flexibly supports mixed bus protocols of the present invention includes: a configuration network master-slave interface, a protocol analysis and address mapping module and a core interconnection network; protocol analysis and address mapping are respectively added to the configuration network master-slave interface. module, the protocol analysis and address mapping module is connected with the core interconnection network; the protocol analysis and address mapping module is used to realize the conversion between the bus read-write request/read-write response address and the network ID, and the read-write of different bus protocols. Write requests or read and write responses are converted into data packets according to a unified format and injected into the core interconnection network, or the data packets received from the core interconnection network are converted into corresponding bus signal timings according to different bus protocols. It is protocol-independent during transmission in the core interconnection network.

Further, the protocol parsing and address mapping module includes a synchronization processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module and an output queue sub-module;

The synchronous processing submodule is used to complete the cross-clock domain processing of the signal between the bus clock and the network clock;

The protocol packet processing submodule is used to encapsulate the bus read-write request/read-write response into a data packet according to the bus protocol;

The address mapping submodule is used for the mapping between the bus read-write request/read-write response address and the network DEST_ID, and the DEST_ID is encapsulated in the data packet for routing in the core interconnection network;

The protocol unpacking processing submodule is used to receive the data packets transmitted in the network, and convert them into corresponding bus signal timings according to different bus protocols;

The input queue sub-module is used to receive the data packets transmitted by the network, generate corresponding back pressure signals and send them to the network, and upload the data packets to the protocol unpacking processor under the control of the bus read-write request/read-write response signal. The module performs subsequent unpacking processing;

The output queue sub-module is used to receive the data packets generated by the bus read-write request/read-write response through the protocol packet processing sub-module, generate a corresponding back pressure signal to the bus interface, and output the queue sub-module when the network is idle. Inject packets into the network.

Further, the read and write requests or read and write responses of different bus protocols have a unified data packet format in the network, and the data packet format is as follows:

Tail Body … Body Header

The data packet consists of three data structures: Header Flit, Body Flit and Tail Flit. The header Flit carries routing information and related bus control information, while the Body Flit and Tail Flit carry routing information and related bus control information. The tail flit carries the read and write data information and the data packet end indication, and the data width of the three flits matches the data bit width of the network interface.

Further, the format of the header microchip is as follows:

Tag Resp Data Des_ID Src_ID Wr_addr Pkt_type Pro_type Flit_type

The format of the body microchip or tail microchip is as follows:

Data Data Data Data Flit_type

Flit_type indicates the type of the microchip, Pro_type indicates the type of the protocol, Pkt_type indicates the type of the data packet, Wr_addr indicates the bus read and write address, Src_ID indicates the source ID address of the message, Des_ID indicates the destination ID address of the message, Data indicates the bus read and write address Data, Resp represents read and write response, and Tag represents other important control information that needs to be paid attention to in the bus protocol.

Further, the core interconnection network in the chip configuration network adopts the Crossbar Switch mode or the NOC-based on-chip interconnection mode. When the chip configuration network has fewer master and slave nodes, the Crossbar Switch structure is adopted. When the chip configuration network has many master and slave nodes, Adopt NOC based on-chip interconnect structure.

Compared with the existing bus interconnection Matrix and the bus Bridge design method, the present invention has the following advantages:

1. Reduce the complexity of configuration network design: The chip configuration network system that flexibly supports mixed bus protocols of the present invention solves the problem of the design complexity of the bus interconnection Matrix and the bus Bridge. It can flexibly support network interconnection between the same protocols and bridge processing between different protocols, and avoid various complex signal dependencies in network protocol processing. The compatibility and consistency of protocol processing can also be easily guaranteed.

2. Avoid the occurrence of network deadlock, livelock and starvation: Different bus protocols are transmitted in the network in a unified data packet format, and mature deadlock-free routing algorithms or fair-based arbitration strategies are used in the network. It can effectively avoid the occurrence of network deadlock, livelock and starvation.

3. Good reusability and scalability: By increasing the communication scale of the core interconnection network and the protocol applicability of the PRAM interface, it can be flexibly applied to communication scenarios of different network scales and different protocol types. In addition, the fully verified PRAM module can be directly used in different application scenarios and has good reusability.

Description of drawings

In order to illustrate the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are For some embodiments of the present invention, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

1 is a schematic diagram of a prior art SRIO switching chip configuration network structure;

2 is a schematic structural diagram of a chip configuration network system that flexibly supports a hybrid bus protocol according to an embodiment of the present invention;

3 is a schematic structural diagram of a protocol parsing and address mapping module according to an embodiment of the present invention;

4 is a flow chart of the protocol packet processing sub-module and the protocol unpacking processing sub-module according to the embodiment of the present invention, wherein (a) is the working flow chart of the protocol packet processing sub-module, and (b) is the protocol unpacking processing sub-module work flow chart;

FIG. 5 is a schematic diagram of the chip configuration network structure based on 2D-MESH NOC.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work are protected by the present invention. scope.

Example 1

Different from the traditional bus interconnection Matrix and bus bridge design methods, complex signal level processing is required for the read and write address signals, data signals and read and write response signals of different bus protocols at the network transmission level, as shown in Figure 2. , the chip configuration network system that flexibly supports mixed bus protocols provided by this embodiment includes a configuration network master-slave interface, a protocol analysis and address mapping module, and a core interconnection network; protocol analysis and address mapping are respectively added at the configuration network master-slave interface. Module (Protocol Resolution and Address Mapping, PRAM), the protocol resolution and address mapping module is connected to the core interconnection network; the protocol resolution and address mapping module is used to realize the bus read-write request/read-write response address and the network ID. Conversion, and converting read and write requests or read and write responses of different bus protocols into data packets in a unified format and inject them into the core interconnection network, or convert data packets received from the core interconnection network into Corresponding bus signal timing, the data packets are protocol-independent when they are transmitted in the network, and the functions of the core interconnection network are simplified from the bus signal-based protocol processing and forwarding process to the data packet-based forwarding processing process, avoiding network protocol processing. Various complex signal dependency guarantees and their processing procedures in the protocol improve the compatibility and consistency of protocol processing.

As shown in Figure 3, the protocol parsing and address mapping module includes a synchronization processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module and an output queue sub-module.

The synchronization processing sub-module is used to complete the cross-clock domain processing of the signal between the bus clock and the network clock.

The protocol packet processing sub-module is used to encapsulate the bus read/write request/read/write response into data packets according to the bus protocol. According to the bus timing of different bus protocols, obtain the bus protocol type, read and write request type, address, control, data and response information, and combine with the network DEST_ID output by the address mapping sub-module, the bus read request, write request, Different bus operations such as read response and write response are encapsulated into read request packets, write request packets, read response packets, and write response packets and injected into the network, as shown in Figure 4(a). The data packets of different bus protocols use a unified data packet format in the network to be compatible with the read and write requests/read and write responses of different bus protocols and the data bit width of the network interface.

The address mapping sub-module is used for mapping between the bus read/write request/read/write response address and the network DEST_ID, which corresponds to the address resolution module in the traditional bus interconnection Matrix module. When various data packets generated by the protocol packet processing sub-module for bus operations of different bus protocol types are transmitted in the network, routing pathfinding will be performed based on the DEST_ID.

The protocol unpacking processing sub-module is used to receive the data packets transmitted from the network and convert them into the bus signal timing of the corresponding interface. After the protocol unpacking processing sub-module receives the valid data packets transmitted from the network, it first parses the corresponding bus protocol type, read and write request type, address, control, data and response information according to the unified data packet format, and according to the current The bus protocol completes the generation of the corresponding bus signal timing, such as bus read request, bus write request, bus write response, bus read response, etc., and maintains the dependency relationship and handshake timing between each bus signal, as shown in Figure 4(b) .

The input queue sub-module is used to receive the data packets sent from the network, generate the corresponding back pressure signal and send it to the network, and upload the data packets to the protocol unpacking processing sub-module under the control of the bus read and write request/read and write response signals. Subsequent unpacking processing.

The output queue sub-module is used to receive the data packets generated by the bus read and write request/read and write response through the protocol packet processing sub-module, generate the corresponding back pressure signal to the bus interface, and send the data in the output queue sub-module when the network is idle. Packets are injected into the network.

The read and write requests or read and write responses of different bus protocols have a unified data packet format in the network, and the data packet format is as follows:

Tail Body … Body Header

In order to simplify the structural design of the core network and be compatible with read and write requests/read and write responses of different bus protocols, data packets consist of three data structures: Header Flit, Body Flit and Tail Flit. The head microchip carries routing information and related bus control information, the body microchip and the tail microchip carry read and write data information and data packet end indication, and the data widths of the three microchips match the data bit width of the network interface. .

The format and bit width of the header microchip are as follows:

Tag Resp Data Des_ID Src_ID Wr_addr Pkt_type Pro_type Flit_type 130-82bit 81-80bit 79-48bit 47-40bit 39-32bit 31-8bit 7-6bit 5-3bit 2-0bit

The format and bit width of the body microchip or tail microchip are as follows:

Data Data Data Data Flit_type 130-99bit 98-67bit 66-35bit 34-3bit 2-0bit

(1) Flit_type indicates the type of the flit, where 001 represents the head flit, 010 represents the body flit, 100 represents the tail flit, and 101 is the single flit message, which represents both the head flit and the tail flit.

(2) Pro_type indicates the type of the protocol, and the bit field width of 3 bits can support up to 8 bus protocols.

(3) Pkt_type indicates the type of the data packet. For the chip configuration network, there are generally four types of data packets, where 00 indicates a write request, 01 indicates a read request, 10 indicates a write response, and 11 indicates a read response.

(4) Wr_addr represents the bus read and write address.

(5) Src_ID indicates the source ID address of the packet. The configuration network will assign a network ID address to each bus interface. The data packet transmission in the network is mainly based on ID for routing and pathfinding.

(6) Des_ID represents the destination ID address of the message, which is converted from the read and write addresses of the bus through address mapping.

(7) Data represents bus read and write data, for write request packets, it means write data, for read response packets, it means read data, and for read request and write response packets, the bit field data is not concerned.

(8) Resp means read and write response. According to different bus protocols, the Resp signal has different meanings.

(9) Tag means to save other important control information that needs attention in the bus protocol. For example, for the AXI4 protocol, the corresponding control signals such as read and write Cache, Prot, Lock, Burst, and Burst Length can be stored in the Tag bit field.

Generally speaking, for different bus protocols, if there is no need to support Burst read and write operations, a single microchip message (Flit_type=101) can completely represent a read and write request or a read and write response. When complex Burst bus operations need to be supported, there may be a situation where one microchip cannot represent a complete read and write request. In this case, the bus read and write requests need to be packaged in the form of multi-chip data packets. For example, for an AXI4 bus write operation with a Burst Length of 15, since one write operation needs to continuously write 16 data to the corresponding continuous address space, in addition to the header microchip, the data packet also needs to be accompanied by 3 individual microchips and 1 tail flit message is used to transmit 16 beats of write data.

The design of the core interconnection network in the chip configuration network of the present invention can adopt the traditional Crossbar Switch mode, and can also support data communication between multiple master-slave bus interfaces based on the NOC on-chip interconnection mode. Generally speaking, when the chip is configured with fewer master-slave nodes in the network, the traditional Crossbar Switch structure can be used. NOC-based on-chip interconnect structures generally have better scalability and communication performance.

Figure 5 shows the chip configuration network structure based on 2D-MESH NOC. Each bus master-slave interface is connected to the on-chip router (Router, R) through a protocol resolution and address mapping interface (PRAM). Links are connected to each other. When the bus read/write request or read/write response completes the packet processing in the PRAM, the data packet will complete its routing process in the network according to the Dest_ID and go through each intermediate router in turn until it reaches the destination network node. After the data packet reaches the destination network node, the unpacking process will be completed in its corresponding PRAM module, and the data packet will be restored to the corresponding bus sequence according to the interface bus protocol. It is not difficult to see that according to different configuration network design requirements, by modifying the communication scale of the core network and the protocol applicability of the PRAM interface, it can be flexibly applied to network communication of different network scales and different protocol types, with good scalability and reusability. . The above takes the 2D-MESH NOC structure as an example to illustrate the packetization, depacketization and data packet transmission process of the bus protocol in the network. Other on-chip interconnection structures, such as Butterfly, Fat-Tree, etc., can also be used in practical applications.

In the present invention, corresponding protocol analysis and address mapping modules are respectively added at the master and slave interfaces of the configuration network, which are used to convert the read and write requests or read and write responses of the bus protocol into the form of data packets according to a certain format and inject them into the network, or from The data packets received by the network are converted into corresponding bus signal timings according to the corresponding bus interface protocol, thereby realizing protocol isolation, converting the configuration network from signal-level processing to data-packet-level processing, and simplifying the complexity of protocol processing in the network. The read and write requests or read and write responses of different bus protocols have a unified data packet format in the network, which can be converted into different bus signal timings after being unpacked by different PRAM modules. Flexible support for data interconnection between different protocols.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus.

Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by program instructions related to hardware, the aforementioned program can be stored in a computer-readable storage medium, and when the program is executed, execute It includes the steps of the above method embodiments; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other mediums that can store program codes.

Finally, it should be noted that the above descriptions are only preferred embodiments of the present invention, and are only used to illustrate the technical solutions of the present invention, but not to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (4)

1. a chip configuration network system that flexibly supports hybrid bus protocol, is characterized in that, comprises: configuration network master-slave interface, protocol analysis and address mapping module and core interconnection network; at configuration network master-slave interface, increase protocol analysis and The address mapping module, the protocol analysis and address mapping module is connected to the core interconnection network; the protocol analysis and address mapping module is used to realize the conversion between the bus read and write request/read and write response addresses and the network ID, and to convert different bus protocols The read and write requests or read and write responses are converted into data packets according to a unified format and injected into the core interconnection network, or the data packets received from the core interconnection network are converted into corresponding bus signal timings according to different bus protocols, data Packets are protocol-independent when transported in the core interconnection network; The protocol parsing and address mapping module includes a synchronization processing sub-module, a protocol packet processing sub-module, an address mapping sub-module, a protocol unpacking processing sub-module, an input queue sub-module and an output queue sub-module; The synchronous processing submodule is used to complete the cross-clock domain processing of the signal between the bus clock and the network clock; The protocol packet processing submodule is used to encapsulate the bus read-write request/read-write response into a data packet according to the bus protocol; The address mapping submodule is used for the mapping between the bus read-write request/read-write response address and the network DEST_ID, and the DEST_ID is encapsulated in the data packet for routing in the core interconnection network; The protocol unpacking processing submodule is used to receive the data packets transmitted in the network, and convert them into corresponding bus signal timings according to different bus protocols; The input queue sub-module is used to receive the data packets transmitted by the network, generate corresponding back pressure signals and send them to the network, and upload the data packets to the protocol unpacking processor under the control of the bus read-write request/read-write response signal. The module performs subsequent unpacking processing; The output queue sub-module is used to receive the data packets generated by the bus read-write request/read-write response through the protocol packet processing sub-module, generate a corresponding back pressure signal to the bus interface, and output the queue sub-module when the network is idle. Inject packets into the network. 2. the chip configuration network system that flexibly supports the hybrid bus protocol according to claim 1, is characterized in that, the read-write request of different bus protocols or the read-write response have a unified data packet format in the network, and its data packet format is as follows : Tail Body … Body Header The data packet consists of three data structures: Header Flit, Body Flit and Tail Flit. The header Flit carries routing information and related bus control information, while the Body Flit and Tail Flit carry routing information and related bus control information. The tail flit carries the read and write data information and the data packet end indication, and the data width of the three flits matches the data bit width of the network interface. 3. the chip configuration network system that flexibly supports the hybrid bus protocol according to claim 2, is characterized in that, the format of the head microchip is as follows: Tag Resp Data Des_ID Src_ID Wr_addr Pkt_type Pro_type Flit_type The format of the body microchip or tail microchip is as follows: Data Data Data Data Flit_type Flit_type indicates the type of the microchip, Pro_type indicates the type of the protocol, Pkt_type indicates the type of the data packet, Wr_addr indicates the bus read and write address, Src_ID indicates the source ID address of the message, Des_ID indicates the destination ID address of the message, Data indicates the bus read and write address Data, Resp represents read and write response, and Tag represents other important control information that needs to be paid attention to in the bus protocol. 4. the chip configuration network system flexibly supporting the hybrid bus protocol according to claim 1, is characterized in that, the core interconnection network in the chip configuration network adopts Crossbar Switch mode or is based on NOC on-chip interconnection mode, when the chip configuration network main When there are few slave nodes, the Crossbar Switch structure is used. When the chip is configured with many master and slave nodes, the on-chip interconnect structure based on NOC is used.

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