CN111554679B - SOI FinFET device and manufacturing method thereof - Google Patents

Abstract

The invention discloses an SOI FinFET device and a manufacturing method thereof, wherein the SOI FinFET device comprises: a substrate having source and drain regions doped to form a group thereon; any one of the first region, the second region, the third region and the fourth region is arranged above the space between each group of the source region and the drain region; a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer are sequentially arranged above the substrate of the first region; a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer are sequentially arranged above the substrate of the second region; a high-K dielectric layer, a second doping layer, a TiN layer and the filling layer are sequentially arranged above the substrate in the third area; and a high-K dielectric layer, a second doping layer and a filling layer are sequentially arranged above the substrate in the fourth region. The SOI FinFET device does not have a thick work function layer, and the problem of metal filling of the gate electrode of a P-type device is well solved.

Description

A kind of SOI FinFET device and manufacturing method thereof

technical field

The invention relates to the technical field of semiconductor devices, in particular to an SOI FinFET device and a manufacturing method thereof.

Background technique

Threshold voltage determines the operating current, switching speed, static power consumption and other performance of MOS (Metal-Oxide-Semiconductor, metal-oxide-semiconductor) devices. It is a key parameter of MOS devices. How to accurately control the threshold voltage of devices Key technologies for manufacturing.

The gate of the Fin FET (Fin Field-Effect Transistor, Fin Field Effect Transistor) device generally adopts a high-K (high-k, HK) metal gate process, and the effective work function of the gate determines the threshold voltage of the high-K metal device. The threshold voltage of high-K metal gate SOI (Silicon-On-Insulator, silicon-on-insulator) FinFET devices is adjusted mainly by controlling the thickness of the gate work function metal. Experiments have shown that within a certain thickness range, the overall effective work function of the gate changes with the thickness of the work function metal layer. Among them, the P-type work function metal TiN (titanium nitride) is more typical, and the thickness of TiN is basically the same as that of the gate. It is directly proportional to the overall work function of the gate, and the greater the thickness, the greater the effective work function of the gate. It can be considered that the change of the gate work function is entirely derived from the change of the thickness of TiN, so the method of changing the thickness of TiN can adjust the effective work function of the gate to achieve the purpose of controlling the threshold voltage. In addition to the thickness adjustment of the work function metal, the high-K metal gate device also uses ion implantation of impurities on the first metal gate above the high-K dielectric layer to adjust the threshold voltage. In PMOS (Positive channel-Metal-Oxide-Semiconductor, The first layer of metal gate implantation in the P-type metal oxide semiconductor) region can increase the dopant of the effective work function, and a layer of metal in the NMOS (Negative channel-Metal-Oxide-Semiconductor, N-type metal oxide semiconductor) region Gate implants can reduce the effective work function of dopants, thereby adjusting the threshold voltage.

In the above-mentioned existing solution, the threshold voltage is adjusted through the metal thickness of the work function, which has limitations on the modulation amplitude of the voltage. Data show that as the metal thickness of the work function increases, the rate of change of the effective work function of the gate gradually decreases until it does not change after a certain critical thickness. When making ultra-low threshold voltage devices, the threshold voltage may not meet the requirements. Secondly, the excessive thickness of the gate work function metal will affect the subsequent metal filling of the gate, as shown in Figure 1, the thicker the work function metal layer 102, the smaller the space left for the gate contact metal 101. When manufacturing PMOS, especially ultra low threshold voltage PMOS (ultra low Vt PMOS, ULVT PMOS), a very thick gate work function metal is required, which is likely to cause filling problems and affect gate resistivity. Therefore, the prior art has the following disadvantages: there are limitations in fabricating ultra-low threshold voltage devices, and thicker gate metals will cause filling problems and thus affect the resistivity of the gate.

Contents of the invention

In view of the above problems, the present invention proposes a SOI FinFET device and its fabrication method, wherein the gate structure of the device does not require a thick gate work function metal, and the gate resistivity is stable; the fabrication method can effectively avoid gate The filling problem of pole metal, and simultaneously manufacture P-type and N-type low-threshold voltage devices, and P-type and N-type standard threshold voltage devices on the same chip, which solves the limitation problem.

In the first aspect, the present application provides the following technical solutions through an embodiment of the present application:

An SOI FinFET device comprising:

a substrate having source and drain regions doped in sets thereon;

Above each group of the source region and the drain region is any region in the first region, the second region, the third region and the fourth region; wherein, the first region is used to form a P-type The gate of the low threshold voltage device, the second region is used to form the gate of the P-type standard threshold voltage device, the third region is used to form the gate of the N-type low threshold voltage device, and the fourth region is used Used to form the gate of an N-type standard threshold voltage device;

The first region is sequentially arranged as a high-K dielectric layer, a first doped layer, a second doped layer, a TiN layer, and a filling layer from bottom to top; wherein, the first doped layer contains A TiN layer of a dopant, the second doped layer is a TiN layer containing a dopant that reduces the effective work function;

The second region is sequentially arranged as the high-K dielectric layer, the first doped layer, the second doped layer, the TiN layer, and the filling layer from bottom to top;

The third region is sequentially arranged as the high-K dielectric layer, the second doped layer, the TiN layer, and the filling layer from bottom to top;

The fourth region is sequentially arranged as the high-K dielectric layer, the second doped layer and the filling layer from bottom to top.

Preferably, the adjacent layer above the second doped layer in any one or more of the first region, the second region, the third region and the fourth region is provided with engraved etch barrier.

Preferably, the thickness of the TiN layer in the first region is greater than the thickness of the TiN layer in the second region.

Preferably, the filling layer is TiAl layer, TiN layer and metal tungsten in order from bottom to top.

Preferably, the first doped layer is a TiN layer of BF ₂ ions, and the second doped layer is a TiN layer of P ions.

In the second aspect, based on the same inventive concept, the present application provides the following technical solutions through an embodiment of the present application:

A method for manufacturing an SOI FinFET device, comprising:

A first doped layer is deposited on the first region and the second region on the high-K dielectric layer on the substrate; wherein, the substrate has a source region and a drain region in groups, and the first region and the second region are The two regions are respectively located above the groups of the source region and the drain region, the first region is used to form the gate of the P-type low threshold voltage device, and the second region is used to form the P-type standard The gate of a threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;

Continue to deposit a second doped layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; wherein, the second region and the third region are respectively Located above the groups of the source region and the drain region, the third region is used to form the gate of an N-type low threshold voltage device, and the fourth region is used to form an N-type standard threshold voltage device The gate of the second doped layer is a TiN layer containing a dopant that reduces the effective work function;

continuing to deposit a TiN layer on the first region, the second region and the third region on the high-K dielectric layer;

Continue to deposit a filling layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer.

Preferably, depositing the first doped layer on the first region and the second region on the high-K dielectric layer on the substrate includes:

Depositing a first doped layer on the high-K dielectric layer on the substrate;

coating a BARC layer on the first doped layer, and stripping the BARC layer of the third region and the fourth region;

The first doped layer in the third region and the fourth region is removed by an etching method.

Preferably, after the second doped layer is deposited on the first region, the second region, the third region and the fourth region on the high-K dielectric layer, and the high-K dielectric layer Before depositing the TiN layer on the first region, the second region and the third region on the layer, it also includes:

An etch stop layer is deposited on the first region, the second region, the third region and the fourth region.

Preferably, depositing a TiN layer on the first region, the second region and the third region on the high-K dielectric layer includes:

depositing a first layer of said TiN layer over said etch stop layer;

etching the second region and the third region up to the etch stop layer;

continue to laminate a second layer of the TiN layer above the etch barrier layer;

The fourth region is etched to the etch barrier layer.

Preferably, depositing a filling layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer includes:

A TiAl layer, a TiN layer and metal tungsten are sequentially deposited on the first region, the second region, the third region and the fourth region on the high-K dielectric layer.

In the SOI FinFET device provided by the present invention, the threshold voltage of the gate is affected by the TiN layer and the first/second doped layer, so that the gate structure of the SOI FinFET device has a wider threshold voltage adjustment range, and further The ultra-low threshold voltage P-type device (ie, the first region and the second region) no longer needs a thick work function layer, and the problem of gate metal filling of the P-type device has been well improved.

In the method for manufacturing an SOI FinFET device provided by the present invention, when forming the first layer of the metal gate, first deposit TiN and dope the P-type device (that is, the first region and the second region) to increase the effective work function. dopant, and then etch away the TiN in the N-type region (i.e. the third region and the fourth region), then deposit TiN and dope the dopant that reduces the effective work function required by the N-type region, and the doping amount can be control, so that the threshold voltage can be controlled. Compared with the method of adjusting the threshold voltage by changing the thickness of the gate work function layer in the prior art, the adjustment range is larger, which solves the limitation problem; for ultra-low threshold voltage P-type FinFET devices, a thick work function is no longer required layer, the gate metal filling problem of P-type devices has been greatly improved. Further, in the embodiment of the present invention, for the different work function requirements of devices with various threshold voltage types, it is not necessary to measure impurities, but to meet them by subsequently depositing a work function metal layer TiN with a corresponding thickness in each region, and finally complete the gate Extremely metallic filling. For P-type low-threshold voltage devices, P-type standard threshold-voltage devices, N-type low-threshold voltage devices and N-type standard threshold-voltage devices, the thickness of the deposited work function metal layer decreases, thus eliminating the need for multiple depositions, doping, and etching steps, and P-type, N-type low threshold voltage devices, P-type, N-type standard threshold voltage devices can be manufactured on the same chip, so that the manufacturing process greatly reduces the manufacturing cost.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the specific embodiments of the present invention are enumerated below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Also throughout the drawings, the same reference numerals are used to designate the same components. In the attached picture:

FIG. 1 shows a schematic diagram of the thickness structure of the gate contact metal and the work function metal layer in the prior art provided in the present invention;

FIG. 2 shows a schematic structural diagram of a gate structure of an SOI FinFET device provided in the first embodiment of the present invention;

FIG. 3 shows a method flow chart of a method for manufacturing a gate structure of an SOI FinFET device according to a second embodiment of the present invention;

FIG. 4 shows a schematic diagram of the grid structure when depositing a TiN layer and doping BF2 ions in the second embodiment of the present invention;

5 shows a schematic diagram of the gate structure when etching the TiN layer doped with BF2 ions deposited in the third region and the fourth region in the second embodiment of the present invention;

6 shows a schematic diagram of the gate structure when depositing a TiN layer and doping P ions in the second embodiment of the present invention;

FIG. 7 shows a schematic diagram of a gate structure when depositing an etching stopper layer in the second embodiment of the present invention;

FIG. 8 shows a schematic diagram of the gate structure when depositing the first TiN layer above the etching barrier layer in the second embodiment of the present invention;

9 shows a schematic diagram of the gate structure when etching the first TiN layer above the etching barrier layer in the second region and the third region in the second embodiment of the present invention;

FIG. 10 shows a schematic diagram of the gate structure when depositing a second TiN layer above the etching barrier layer in the second embodiment of the present invention;

11 shows a schematic diagram of the gate structure when etching the first TiN layer and the second TiN layer above the etch barrier layer in the fourth region in the second embodiment of the present invention;

FIG. 12 shows a schematic diagram of the gate structure after the filling layer is deposited in the second embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

It should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner" and "outer" are based on the Orientation or positional relationship, or the orientation or positional relationship that the inventive product is usually placed in use, is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, so as to Specific orientation configurations and operations, therefore, are not to be construed as limitations on the invention. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions, and should not be construed as indicating or implying relative importance.

In the description of the present invention, it also needs to be explained that, unless otherwise clearly specified and limited, the terms "set", "connected" and "connected" should be interpreted in a broad sense, for example, they can be directly connected or can be connected through an intermediate An indirect connection through a medium may be an internal connection between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations.

first embodiment

Please refer to FIG. 2 , which shows a schematic structural diagram of a gate structure 10 of an SOI FinFET device according to the first embodiment of the present invention. The gate structure 10 of the SOI FinFET device includes: a substrate with doping on the substrate to form a group of source regions and drain regions; above each group of source regions and drain regions is a first region a , any one of the second region b, the third region c, and the fourth region d; the four regions correspond respectively as follows: the first region a is used to form a P type ultra low threshold voltage device (P type ultra low threshold voltage, PULVT), the second region b is used to form the gate of P type standard threshold voltage device (P type Standard threshold voltage, PSVT), and the third region c is used to form N type low threshold voltage device (N type ultra low threshold voltage, NULVT), the fourth region d is used to form the gate of N type standard threshold voltage device (N type Standard threshold voltage, NSVT). Above the substrate in the first region a, a high-K dielectric layer 12, a first doped layer 13, a second doped layer 14, a TiN (titanium nitride) layer 160, and a filling layer 18 are sequentially arranged from bottom to top; wherein, The first doped layer 13 is a TiN layer containing a dopant that increases the effective work function, and the second doped layer 14 is a TiN layer that contains a dopant that reduces the effective work function; above the substrate of the second region b The high-K dielectric layer 12, the first doped layer 13, the second doped layer 14, the TiN layer 17, and the filling layer 18 are arranged sequentially from bottom to top; Dielectric layer 12 , second doped layer 14 , TiN layer 17 and filling layer 18 ; high-K dielectric layer 12 , second doping layer 14 and filling layer 18 are sequentially arranged above the substrate of the fourth region d from bottom to top.

In this embodiment, the position structure of the source region and the drain region relative to the gate can refer to the relative position structure relationship in the existing FinFET device, and will not be repeated here.

In this embodiment, the thickness of the TiN layer 160 in the first region a is greater than the thickness of the TiN layer 17 in the second region b and the third region c; specifically, two layers of TiN layers can be deposited in the first region a , that is, TiN layer 16 and TiN layer 17, and a layer of TiN layer 17 is deposited in the second region b and the third region c. Through the adjustment of the TiN thickness 160 , the change of the work function can be correspondingly realized, so as to realize different threshold voltages.

Through the above-mentioned gate structure 10 of the SOI FinFET device, the deposited layer with increased effective work function can be obtained in the P-type device, and the deposited layer with reduced effective work function can be obtained in the N-type device, increasing the adjustment range of the voltage threshold ; Further, in the P-type device, the thicker the TiN, the lower the threshold voltage, and in the N-type device, the thinner the TiN, the lower the threshold voltage, and different thicknesses of TiN are deposited in different regions, so that the SOI FinFET in this embodiment The threshold voltage adjustment range of the gate structure 10 of the device is larger, and the preparation is more flexible, thereby avoiding the filling problem caused by thicker gate metal and avoiding affecting the resistivity of the gate.

Further, the adjacent layer above the second doped layer 14 in each of the first region a, the second region b, the third region c and the fourth region d is provided with an etching stopper layer 15 . The thickness of the deposited TiN can be more accurately controlled during the fabrication of the gate structure 10 by setting the etching barrier layer 15 . Specifically, the etch barrier layer 15 is located between the second doped layer 14 and the TiN layer 16 in the first region a. The etch stop layer 15 is located between the second doped layer 14 and the TiN layer 17 in the second region b. In the third region c, the etch stop layer 15 is located between the second doped layer 14 and the TiN layer 17 , and in the fourth region d, the etch stop layer 15 is located between the second doped layer 14 and the filling layer 18 .

The dopant for increasing the effective work function corresponding to the first doped layer 13 may be: BF ₂ (boron fluoride), Al (aluminum), B (boron), Mo (molybdenum), Pt (platinum), etc. ; The dopant that reduces the effective work function corresponding to the second doped layer 14 can be: La (lanthanum), As (arsenic), Sb (antimony) and the like.

The filling layer 18 includes a TiAl layer (TiAl-based alloy), a TiN layer and a metal W (tungsten) from bottom to top to form a complete gate structure 10 .

It should be noted that, in this embodiment, the substrate material is Si (silicon) material. For the high-K dielectric layer 12, the dielectric constant of Al ₂ O ₃ (aluminum oxide) is too low in this embodiment, and ZrO ₂ (zirconium dioxide) and TiO ₂ (titania) react easily with the Si substrate, La ₂ O ₃ (lanthanum oxide) is easy to absorb water; therefore, the preferred high-K dielectric layer 12 is the following materials: HfO ₂ (hafnium oxide), HfSiO ₄ (hafnium orthosilicate), HfON (hafnium oxynitride), HfAlO (hafnium Aluminum oxide), HfSiO (hafnium silicate), HfSiON (hafnium silicon oxynitride), etc. In addition, an IL layer (interfacial layer, interfacial layer) may be deposited between the substrate and the high-K dielectric layer 12 for improving the contact characteristics between the substrate and the high-K dielectric layer 12 , and the interfacial layer may be SiO2.

An SOI FinFET device in this embodiment can be fabricated on the same chip to form different device types such as P-type low threshold voltage region, P-type standard threshold voltage region, N-type low threshold voltage region, and N-type standard threshold voltage region. At the same time, the gate structure 10 of the SOI FinFET device in this embodiment does not need to be doped by ion implantation, which avoids damage to the metal film due to the high doping energy of the ion implantation. In the gate structure 10 in this embodiment, the gate threshold voltage is affected by the TiN layer and the first/second doped layer 14, so that the gate structure 10 of the SOI FinFET device has a wider threshold voltage adjustment range , and then the ultra-low threshold voltage P-type FinFET device no longer needs a thick work function layer, and the problem of gate metal filling of the P-type device has been well improved.

second embodiment

Referring to FIG. 3 , this embodiment also provides a method for fabricating an SOI FinFET device, and FIG. 2 shows a flow chart of the method.

Specifically, the manufacturing method of the SOI FinFET device includes:

Step S10: Depositing a first doped layer on the first region and the second region on the high-K dielectric layer on the substrate; wherein, the substrate has source regions and drain regions in groups, and the first region and The second regions are respectively located above the groups of the source regions and the drain regions, the first regions are used to form gates of P-type low threshold voltage devices, and the second regions are used to form The gate of a P-type standard threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;

Step S20: continue to deposit a second doped layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; wherein, the second region and the first The three regions are respectively located above the groups of the source region and the drain region, the third region is used to form the gate of the N-type low threshold voltage device, and the fourth region is used to form the N-type standard The gate of the threshold voltage device, the second doped layer is a TiN layer containing a dopant that reduces the effective work function;

Step S30: continue to deposit a TiN layer on the first region, the second region and the third region on the high-K dielectric layer;

Step S40: continue to deposit filling layers on the first region, the second region, the third region and the fourth region on the high-K dielectric layer.

In step S10, the specific implementation may be: doping the substrate to form source regions and drain regions existing in groups, and depositing a first doped layer. Specifically, PEALD (PlasmaEnhanced Atomic Layer Deposition, Plasma Enhanced Atomic Layer Deposition) is used to deposit the first layer of metal gate TiN, and in-situ doping is doped with a dopant that can increase the effective work function, such as BF ₂ , as shown in Fig. 4. Further, a BARC layer (Bottom Anti-Reflective Coatings, Bottom Anti-Reflective Coatings) is coated on the first doped layer, and the BARC layer in the third region and the fourth region is stripped off, as shown in FIG. 5 . Finally, the first doped layer in the third region and the fourth region is removed by etching, and the etching stops on the high-K dielectric layer, that is, only the first doped layer on the first region and the second region remains . After the etching is completed, the BARC layer on the first doped layer is stripped for subsequent deposition steps. PEALD is an improved technology of traditional ALD (atomic layer deposition, atomic layer deposition), which is formed by adding a plasma discharge device to the ALD equipment. It can achieve single atomic layer deposition. The process is the same as ALD, which is suitable for the three-dimensional gate structure of FinFET. The amount of deposited impurities can be precisely controlled by parameters such as plasma power and gas flow rate during the deposition process; in addition, the PEALD In-situ doping can achieve surface deposition and the amount of impurities required in the deposition process is small, so the plasma power can be greatly reduced, and it is less destructive to the surface structure of the gate than ion implantation.

Further, step S20 is executed. In step S20, the second doped layer is also deposited by PEALD, specifically, a layer of TiN is deposited, and a dopant that can reduce the effective work function, such as P, is doped by an in-situ doping method, as shown in Figure 6 shown.

In order to facilitate etching, the accuracy of etching is improved. In this embodiment, a layer of etching barrier layer may be deposited after step S20 and before step S30, as shown in FIG. 7 . Specifically, an etch stop layer is deposited on the first region, the second region, the third region and the fourth region. In the first region, the second region, the third region and the fourth region, the etching barrier layer is in contact with the second doped layer. The etch stop layer may be TaN (tantalum nitride).

Further, step S30 is executed. In step S30, a first layer of TiN layer is atomically layer deposited on the etching barrier layer, as shown in FIG. 8 . Then, apply a layer of BARC layer and peel off the BARC layer above the second region and the third region, and then etch away the first layer of TiN layer in these two regions, that is, etch at the TaN layer (etch stop layer) stop, as shown in Figure 9. The BARC layers in the first region and the fourth region are stripped, and then continue to deposit a second TiN layer on the etching barrier layer, as shown in FIG. 10 . Further, coat a layer of BARC layer, peel off the BARC layer in the fourth region, and then etch away the first layer of TiN layer and the second layer of TiN layer in this region, and the etching stops at the TaN layer, as shown in Figure 11 . Finally, clear the remaining BARC layers. Thus, the redundant TiN layer (the first TiN layer and the second TiN layer) in the fourth area can be removed at one time, avoiding multiple cleaning operations of the BARC layer in the fourth area, and simplifying the manufacturing steps . At the same time, through the above operations, two layers of TiN layers can be deposited on the etching barrier layer in the first region to obtain a thicker TiN layer and lower threshold voltage.

Further, step S40 is performed, specifically depositing a TiAl layer, a TiN layer in sequence in the first region, the second region, the third region and the fourth region on the high-K dielectric layer, and finally filling it with metal tungsten, as shown in FIG. 12 .

The following beneficial effects can be achieved by the method in this embodiment:

1. Using the preparation method in this example to manufacture SOI FinFET devices can effectively control the thickness of the gate work function metal without affecting the subsequent metal filling of the gate, ensuring the stability of the gate resistivity of the device . Specifically, in this embodiment, the TiN layer is deposited on the high-K dielectric layer by PEALD, and at the same time, impurities are doped by PEALD in-situ doping method. Impurities that increase the effective work function are doped into the N-type region (the third region and the fourth region) to reduce the effective work function, and the doping amount is controllable, so that the threshold voltage can be controlled. Compared with the method of adjusting the threshold voltage by changing the thickness of the gate work function layer in the prior art, the adjustment range is larger, which solves the problem of manufacturing limitations; for ultra-low threshold voltage P-type FinFET devices, no thick work function is required. The function layer, the gate metal filling problem of P-type devices has been greatly improved.

2. In the prior art, there is the following manufacturing method. The MOS FET device in the high-K metal gate process can adjust the threshold voltage by implanting impurities into the first layer of metal gate. Specifically, a dopant that can increase the effective work function is injected into the first metal gate of the P-type device, and a dopant that can reduce the effective work function is implanted into the metal gate of the N-type device, thereby adjusting the threshold Voltage. On the one hand, the ion implantation doping energy is relatively large, which will cause damage to the metal film, especially for Fin FET devices under advanced process nodes; on the other hand, the work functions of P-type devices and N-type devices Different: The effective work function of P-type devices should be near the top of the valence band of Si, and the work function of N-type devices should be near the bottom of the conduction band of Si; devices of the same type can also be divided into ultra-low threshold voltage devices and Standard threshold voltage devices also have different work function requirements. If it is necessary to form different types of devices with different threshold voltages on one chip, different doping types or metering are required for different devices during gate manufacturing, and it is necessary to separately target P-type low threshold voltage devices and P-type standard threshold voltage devices. , N-type low-threshold-voltage devices, and N-type standard-threshold-voltage devices perform respective deposition, doping, and etching steps, resulting in complex processes and high costs. However, the manufacturing method of the SOI FinFET device in this embodiment adopts PEALD in-situ doping technology, which has lower energy and less damage to the gate surface structure than ion implantation doping; At the same time, when forming the first layer of the metal gate in this method, first deposit TiN and dope the dopant that increases the effective work function required by the P-type device (ie, the first region and the second region), and then etch away the N TiN in the N-type region (that is, the third region and the fourth region), and then TiN is deposited and doped with the dopant required to reduce the effective work function in the N-type region. For the different work function requirements of devices of various threshold voltage types, it is not necessary to measure impurities, but to meet them by subsequently depositing a corresponding thickness of work function metal layer TiN in each region, and finally complete the gate metal filling. For P-type low-threshold voltage devices, P-type standard threshold-voltage devices, N-type low-threshold voltage devices and N-type standard threshold-voltage devices, the thickness of the deposited work function metal layer decreases, thus eliminating the need for multiple depositions, doping, and etching steps, and P-type, N-type low threshold voltage devices, P-type, N-type standard threshold voltage devices can be manufactured on the same chip, so that the manufacturing process greatly reduces the manufacturing cost.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

Claims (10)

1. A soi finfet device, comprising:

a substrate having a source region and a drain region doped to form a set thereon;

any one of a first region, a second region, a third region and a fourth region is arranged above the space between each group of the source region and the drain region; the first region is used for forming a grid electrode of a P-type low threshold voltage device, the second region is used for forming a grid electrode of a P-type standard threshold voltage device, the third region is used for forming a grid electrode of an N-type low threshold voltage device, and the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device;

the first region is sequentially provided with a high-K dielectric layer, a first doping layer, a second doping layer, a TiN layer and a filling layer from bottom to top; the first doping layer is a TiN layer containing a dopant for increasing the effective work function, and the second doping layer is a TiN layer containing a dopant for reducing the effective work function;

the second region is sequentially provided with the high-K dielectric layer, the first doping layer, the second doping layer, the TiN layer and the filling layer from bottom to top;

the third region is sequentially provided with the high-K dielectric layer, the second doping layer, the TiN layer and the filling layer from bottom to top;

the fourth region is sequentially provided with the high-K dielectric layer, the second doping layer and the filling layer from bottom to top.

2. The soi finfet device of claim 1, wherein an etch stop layer is disposed over the second doped layer in any one or more of the first, second, third and fourth regions.

3. The SOI FinFET device of claim 1, wherein a thickness of the TiN layer in the first region is greater than a thickness of the TiN layer in the second region.

4. The SOI FinFET device of claim 1, wherein the fill layer is a TiAl layer, a TiN layer and metal tungsten in sequence from bottom to top.

5. The SOI FinFET device of claim 1, wherein the first doped layer is BF ₂ The second doping layer is a TiN layer of P ions.

6. A method for fabricating a SOFFINFET device, comprising:

depositing a first doping layer on a first region and a second region on a high-K dielectric layer on a substrate; wherein the substrate has a set of source and drain regions, the first and second regions being located above and between the set of source and drain regions, respectively, the first region being for forming a gate of a P-type low threshold voltage device and the second region being for forming a gate of a P-type standard threshold voltage device, wherein the first doped layer is a TiN layer containing a dopant that increases the effective work function;

continuously depositing a second doping layer on the first region, the second region, the third region and the fourth region on the high-K dielectric layer; the second region and the third region are respectively positioned above the grouped source regions and drain regions, the third region is used for forming a grid electrode of an N-type low threshold voltage device, the fourth region is used for forming a grid electrode of an N-type standard threshold voltage device, and the second doping layer is a TiN layer containing a dopant for reducing an effective work function;

continuing to deposit TiN layers on the first region, the second region and the third region on the high-K dielectric layer;

and continuously depositing filling layers in the first area, the second area, the third area and the fourth area on the high-K dielectric layer.

7. The method of claim 6, wherein depositing a first doped layer in the first region and the second region on the high-K dielectric layer on the substrate comprises:

depositing a first doping layer on the high-K dielectric layer on the substrate;

coating a BARC layer on the first doping layer, and stripping the BARC layer of the third area and the fourth area;

and removing the first doping layer in the third region and the fourth region by adopting an etching method.

8. The method of claim 6, wherein after the depositing a second doped layer on the high-K dielectric layer in the first, second, third, and fourth regions and before the depositing a TiN layer on the high-K dielectric layer in the first, second, and third regions, further comprises:

depositing an etch stop layer in the first region, the second region, the third region, and the fourth region.

9. The method of claim 8, wherein depositing a TiN layer on the first, second, and third regions on the high-K dielectric layer comprises:

depositing a first layer of the TiN layer over the etch stop layer;

etching the second region and the third region to the etching barrier layer;

continuously laminating a second TiN layer above the etching barrier layer;

and etching the fourth region to the etching barrier layer.

10. The method of claim 6, wherein depositing a fill layer on the first, second, third, and fourth regions on the high-K dielectric layer comprises:

and sequentially depositing a TiAl layer, a TiN layer and metal tungsten in the first region, the second region, the third region and the fourth region on the high-K dielectric layer.

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