CN111538687A - Memory control method, memory storage device, and memory control circuit unit - Google Patents

Abstract

The invention provides a memory control method, which comprises the following steps: sending a first read command sequence instructing to read a first physical unit using a first read voltage level to obtain first data; decoding the first data; if the first data decoding fails, sending a second read command sequence indicating that the first entity unit is read by using a second read voltage level to obtain second data; if the second read voltage level meets the first condition or the second data meets the second condition, decoding the second data by using the auxiliary information to improve the decoding success rate of the second data; and if the second read voltage level does not meet the first condition and the second data does not meet the second condition, decoding the second data without using the auxiliary information. In addition, the invention also provides a memory storage device and a memory control circuit unit.

Description

Memory control method, memory storage device, and memory control circuit unit

technical field

The present invention relates to a memory control technology, and in particular, to a memory control method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones and MP3 players have grown rapidly over the past few years, resulting in a rapid increase in consumer demand for stored media. Because rewritable non-volatile memory modules (eg, flash memory) have the characteristics of data non-volatility, power saving, small size, and no mechanical structure, they are very suitable for built-in Among the various portable multimedia devices exemplified above.

Some types of memory storage devices support both hard-bit mode decoding and soft-bit mode decoding. Hard-bit mode decoding has a faster decoding speed, while soft-bit mode decoding has a higher decoding success rate. In hard bit mode decoding, whenever decoding fails, the read voltage level used to read the memory cells in the rewritable non-volatile memory module can be adjusted with reference to the reread table, and the adjusted read voltage level The voltage levels can be used to reread data (also known as hard bits). Once the number of retries for hard-bit mode decoding exceeds a predetermined value, soft-bit mode decoding can be performed. In soft bit mode decoding, more read voltage levels can be used to read memory cells to obtain additional information about the hard bits (also known as soft bits) to improve decoding by importing the additional information Success rate.

However, for the rewritable non-volatile memory module with serious voltage offset, the decoding success rate of hard-bit mode decoding is low, so that the system needs to spend a lot of time waiting for the end of hard-bit mode decoding before the soft-bit mode is completed. The data is successfully decoded during decoding.

SUMMARY OF THE INVENTION

The present invention provides a memory control method, a memory storage device and a memory control circuit unit, which can effectively improve the decoding success rate of data in hard bit mode decoding.

Exemplary embodiments of the present invention provide a memory control method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control method includes: sending a first read instruction sequence, which instructs to read a first physical unit of the plurality of physical units using a first read voltage level to obtain first data; decoding the first physical unit data; if the decoding of the first data fails, a second read command sequence is sent, which instructs the first physical unit to be read using a second read voltage level to obtain second data, wherein the second read The voltage level is different from the first read voltage level; if the second read voltage level meets the first condition or the second data meets the second condition, use auxiliary information to decode the second data , wherein the auxiliary information is used to improve the decoding success rate of the second data; and if the second read voltage level does not meet the first condition and the second data does not meet the second condition , the second data is decoded without using the auxiliary information.

In an exemplary embodiment of the present invention, the memory control method further includes: according to whether the second read voltage level is within a specific voltage range, determining whether the second read voltage level conforms to the first condition.

In an exemplary embodiment of the present invention, the memory control method further includes: obtaining a syndrome value of the second data, wherein the syndrome value is related to a bit error rate of the second data; and determining whether the second data meets the second condition according to whether the syndrome value is less than a preset value.

In an exemplary embodiment of the present invention, the memory control method further includes: before sending the first read command sequence, sending a third read command sequence, which instructs to use a third read voltage level to read fetching the first physical unit to obtain third data; decoding the third data; and determining a specific voltage range according to the first read voltage level and the third read voltage level, wherein the first read voltage level One of a read voltage level and the third read voltage level is used to define the upper boundary of the specific voltage range, and the first read voltage level and the third read voltage level The other of the levels is used to define the lower boundary of the specific voltage range.

In an exemplary embodiment of the present invention, the memory control method further includes: updating the boundary of the specific voltage range according to the second read voltage level.

In an exemplary embodiment of the present invention, the step of updating the boundary value of the specific voltage range according to the second read voltage level includes: according to the second read voltage level and the specific voltage The relative relationship of the ranges determines whether to update the boundaries of the particular voltage range.

In an exemplary embodiment of the present invention, the memory control method further includes: if the second read voltage level meets the first condition or the second data meets the second condition, according to the The first read voltage level and the second read voltage level are divided into a plurality of voltage intervals; and the auxiliary information is determined according to the divided voltage intervals.

Exemplary embodiments of the present invention further provide a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to the host system. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is configured to send a first read command sequence, which instructs to read a first physical unit of the plurality of physical units using a first read voltage level to obtain first data. The memory control circuit unit is further used for decoding the first data. If the decoding of the first data fails, the memory control circuit unit is further configured to send a second read command sequence, which instructs to use the second read voltage level to read the first physical unit to obtain the second data . The second read voltage level is different from the first read voltage level. If the second read voltage level meets the first condition or the second data meets the second condition, the memory control circuit unit is further configured to decode the second data using auxiliary information, wherein the auxiliary information is In order to improve the decoding success rate of the second data. If the second read voltage level does not meet the first condition and the second data does not meet the second condition, the memory control circuit unit is further configured to decode the auxiliary information without using the auxiliary information Second data.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the second read voltage level conforms to the first condition.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to obtain a syndrome value of the second data, where the syndrome value is related to a bit error rate of the second data. The memory control circuit unit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is less than a preset value.

In an exemplary embodiment of the present invention, before sending the first read command sequence, the memory control circuit unit is further configured to send a third read command sequence, which instructs to use a third read voltage level to read The first entity unit is taken to obtain third data. The memory control circuit unit is further used for decoding the third data. The memory control circuit unit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level. One of the first read voltage level and the third read voltage level is used to define an upper boundary of the specific voltage range. The other of the first read voltage level and the third read voltage level is used to define a lower boundary of the specific voltage range.

In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to update the boundary of the specific voltage range according to the second read voltage level.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit updating the boundary value of the specific voltage range according to the second read voltage level includes: according to the second read voltage level A relative relationship between the level and the specific voltage range determines whether to update the boundary of the specific voltage range.

In an exemplary embodiment of the present invention, if the second read voltage level meets the first condition or the second data meets the second condition, the memory control circuit unit is further configured to The first read voltage level and the second read voltage level are divided into a plurality of voltage intervals. The memory control circuit unit is further configured to determine the auxiliary information according to the divided voltage intervals.

Exemplary embodiments of the present invention further provide a memory control circuit unit for controlling a memory storage device. The memory storage device includes a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical units. The memory control circuit unit includes a host interface, a memory interface, a decoding circuit and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface, and the decoding circuit. The memory management circuit is configured to send a first read command sequence, which instructs to read a first physical unit of the plurality of physical units using a first read voltage level to obtain first data. The decoding circuit is used for decoding the first data. If the decoding of the first data fails, the memory management circuit is further configured to send a second read command sequence, which instructs to use the second read voltage level to read the first physical unit to obtain the second data. The second read voltage level is different from the first read voltage level. If the second read voltage level meets the first condition or the second data meets the second condition, the decoding circuit is further configured to decode the second data using auxiliary information, wherein the auxiliary information is used to improve The decoding success rate of the second data. If the second read voltage level does not meet the first condition and the second data does not meet the second condition, the decoding circuit is further configured to decode the second data without using the auxiliary information data.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to determine whether the second read voltage level conforms to the first read voltage level according to whether the second read voltage level is within a specific voltage range. a condition.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to obtain a syndrome value of the second data. The syndrome value is related to the bit error rate of the second data. The memory management circuit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is less than a preset value.

In an exemplary embodiment of the present invention, before sending the first read command sequence, the memory management circuit is further configured to send a third read command sequence, which instructs to use a third read voltage level to read The first entity unit obtains third data. The decoding circuit is also used for decoding the third data. The memory management circuit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level. One of the first read voltage level and the third read voltage level is used to define an upper boundary of the specific voltage range. The other of the first read voltage level and the third read voltage level is used to define a lower boundary of the specific voltage range.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to update the boundary of the specific voltage range according to the second read voltage level.

In an exemplary embodiment of the present invention, the operation of the memory management circuit updating the boundary value of the specific voltage range according to the second read voltage level includes: according to the second read voltage level The relative relationship with the specific voltage range determines whether to update the boundary of the specific voltage range.

In an exemplary embodiment of the present invention, if the second read voltage level meets the first condition or the second data meets the second condition, the memory management circuit is further configured to The first read voltage level and the second read voltage level are divided into a plurality of voltage intervals. The memory management circuit is further configured to determine the auxiliary information according to the divided voltage intervals.

Based on the above, after reading the first physical unit at least once and experiencing at least one decoding failure, the auxiliary information that can improve the decoding success rate of the data is only used when certain conditions are met, rather than unconditional in each re-reading and decoding. use. In this way, under the premise of trying to improve the decoding success rate of data in hard-bit mode decoding, it is possible to avoid reducing the decoding success rate due to excessive use or adjustment of auxiliary information.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention;

2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention;

3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

FIG. 7 is a schematic diagram of a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a hard-bit decoding mode according to an exemplary embodiment of the present invention;

9 is a schematic diagram illustrating a threshold voltage distribution and a read voltage level used in a soft bit decoding mode according to an exemplary embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a specific voltage range according to an exemplary embodiment of the present invention;

11 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention;

12 is a schematic diagram of a parity check operation according to an exemplary embodiment of the present invention;

13 is a schematic diagram of updating the boundary of a specific voltage range according to an exemplary embodiment of the present invention;

14 is a schematic diagram of dividing a plurality of voltage intervals according to a plurality of read voltage levels used in hard-bit mode decoding according to an exemplary embodiment of the present invention;

15 is a schematic diagram of dividing a plurality of voltage intervals according to a plurality of read voltage levels used in hard-bit mode decoding according to an exemplary embodiment of the present invention;

16 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a hard-bit decoding mode according to an exemplary embodiment of the present invention;

17 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention;

18 is a schematic diagram of threshold voltage distribution and read voltage levels used in hard-bit decoding mode according to an exemplary embodiment of the present invention;

19 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention;

20 is a flowchart of a memory control method according to an exemplary embodiment of the present invention;

FIG. 21 is a flowchart of a memory control method according to an exemplary embodiment of the present invention.

Detailed ways

Generally, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIGS. 1 and 2 , the host system 11 generally includes a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , the random access memory 112 , the ROM 113 and the data transmission interface 114 are all connected to a system bus 110 .

In this exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114 . For example, host system 11 may store data to or read data from memory storage device 10 via data transfer interface 114 . In addition, the host system 11 is connected to the I/O device 12 via the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O device 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11 . The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means. The memory storage device 10 may be, for example, a USB flash drive 201 , a memory card 202 , a Solid State Drive (SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (eg, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I/O modules such as a Global Positioning System (GPS) module 205 , a network interface card 206 , a wireless transmission device 207 , a keyboard 208 , a screen 209 , a speaker 210 and the like through the system bus 110 . O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 3 , in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be used therefor Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (Compact Flash, CF) card 33 or an embedded storage device 34. The embedded storage device 34 includes various types of embedded multimedia card (embedded Multi Media Card, eMMC) 341 and/or embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342 and other types to directly connect the memory module to the substrate of the host system on the embedded storage device.

4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention. Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used to connect the memory storage device 10 to the host system 11 . The memory storage device 10 may communicate with the host system 11 through the connection interface unit 402 . In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited to this, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) Interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash memory (Universal Flash) Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 may be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in a hardware type or a solid-state type and perform data writing and reading in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 operations such as fetching and erasing.

The rewritable non-volatile memory module 406 is connected to the memory control circuit unit 404 and used to store data written by the host system 11 . The rewritable non-volatile memory module 406 may be a single level cell (Single Level Cell, SLC) NAND type flash memory module (ie, a flash memory module that can store 1 bit in one memory cell), a multi-level memory module. Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in one memory cell), triple level cell (Triple Level Cell, TLC) NAND flash memory Module (that is, a flash memory module that can store 3 bits in one memory cell), quad-level memory cell (Quad Level Cell, QLC) NAND flash memory module (that is, a memory cell that can store 4 bits of flash memory module) flash memory modules), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits with a change in voltage (also referred to as a threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming the memory cell". Each memory cell in the rewritable non-volatile memory module 406 has multiple storage states as the threshold voltage changes. By applying a read voltage, it is possible to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, memory cells on the same word line can form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming unit on the same word line can be at least classified into a lower physical programming unit and an upper physical programming unit. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is higher than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit Programmable unit reliability.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit in which data is written. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, the physical programming unit may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit region may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory units that are erased together. For example, the physical erasing unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 , a memory interface 506 and an error checking and correction circuit 508 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 operates, these control commands are executed to perform operations such as data writing, reading, and erasing. The following description of the operation of the memory management circuit 502 is equivalent to the description of the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in a solid state. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control commands are programmed into the read-only memory. When the memory storage device 10 operates, the control commands are executed by the microprocessor unit to perform operations such as data writing, reading and erasing.

In another exemplary embodiment, the control commands of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program codes (eg, a system area in the memory module dedicated to storing system data) middle. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store the boot code in the rewritable non-volatile memory module The control instructions in 406 are loaded into the random access memory of memory management circuit 502 . Afterwards, the microprocessor unit will run these control commands to perform operations such as data writing, reading and erasing.

In addition, in another exemplary embodiment, the control commands of the memory management circuit 502 may also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or memory cell groups of the rewritable non-volatile memory module 406 . The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory read circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used to process the data to be written into the rewritable non-volatile memory module 406 and the data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes, respectively, and are used to instruct the rewritable non-volatile memory module 406 to perform the corresponding write, read, and Erase, etc. In an exemplary embodiment, the memory management circuit 502 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 504 is connected to the memory management circuit 502 . Memory management circuitry 502 may communicate with host system 11 through host interface 504 . The host interface 504 can be used to receive and identify commands and data transmitted by the host system 11 . For example, instructions and data transmitted by the host system 11 may be transmitted to the memory management circuit 502 through the host interface 504 . Additionally, the memory management circuit 502 may communicate data to the host system 11 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compliant with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 can also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 506 is connected to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406 . That is, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding command sequence. For example, these instruction sequences may include a write instruction sequence to instruct to write data, a read instruction sequence to instruct to read data, an erase instruction sequence to instruct to erase data, and to instruct various memory operations (eg, change read take a voltage level or perform a garbage collection operation, etc.) These sequences of instructions are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on the bus. These signals or data may include instruction code or program code. For example, in the read command sequence, the read identification code, memory address and other information will be included.

An error checking and correction circuit (also referred to as a decoding circuit) 508 is connected to the memory management circuit 502 and is used to perform error checking and correction operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and and/or an error detecting code (EDC), and the memory management circuit 502 writes the data corresponding to this write instruction and the corresponding error correcting code and/or error checking code to the rewritable non-volatile memory module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the error correction code and/or error check code corresponding to the data, and the error check and correction circuit 508 will This error correction code and/or error checking code performs error checking and correction operations on the read data.

It should be noted that the error checking and correction circuit 508 can support hard bit mode decoding operations and soft bit mode decoding operations. The decoding speed of each decoding operation in hard bit mode is faster than the decoding speed of each decoding operation in soft bit mode. However, the decoding success rate of each decoding operation in the soft-bit mode is higher than the decoding success rate of each decoding operation in the hard-bit mode.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512 . The buffer memory 510 is connected to the memory management circuit 502 and used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is connected to the memory management circuit 502 and used to control the power supply of the memory storage device 10 .

In an exemplary embodiment, the rewritable non-volatile memory module 406 of FIG. 4 is also referred to as a flash memory module, and the memory control circuit unit 404 is also referred to as a flash for controlling the flash memory module. memory controller. In an example embodiment, the memory management circuit 502 of FIG. 5 is also referred to as a flash memory management circuit.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Referring to FIG. 6 , the memory management circuit 502 can logically group the physical units 610( 0 ) to 610(B) of the rewritable non-volatile memory module 406 into the storage area 601 and the replacement area 602 . The physical units 610(0)-610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)-610(B) in the replacement area 602 are used to replace the storage area 601 Damaged solid unit. For example, if the data read from a physical unit contains too many errors to be corrected, the physical unit is considered a damaged physical unit. It should be noted that if there is no available physical erase unit in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 to be in a write protect state, and no data can be written.

In this exemplary embodiment, each physical unit refers to a physical programming unit. However, in another exemplary embodiment, a physical unit may also refer to a physical address, a physical erasing unit, or consists of a plurality of consecutive or discontinuous physical addresses. The memory management circuit 502 configures the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the memory area 601. In this exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logical unit may also refer to a logical programming unit, a logical erasing unit, or is composed of a plurality of consecutive or discontinuous logical addresses. Furthermore, each of logical units 612(0)-612(C) may be mapped to one or more physical units.

The memory management circuit 502 can record the mapping relationship between the logical unit and the physical unit (also referred to as the logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from or write data to the memory storage device 10 , the memory management circuit 502 can perform data access operations to the memory storage device 10 according to the logical-physical address mapping table.

FIG. 7 is a schematic diagram illustrating a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention. Please refer to FIG. 7 , taking a TLC NAND flash memory module as an example, after programming a certain physical unit (also referred to as the first physical unit), the threshold voltage of each programmed memory cell in the first physical unit May belong to one of the states 701-708. For example, if multiple memory cells are programmed to store the bits "111", "011", "001", "000", "010", "110", "100" and "101", respectively, then this These memory cells will belong to states 701-708, respectively. When data stored in these memory cells is to be read, the read voltage levels V1-V7 can be applied to the first physical unit. According to the conduction states of the memory cells in the first physical unit in response to the read voltage levels V1-V7, the state to which each memory cell belongs can be identified, and then the data stored in each memory cell can be obtained.

It should be noted that, in another exemplary embodiment, if an SLC NAND type flash memory module, an MLC NAND type flash memory module or a QLC NAND type flash memory module is taken as an example, the bits stored in each memory cell are may vary. Therefore, there may be more or less states in the threshold voltage distribution of the memory cell, which is not limited by the present invention.

FIG. 8 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a hard-bit decoding mode according to an exemplary embodiment of the present invention. Referring to FIG. 8 , states 801 and 802 may be any two adjacent states in FIG. 7 . Depending on the usage environment (eg, ambient temperature) and/or the degree of usage (eg, usage time), there may be an overlap between states 801 and 802, so that subsequent data read from this overlapping area has a high chance of containing erroneous bits .

In hard-bit decoding mode, memory management circuit 502 may send a read command sequence that instructs rewritable non-volatile memory module 406 to use a read voltage level (eg, read voltage level VR ₍₁₎ ) to read the first entity unit. The memory management circuit 502 can obtain data reflecting the read result of this read voltage level. Error checking and correction circuitry 508 can decode this data. If decoding of this data is successful, the successfully decoded data may be output (eg, transmitted to the host system). If decoding of this data fails, memory management circuit 502 may send another read command sequence that instructs rewritable non-volatile memory module 406 to use another read voltage level (eg, read voltage level _{VR (2)} ) Read the first entity unit. The memory management circuit 502 can obtain data reflecting the read result of this read voltage level. Error checking and correction circuitry 508 can decode this data.

And so on, in hard-bit decoding mode, before the number of retries exceeds a retry threshold, whenever decoding fails, the next different read voltage level (eg read voltage level VR ₍₃₎ and /or the read voltage level VR ₍₄₎ ) can be used again to read the first physical unit, and the read data can be decoded. In addition, the information of the read voltage level used in the hard bit decoding mode may be recorded in a retry table. According to this retry table, multiple read voltage levels (eg, read voltage levels VR ₍₁₎ ˜VR ₍₄₎ ) can be used sequentially in the hard-bit decoding mode.

In an exemplary embodiment, if the number of retries in the hard-bit decoding mode exceeds the retry threshold, it means that the decoding capability of the hard-bit decoding mode cannot correct all errors in the read data. Therefore, the error checking and correction circuit 508 can enter a soft bit decoding mode to improve the decoding ability of the data.

FIG. 9 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a soft bit decoding mode according to an exemplary embodiment of the present invention. Referring to FIG. 9, in the soft-bit decoding mode, the memory management circuit 502 may send multiple read command sequences, which instruct the rewritable non-volatile memory module 406 to use multiple read voltage levels (eg, read voltage The levels V _S(1) ˜V _S(5) ) read the first physical unit. Memory management circuitry 502 may obtain data reflecting read results of such read voltage levels. According to the reading results of the reading voltage levels, the threshold voltage of each memory cell can be identified as belonging to one of a plurality of voltage intervals (eg, the voltage intervals 901 to 906 ) and assigned corresponding reliability information. Taking the log similarity ratio (Log Likelihood Ratio, LLR) as an example of the reliability information, the value of the reliability information corresponding to the voltage interval to the left is smaller.

After the reliability information corresponding to each voltage interval is determined according to the reading results of the read voltage levels, the error checking and correction circuit 508 can use the corresponding reliability information to decode and use the voltage interval to which each memory cell belongs. A particular read voltage level reads data from these memory cells. For example, this particular read voltage level is also referred to as a signed read voltage level and is used to preliminarily determine whether the bit read from each memory cell is a "0" or a "1". Taking FIG. 9 as an example, the specific read voltage level may be the read voltage level VS ₍₁₎ .

From another perspective, in the hard-bit decoding mode of FIG. 8 , each time a read voltage level is applied, the data reflecting the read result of the read voltage level is decoded once. However, in the soft-bit decoding mode of FIG. 9 , data reflecting the read result of a specific read voltage level is decoded only once after a plurality of read voltage levels are continuously applied.

Traditionally, each decoding in the hard-bit decoding mode only decodes the data obtained by each application of the read voltage level, unlike the soft-bit decoding mode, which is dynamically generated or updated to improve decoding success. rate reliability information. Therefore, the decoding success rate of the hard-bit decoding mode is generally low. In the case where the critical voltage shift of the memory cell is severe, the system may need to wait until all read voltage levels in the hard-bit decoding mode have been used before entering the soft-bit decoding mode, resulting in prolonged decoding time.

In an example embodiment, in hard-bit decoding mode, the memory management circuit 502 may send a read command sequence (also referred to as the first read command sequence) that instructs the use of a read voltage level (also referred to as The first read voltage level) reads the first physical unit to obtain a data (also referred to as first data). The first data can reflect the read result of each memory cell in the first physical unit by the first read voltage level. The error checking and correction circuit 508 can decode the first data. If the decoding of the first data is successful, the successfully decoded first data may be output.

If the decoding of the first data fails, the memory management circuit 502 may send another read command sequence (also referred to as a second read command sequence) that instructs the use of another read voltage level (also referred to as a second read) voltage level) to read the first physical unit to obtain another data (also referred to as second data). The second data can reflect the read result of each memory cell in the first physical unit by the second read voltage level. The second read voltage level is different from the first read voltage level. Taking FIG. 8 as an example, the first reading voltage level and the second reading voltage level may be any two of the reading voltage levels VR ₍₁₎ -VR ₍₄₎ .

After obtaining the second data, the memory management circuit 502 can determine whether the second read voltage level meets a specific condition (also referred to as a first condition) and/or whether the second data meets a specific condition (also referred to as a second condition) condition). If the second read voltage level meets the first condition or the second data meets the second condition, the error checking and correction circuit 508 may decode the second data using the auxiliary information. The auxiliary information can be used to improve the decoding success rate of the second data. For example, the auxiliary information may include dynamically determined reliability information corresponding to a plurality of voltage intervals (similar to the dynamically determined reliability information in the exemplary embodiment of FIG. 9 ). After importing the auxiliary information to decode the second data, even in the hard-bit decoding mode, the decoding success rate of the second data can be significantly improved.

However, if the second read voltage level does not meet the first condition and the second data does not meet the second condition, the error checking and correction circuit 508 may decode the second data without using this auxiliary information. For example, if the second read voltage level does not meet the first condition and the second data does not meet the second condition, the error checking and correction circuit 508 can maintain the predetermined decoding operation in the hard-bit decoding mode to decode the second data, Without additional reference to dynamically determined reliability information. In other words, by appropriately and correctly using the auxiliary information in the hard-bit decoding mode, it is also possible to avoid excessive use or adjustment of the auxiliary information, which may reduce the decoding success rate of the data.

In an exemplary embodiment, the memory management circuit 502 can determine whether the second read voltage level meets the first condition according to whether the second read voltage level is within a specific voltage range. In an exemplary embodiment, if the second read voltage level is within a specific voltage range, the memory management circuit 502 may determine that the second read voltage level meets the first condition. In an exemplary embodiment, if the second read voltage level is not within a specific voltage range, the memory management circuit 502 may determine that the second read voltage level does not meet the first condition.

FIG. 10 is a schematic diagram illustrating a specific voltage range according to an exemplary embodiment of the present invention. Referring to FIG. 8 and FIG. 10, in an exemplary embodiment, after the read voltage levels VR ₍₁₎ and VR ₍₂₎ are used to read the first physical unit and the data is not successfully decoded, the memory management The circuit 502 can determine the specific voltage range 1010 according to the read voltage levels VR ₍₁₎ and VR ₍₂₎ . For example, the memory management circuit 502 may determine the boundary 1011 of the specific voltage range 1010 according to the read voltage level VR( _{1 )} and determine the boundary 1012 of the specific voltage range 1010 according to the read voltage level VR(2). In other words, the specific voltage range 1010 includes the voltage range between the boundaries 1011 and 1012 .

11 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention. Referring to FIG. 11 , in an exemplary embodiment, after the specific voltage range 1010 is determined, it is assumed that the read voltage level VR ₍₃₎ is used to read the first physical unit (ie, the read voltage level _{VR (3)} is the second read voltage level). In response to the read voltage level VR ₍₃₎ not being within the specific voltage range 1010, the memory management circuit 502 may determine that the read voltage level VR ₍₃₎ does not meet the first condition. In response to the read voltage level VR ₍₃₎ not meeting the first condition, the memory management circuit 502 may instruct the error checking and correction circuit 508 to decode the reflected read voltage level VR ₍ 3) without reference to additional auxiliary information. ₃₎ The data of the read result (ie, the second data).

Or, in another exemplary embodiment, after the specific voltage range 1010 is determined, it is assumed that the read voltage level VR ₍₄₎ is used to read the first physical unit (ie the read voltage level VR _{(4) )} is the second read voltage level). In response to the read voltage level VR ₍₄₎ being within the specified voltage range 1010, the memory management circuit 502 may determine that the read voltage level VR ₍₄₎ meets the first condition. In response to the read voltage level VR ₍₄₎ meeting the first condition, the memory management circuit 502 may instruct the error checking and correction circuit 508 to reference the additional side information to decode the read reflecting the read voltage level VR ₍₄₎ The resulting data (ie, the second data).

In an exemplary embodiment, the memory management circuit 502 can obtain the syndrome value of the second data. The syndrome value is related to the bit error rate of the second data. For example, memory management circuit 502 (or error checking and correction circuit 508) may perform a parity check operation on the second data to obtain a syndrome value for the second data. The memory management circuit 502 can determine whether the second data meets the second condition according to whether the syndrome value is less than a predetermined value. For example, if the syndrome value is smaller than the predetermined value, the memory management circuit 502 may determine that the second data meets the second condition. If the syndrome value is not less than the predetermined value, the memory management circuit 502 may determine that the second data does not meet the second condition.

FIG. 12 is a schematic diagram illustrating a parity check operation according to an exemplary embodiment of the present invention. Referring to FIG. 12 , in an exemplary embodiment, it is assumed that the second data includes a codeword 1202 . The codeword 1202 includes a plurality of bits V ₀ to V ₈ . Memory management circuit 502 (or error checking and correction circuit 508 ) may multiply codeword 1202 by a matrix (also known as a parity check matrix, denoted H) 1201 to obtain syndrome vector 1203 . The syndrome vector 1203 includes a plurality of syndromes S ₀ to S ₇ . If there is no error bit in the codeword 1202, the syndromes S ₀ to S ₇ should all be bits "0". The more bits "1" in the syndromes S ₀ -S ₇ (or the fewer "0" bits in the syndromes S ₀ -S ₇ ), the more erroneous bits in the codeword 1202 may be.

In an exemplary embodiment, the memory management circuit 502 may determine the syndrome value of the second data according to the sum of the syndromes S ₀ -S ₇ . For example, the syndrome value of the second data may reflect the sum of the syndromes S ₀ -S ₇ . For example, the syndrome value of the second data may be positively related to the sum of the syndromes S ₀ ˜ S ₇ . If there are more bits "1" in the syndromes S ₀ -S ₇ (or fewer "0" bits in the syndromes S ₀ -S ₇ ), the syndrome value of the second data is larger.

In an exemplary embodiment, the memory management circuit 502 can update the boundary of the specific voltage range according to the second read voltage level to expand the coverage of the specific voltage range. In an exemplary embodiment, the memory management circuit 502 can determine whether to update the memory according to whether the second read voltage level is within the specific voltage range or the relative relationship between the remaining second read voltage levels and the specific voltage range. the boundaries of the specified voltage range. In this way, the probability that the read voltage level used in the subsequent hard-bit decoding mode meets the first condition can be improved.

FIG. 13 is a schematic diagram of updating the boundary of a specific voltage range according to an exemplary embodiment of the present invention. Referring to FIG. 13 , it is assumed that the read voltage level VR _{( 3 )} is not within the specific voltage range 1010 . After reading the first physical cell using the read voltage level VR ₍₃₎ , the memory management circuit 502 can change the boundary of the specific voltage range 1010 from the boundary 1010 originally corresponding to the read voltage level VR ₍₁₎ Updated to the boundary 1301 corresponding to the read voltage level VR ₍₃₎ , thereby expanding the coverage of the specific voltage range 1010.

In an exemplary embodiment, after it is determined that the second read voltage level meets the first condition or the second data meets the second condition, the memory management circuit 502 can generate a voltage according to the first read voltage level and the second read voltage level. The plurality of voltage intervals are divided equally among the plurality of read voltage levels used at least in part in hard bit mode decoding. Then, the memory management circuit 502 can determine the auxiliary information according to the divided voltage intervals.

FIG. 14 is a schematic diagram of dividing a plurality of voltage intervals according to a plurality of read voltage levels used in hard-bit mode decoding according to an exemplary embodiment of the present invention. Referring to FIG. 14 , in an exemplary embodiment, in response to the read voltage level VR ₍₄₎ meeting the first condition, the memory management circuit 502 may decode the read voltage level VR according to the hard bit pattern used for the read voltage level _{VR (1)} , VR ₍₂₎ and VR ₍₄₎ to divide the voltage intervals 1401-1404.

According to the read results of the read voltage levels VR ₍₁₎ , VR ₍₂₎ and VR ₍₄₎ , the threshold voltage of each memory cell in the first physical unit can be identified as belonging to the voltage range 1401-1404 One of them is given corresponding reliability information. The auxiliary information may include reliability information obtained at this time. Taking the logarithmic similarity ratio (LLR) as an example of the reliability information, the value of the reliability information corresponding to the voltage interval to the left may be smaller. Then, according to the voltage interval to which each memory cell belongs, the error checking and correction circuit 508 can use the corresponding reliability information (ie, the auxiliary information) to decode the reading from these memory cells using the read voltage level VR ₍₄₎ . The data.

In an exemplary embodiment, it is assumed that the data read using the read voltage level VR ₍₁₎ is the third data, the data read using the read voltage level VR ₍₂₎ is the first data, and The data read by the read voltage level VR ₍₄₎ is the second data. The memory management circuit 502 can use the difference between the syndrome value of the third data and the syndrome value of the second data and the read voltage level VR ₍₁₎ and the read voltage level VR ₍₄₎ The difference between them determines the reliability information corresponding to the voltage interval 1402 . For example, the memory management circuit 502 can determine the reliability information corresponding to the voltage interval 1402 according to the following equation (1.1).

LLR(1402)=α×(DIF(A)/DIF(B))+β×DIF(A)+γ×DIF(B)+C

Wherein, DIF(A) corresponds to the difference between the syndrome value of the third data and the syndrome value of the second data, and DIF(B) corresponds to the read voltage level VR ₍₁₎ and the read voltage voltage The difference between flat VR ₍₄₎ . α, β, γ and C are all constants. Similarly, the memory management circuit 502 can use the difference between the syndrome value of the second data and the syndrome value of the first data and the read voltage level VR _{( 4)} and the read voltage level VR The difference between ₍₂₎ determines the reliability information corresponding to the voltage interval 1403 . For example, in an exemplary embodiment, the reliability information corresponding to the voltage intervals 1401 - 1404 may be determined as "-1", "-0.2", "0.4" and "1", respectively.

FIG. 15 is a schematic diagram of dividing a plurality of voltage intervals according to a plurality of read voltage levels used in hard-bit mode decoding according to an exemplary embodiment of the present invention. Referring to FIG. 15, following the exemplary embodiment of FIG. 14, if the decoding of the data read using the read voltage level VR ₍₄₎ still fails, the read voltage level VR ₍₅₎ can be used continuously for reading the first physical unit.

In an exemplary embodiment, in response to the read voltage level VR ₍₅₎ meeting the first condition, the memory management circuit 502 may decode the read voltage levels VR ₍₁₎ , V _R(2) , VR ₍₄₎ and VR ₍₅₎ are divided into voltage intervals 1501-1505.

According to the read results of the read voltage levels VR ₍₁₎ , VR ₍₂₎ , VR ₍₄₎ and VR ₍₅₎ , the threshold voltages of the memory cells in the first physical unit can be identified as belonging to One of the voltage intervals 1501 to 1505 is assigned corresponding reliability information. The auxiliary information may include reliability information obtained at this time. Then, according to the voltage interval to which each memory cell belongs, the error checking and correction circuit 508 can use the corresponding reliability information (ie, the auxiliary information) to decode the reading from these memory cells using the read voltage level VR ₍₅₎ . The data.

In an exemplary embodiment, the memory management circuit 502 may simultaneously consider whether the second read voltage level meets the first condition and the second data meets the second condition to determine whether to use the auxiliary information to decode the second data. In an exemplary embodiment, the memory management circuit 502 may also determine whether to use the auxiliary information to decode the second data only according to whether the second read voltage level meets the first condition or only according to whether the second data meets the second condition. Depends on practical needs.

In the foregoing exemplary embodiments, the data reading of a single reading voltage level is used as an example for description. However, in the following exemplary embodiments, data reading with multiple read voltage levels is used as an example for description.

FIG. 16 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a hard-bit decoding mode according to an exemplary embodiment of the present invention. Referring to FIG. 16, it is assumed that the threshold voltage distribution of the programmed memory cells in the first physical unit includes states 1601-1604. State 1601 is adjacent to 1602, and state 1603 is adjacent to 1604. In hard-bit decoding mode, read voltage levels VR ₍₁₎ and VR ₍₁₎ ', read voltage levels VR ₍₂₎ and VR ₍₂₎ ', or read voltage levels _{VR (3)} and VR ₍₃₎ ' can be simultaneously applied to the first physical unit to read the corresponding data. For example, read voltage levels VR ₍₁₎ and VR ₍₁₎ ', read voltage levels VR ₍₂₎ and VR ₍₂₎ ', or read voltage levels VR ₍₃₎ and V _R(3) ' may correspond to any two read voltage levels in FIG. 7 that can be applied simultaneously (eg, read voltage levels V1 and V2).

In an example embodiment, the memory management circuit 502 may send a read command sequence that instructs the first physical unit to be read using the read voltage levels VR ₍₁₎ and VR ₍₁₎ ' to obtain a reflective read Data of read results of voltage levels VR ₍₁₎ and VR ₍₁₎ '. Error checking and correction circuitry 508 can decode this data. Assuming the decoding of this data fails, the memory management circuit 502 may send a read command sequence that instructs the first physical unit to be read using the read voltage levels VR ₍₂₎ and VR ₍₂₎ ' to obtain a reflective read Data of read results of voltage levels VR ₍₂₎ and VR ₍₂₎ '. Error checking and correction circuitry 508 can decode this data. Assuming that the decoding of this data fails, the memory management circuit 502 may send a read command sequence that instructs the first physical unit to be read using read voltage levels VR ₍₃₎ and VR ₍₃₎ ' to obtain a reflective read Data of read results of voltage levels VR ₍₃₎ and VR ₍₃₎ '.

FIG. 17 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention. 16 and FIG. 17 , in an exemplary embodiment, the memory management circuit 502 can determine the specific voltage range 1710 according to the read voltage levels VR ₍₁₎ and VR ₍₂₎ and according to the read voltage level V _R(1) ' and VR ₍₂₎ ' determine the specific voltage range 1720.

As shown in FIG. 17, the read voltage levels VR ₍₃₎ and VR ₍₃₎ ' are not within the specific voltage ranges 1710 and 1720, so the memory management circuit 502 can determine the read voltage level VR ₍₃₎ and VR ₍₃₎ ' does not meet the first condition. In response to the read voltage levels VR ₍₃₎ and VR ₍₃₎ ' not meeting the first condition, in decoding the read results reflecting the read voltage levels VR ₍₃₎ and VR ₍₃₎ ' data, the error checking and correction circuit 508 will not use auxiliary information.

On the other hand, the memory management circuit 502 can determine whether to update the specific voltage ranges 1710 and 1720 according to the relative relationship between the read voltage levels VR ₍₃₎ and VR ₍₃₎ ′ and the specific voltage ranges 1710 and 1720 boundary. In an exemplary embodiment, the memory management circuit 502 may determine whether to update the specific voltage ranges 1710 and 1720 according to whether the read voltage levels VR ₍₃₎ and VR _(3)' are within the specific voltage ranges 1710 and 1720, respectively. border. For related operations, reference may be made to the exemplary embodiment in FIG. 13 , and details are not repeated here.

In an exemplary embodiment, the memory management circuit 502 can obtain the difference D(1) between the read voltage levels VR ₍₁₎ and VR ₍₂₎ and the read voltage level VR ₍₁₎ ' Difference D(1)' from VR ₍₂₎ '. The memory management circuit 502 can obtain the difference D(2) between the read voltage levels VR(1 ₎ and VR ₍₃ ) and the read voltage levels VR ₍₁₎ ' and VR ₍₃₎ ' The difference between D(2)'. The memory management circuit 502 can determine whether the sum of the differences D(2) and D(2)' is greater than the sum of the differences D(1) and D(1)'. If the sum of the differences D(2) and D(2)' is greater than the sum of the differences D(1) and D(1)', the memory management circuit 502 can update the specific voltage according to the read voltage level VR ₍₃₎ The boundary 1712 of the range 1710 and the boundary 1722 of the particular voltage range 1720 are updated according to the read voltage level VR ₍₃₎ '.

The memory management circuit 502 can obtain the difference D(3 ₎ between the read voltage levels VR ₍₂₎ and VR(3) and the read voltage levels VR ₍₂₎ ' and VR ₍₃₎ ' The difference between D(3)'. The memory management circuit 502 can determine whether the sum of the differences D(3) and D(3)' is greater than the sum of the differences D(1) and D(1)'. If the sum of the differences D(3) and D(3)' is greater than the sum of the differences D(1) and D(1)', the memory management circuit 502 can update the specific voltage according to the read voltage level VR ₍₃₎ The boundary 1711 of the range 1710 and the boundary 1721 of the particular voltage range 1720 are updated according to the read voltage level VR ₍₃₎ '.

As shown in Figure 17, the sum of the differences D(2) and D(2)' is not greater than the sum of the differences D(1) and D(1)' and the sum of the differences D(3) and D(3)' The sum is greater than the sum of the differences D(1) and D(1)', so the memory management circuit 502 can update the boundary 1711 of the specific voltage range 1710 according to the read voltage level VR(3) and according to the read voltage level V _{R(3) R(3)} ' updates the boundary 1721 of the specific voltage range 1720. For example, the memory management circuit 502 may update the left boundary of the particular voltage range 1710 from the boundary 1711 corresponding to the read voltage level VR( ₁ ) to the boundary 1713 corresponding to the boundary read voltage level VR ₍₃₎ , to expand the coverage of the specific voltage range 1710. At the same time, the memory management circuit 502 may update the left boundary of the particular voltage range 1720 from the boundary 1721 corresponding to the read voltage level VR ₍₁₎ ' to the boundary corresponding to the boundary read voltage level VR ₍₃₎ ' 1723 to expand the coverage of a specific voltage range 1710.

FIG. 18 is a schematic diagram illustrating threshold voltage distributions and read voltage levels used in a hard-bit decoding mode according to an exemplary embodiment of the present invention. FIG. 19 is a schematic diagram illustrating a specific voltage range and a plurality of read voltage levels according to an exemplary embodiment of the present invention. Please refer to FIGS. 18 and 19. Compared with the exemplary embodiments of FIGS. 16 and 17, the exemplary embodiments of FIGS. 18 and 19 are based on the read voltage level VR ₍₄₎ and the read voltage level VR _{. (4)} ' to replace the read voltage level VR ₍₃₎ and the read voltage level VR ₍₃₎ ', respectively. For example, the read voltage levels VR ₍₄₎ and VR ₍₄₎ ' may correspond to any two read voltage levels (eg, read voltage levels V1 and V2) in FIG. 7 that can be applied simultaneously.

As shown in FIG. 19, the read voltage levels VR ₍₄₎ and VR ₍₄₎ ' are located in the specific voltage ranges 1910 and 1920, so the memory management circuit 502 can determine the read voltage levels VR ₍₄₎ and VR(4)' VR ₍₄₎ ' meets the first condition. In response to the read voltage levels VR ₍₄₎ and VR ₍₄₎ ' meeting the first condition, the error check and correction circuit 508 may use the auxiliary information to decode the read voltage levels VR _{( 3)} and VR ₍₃₎ 'The data of the read result. How to use the auxiliary information to perform the decoding operation in the hard-bit mode decoding has been described in detail above, and will not be repeated here.

On the other hand, the memory management circuit 502 can determine whether to update the specific voltage ranges 1910 and 1920 according to the relative relationship between the read voltage levels VR ₍₄₎ and VR ₍₄₎ ′ and the specific voltage ranges 1910 and 1920 boundary. In an exemplary embodiment, the memory management circuit 502 may determine whether to update the specific voltage ranges 1910 and 1920 according to whether the read voltage levels VR ₍₄₎ and VR ₍₄₎ ' are within the specific voltage ranges 1910 and 1920, respectively. border. For related operations, reference may be made to the exemplary embodiment in FIG. 13 , and details are not repeated here.

In an example embodiment, the memory management circuit 502 can obtain the difference D(4 ₎ between the read voltage levels VR ₍₁₎ and VR(4) and the read voltage level VR ₍₁₎ ' Difference D(4)' from VR ₍ 4)'. The memory management circuit 502 can determine whether the sum of the differences D(4) and D(4)' is greater than the sum of the differences D(1) and D(1)'. If the sum of the differences D(4) and D(4)' is greater than the sum of the differences D(1) and D(1)', the memory management circuit 502 can update the specific voltage according to the read voltage level VR ₍₄₎ The boundary 1912 of the range 1910 and the boundary 1922 of the particular voltage range 1920 are updated according to the read voltage level VR ₍₄₎ '.

The memory management circuit 502 can obtain the difference D(5) between the read voltage levels VR(2 ₎ and VR ₍₄ ) and the read voltage levels VR ₍₂₎ ' and VR ₍₄₎ ' The difference between D(5)'. The memory management circuit 502 can determine whether the sum of the differences D(5) and D(5)' is greater than the sum of the differences D(1) and D(1)'. If the sum of the differences D(5) and D(5)' is greater than the sum of the differences D(1) and D(1)', the memory management circuit 502 can update the specific voltage according to the read voltage level VR ₍₄₎ The boundary 1911 of the range 1910 and the boundary 1921 of the particular voltage range 1920 are updated according to the read voltage level VR ₍₄₎ '.

As shown in Figure 19, the sum of the differences D(4) and D(4)' is not greater than the sum of the differences D(1) and D(1)' and the sum of the differences D(5) and D(5)' The sum is not greater than the sum of the differences D( 1 ) and D( 1 )′, so the memory management circuit 502 may not update the specific voltage ranges 1910 and 1920 to avoid narrowing the coverage of the specific voltage ranges 1910 and 1920 .

FIG. 20 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to FIG. 20, in step S2001, a first read command sequence is sent, which instructs to read the first physical unit using the first read voltage level to obtain the first data. In step S2002, the first data is decoded. In step S2003, it is determined whether the decoding of the first data is successful. If the decoding of the first data is successful, in step S2004, output the successfully decoded first data. If the decoding of the first data fails, in step S2005, a second read command sequence is sent, which instructs to use the second read voltage level to read the first physical unit to obtain the second data. The second read voltage level is different from the first read voltage level.

In step S2006, it is determined whether the second read voltage level meets the first condition or whether the second data meets the second condition. If the second read voltage level meets the first condition or the second data meets the second condition, in step S2007, the auxiliary information is used to decode the second data. The auxiliary information is used to improve the decoding success rate of the second data. If the second read voltage level does not meet the first condition and the second data does not meet the second condition, in step S2008, the second data is decoded without using the auxiliary information.

FIG. 21 is a flowchart of a memory control method according to an exemplary embodiment of the present invention. Referring to FIG. 21, in step S2101, hard bit mode decoding (also referred to as hard decoding mode) is started. In step S2102, a read instruction sequence is sent, which instructs to read the first physical unit to obtain data. This data can reflect the read result of the used read voltage for the first physical unit. In step S2103, it is judged whether a preset condition is met or satisfied. For example, the preset condition may include whether the used read voltage meets the first condition and/or whether the read data meets the second condition. If the used read voltage meets the first condition and/or the read data meets the second condition, it can be determined that the preset condition is met or satisfied. If the used read voltage does not meet the first condition and the read data does not meet the second condition, it can be determined that the preset condition is not met or not met.

If the preset condition is met or satisfied, in step S2104, the read data is decoded using the auxiliary information. The auxiliary information is used to improve the decoding success rate of the data. If the preset condition is not met or not met, in step S2105, the read data is decoded without using the auxiliary information. In step S2106, it is determined whether the decoding is successful. If the decoding is successful, in step S2107, output the successfully decoded data. If the decoding is unsuccessful, in step S2108, it is determined whether the number of times the decoding is performed exceeds a retry threshold. If the number of decoding executions does not exceed the retry threshold, in step S2109, adjust the read voltage level used next time and return to step S2102 to read the first physical unit again using the adjusted read voltage level. If the number of times to perform decoding exceeds the retry threshold, in step S2110, the hard decoding mode is exited and soft-bit mode decoding (also referred to as soft-bit mode) is started.

However, each step in FIG. 20 and FIG. 21 has been described in detail as above, and will not be repeated here. It should be noted that each step in FIG. 20 and FIG. 21 can be implemented as multiple program codes or circuits, which is not limited by the present invention. In addition, the methods of FIG. 20 and FIG. 21 can be used in conjunction with the above exemplary embodiments, and can also be used alone, which is not limited in the present invention.

To sum up, in hard-bit mode decoding, after reading the first entity unit at least once and experiencing at least one decoding failure, the auxiliary information that can improve the decoding success rate of the data is only used when certain conditions are met, not Unconditionally used in every reread and decode. In this way, under the premise of trying to improve the decoding success rate of data in hard-bit mode decoding, it is possible to avoid reducing the decoding success rate due to excessive use or adjustment of auxiliary information.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.

Claims (21)

1. A memory control method, characterized in that it is used in a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and the memory control method comprises: sending a first read command sequence, which instructs to read a first physical unit of the plurality of physical units using a first read voltage level to obtain first data; decoding the first data; If the decoding of the first data fails, a second read command sequence is sent, which instructs the first physical unit to be read using a second read voltage level to obtain second data, wherein the second read voltage a level different from the first read voltage level; If the second read voltage level meets the first condition or the second data meets the second condition, the second data is decoded using auxiliary information, wherein the auxiliary information is used to improve decoding of the second data success rate; and If the second read voltage level does not meet the first condition and the second data does not meet the second condition, the second data is decoded without using the auxiliary information. 2. The memory control method according to claim 1, further comprising: Whether the second read voltage level meets the first condition is determined according to whether the second read voltage level is within a specific voltage range. 3. The memory control method according to claim 1, further comprising: obtaining a syndrome value for the second data, wherein the syndrome value is related to a bit error rate of the second data; and Whether the second data meets the second condition is determined according to whether the syndrome value is less than a preset value. 4. The memory control method of claim 1, further comprising: before sending the first read command sequence, sending a third read command sequence, which instructs to read the first physical unit using a third read voltage level to obtain third data; decoding the third data; and A specific voltage range is determined according to the first read voltage level and the third read voltage level, wherein one of the first read voltage level and the third read voltage level is used for to define the upper boundary of the specific voltage range, and the other one of the first read voltage level and the third read voltage level is used to define the lower boundary of the specific voltage range. 5. The memory control method of claim 4, further comprising: The boundaries of the specific voltage range are updated according to the second read voltage level. 6. The memory control method of claim 5, wherein the step of updating the boundary value of the specific voltage range according to the second read voltage level comprises: Whether to update the boundary of the specific voltage range is determined according to the relative relationship between the second read voltage level and the specific voltage range. 7. The memory control method of claim 1, further comprising: If the second read voltage level meets the first condition or the second data meets the second condition, the division is performed according to the first read voltage level and the second read voltage level multiple voltage ranges; and The auxiliary information is determined according to the divided voltage intervals. 8. A memory storage device, comprising: a connection interface unit for connecting to a host system; a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units; and a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is configured to send a first read command sequence, which instructs to use a first read voltage level to read a first physical unit of the plurality of physical units to obtain the first data, The memory control circuit unit is further used for decoding the first data, If the decoding of the first data fails, the memory control circuit unit is further configured to send a second read command sequence, which instructs to use the second read voltage level to read the first physical unit to obtain the second data , wherein the second read voltage level is different from the first read voltage level, If the second read voltage level meets the first condition or the second data meets the second condition, the memory control circuit unit is further configured to decode the second data using auxiliary information, wherein the auxiliary information is to improve the decoding success rate of the second data, and If the second read voltage level does not meet the first condition and the second data does not meet the second condition, the memory control circuit unit is further configured to decode the auxiliary information without using the auxiliary information Second data. 9. The memory storage device of claim 8, wherein the memory control circuit unit is further configured to determine the second read voltage level according to whether the second read voltage level is within a specific voltage range whether the first condition is met. 10. The memory storage device according to claim 8, wherein the memory control circuit unit is further configured to obtain a syndrome value of the second data, the syndrome value and the bit error of the second data rate related, and The memory control circuit unit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is less than a preset value. 11. The memory storage device of claim 8, wherein prior to sending the first sequence of read instructions, the memory control circuit unit is further configured to send a third sequence of read instructions indicating use of a third read instruction the voltage level reads the first physical unit to obtain third data, the memory control circuit unit is further used to decode the third data, and The memory control circuit unit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level, wherein the first read voltage level and the third read voltage level One of the voltage levels is taken to define the upper boundary of the specific voltage range, and the other of the first read voltage level and the third read voltage level is used to define the Lower boundary of a specific voltage range. 12. The memory storage device of claim 11, wherein the memory control circuit unit is further operative to update the boundary of the specific voltage range according to the second read voltage level. 13. The memory storage device of claim 12, wherein the operation of the memory control circuit unit to update the boundary value of the specific voltage range according to the second read voltage level comprises: Whether to update the boundary of the specific voltage range is determined according to the relative relationship between the second read voltage level and the specific voltage range. 14. The memory storage device of claim 8, wherein if the second read voltage level meets the first condition or the second data meets the second condition, the memory control circuit unit further for dividing a plurality of voltage intervals according to the first read voltage level and the second read voltage level, and The memory control circuit unit is further configured to determine the auxiliary information according to the divided voltage intervals. 15. A memory control circuit unit, characterized in that it is used to control a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, and the rewritable non-volatile memory module comprises a plurality of physical units, and the memory control circuit unit includes: a host interface for connecting to a host system; a memory interface for connecting to the rewritable non-volatile memory module; a decoding circuit; and a memory management circuit connected to the host interface, the memory interface and the decoding circuit, wherein the memory management circuit is configured to send a first read command sequence, which instructs to use a first read voltage level to read a first physical unit of the plurality of physical units to obtain the first data, the decoding circuit is used for decoding the first data, If the decoding of the first data fails, the memory management circuit is further configured to send a second read command sequence, which instructs to use the second read voltage level to read the first physical unit to obtain the second data, wherein the second read voltage level is different from the first read voltage level, If the second read voltage level meets the first condition or the second data meets the second condition, the decoding circuit is further configured to decode the second data using auxiliary information, wherein the auxiliary information is used to improve the decoding success rate of the second data, and If the second read voltage level does not meet the first condition and the second data does not meet the second condition, the decoding circuit is further configured to decode the second data without using the auxiliary information data. 16. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to determine the second read voltage level according to whether the second read voltage level is within a specific voltage range whether the first condition is met. 17. The memory control circuit unit of claim 15, wherein the memory management circuit is further configured to obtain a syndrome value of the second data, the syndrome value and the bit error of the second data rate related, and The memory management circuit is further configured to determine whether the second data meets the second condition according to whether the syndrome value is less than a preset value. 18. The memory control circuit unit of claim 15, wherein prior to sending the first read command sequence, the memory management circuit is further configured to send a third read command sequence indicating that a third read command is to be used The voltage level reads the first physical unit to obtain the third data, the decoding circuit is also used to decode the third data, and The memory management circuit is further configured to determine a specific voltage range according to the first read voltage level and the third read voltage level, wherein the first read voltage level and the third read voltage level One of the voltage levels is used to define the upper boundary of the specific voltage range, and the other of the first read voltage level and the third read voltage level is used to define the specific voltage range Lower boundary of the voltage range. 19. The memory control circuit unit of claim 18, wherein the memory management circuit is further operative to update the boundary of the specific voltage range according to the second read voltage level. 20. The memory control circuit unit of claim 19, wherein the operation of the memory management circuit to update the boundary value of the specific voltage range according to the second read voltage level comprises: Whether to update the boundary of the specific voltage range is determined according to the relative relationship between the second read voltage level and the specific voltage range. 21. The memory control circuit unit of claim 15, wherein if the second read voltage level meets the first condition or the second data meets the second condition, the memory management circuit further for dividing a plurality of voltage intervals according to the first read voltage level and the second read voltage level, and The memory management circuit is further configured to determine the auxiliary information according to the divided voltage intervals.

Images